133 results about "Voltage swing" patented technology

Amplification circuitry is disclosed that couples neutralization transistors to amplification transistors to neutralize parasitic capacitance of the amplification transistors. Gates of a first amplification transistor and a first neutralization transistor are coupled together, and gates of a second amplification transistor and a second neutralization transistor are also coupled together. Drains of the first amplification transistor and the second neutralization transistor are coupled together, and drains of the second amplification transistor and the first neutralization transistor are also coupled together. Sources of neutralization transistors are coupled together at a node, such that a voltage swing of a first signal in the first neutralization transistor may be canceled by a voltage swing of a second signal in the second neutralization transistor. The node also couples to a resistor that prevents charge building in the neutralization transistors.

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

The invention relates to a simple multi-parameter testing method for an integrated operational amplifier, which comprises the following steps of: 1) configuring the operational amplifier as a follower circuit, and short-circuiting the inverting input end of the operational amplifier and the output end VOUT; and 2) different excitation signals are respectively given to the in-phase input end VIN of the follower circuit, and parameters such as offset voltage VOS, quiescent current IQ, power supply rejection ratio PSRR, maximum input voltage range IVR, output voltage swing VO, slew rate SR, setup time ST and unity gain bandwidth product UGBW are tested. According to the invention, a common operational amplifier is configured as a follower circuit, so that simple testing of parameters such as offset voltage VOS, quiescent current IQ, power supply rejection ratio PSRR, maximum input voltage range IVR, output voltage swing VO, slew rate SR, establishment time ST, unity gain bandwidth product UGBW and the like can be completed.

The invention discloses a power switch MOS tube driving power supply protection circuit, and the circuit comprises a driving amplitude detection module which is used for sampling and monitoring the voltage swing of power switch MOS tube driving power supply in real time; the driving amplitude limiting module is configured to be used for limiting the voltage swing which is externally provided for driving and supplying power to the power switch MOS tube, so that the voltage swing does not exceed a preset threshold value; and the driving amplitude response module is used for receiving and processing the control signal of the driving amplitude detection module and outputting a feedback signal with loading capacity to the inside and the outside simultaneously. When the swing of the power supply voltage externally provided for the power switch MOS tube drive is unstable, the drive amplitude detection module is used for sampling and detecting the power supply voltage in real time, and then the drive amplitude response module is used for processing signals and feeding back whether the power supply information meets the protection action triggering requirement or not to the outside. And meanwhile, reasonable voltage limiting protection measures are implemented through the driving amplitude limiting module, so that the safe operation of the power switch MOS tube is ensured.

A level shifter includes an input circuit configured to invert an input voltage to output a first inverted voltage and a second inverted voltage, wherein the input voltage swings between a first ground voltage and a first power supply voltage, a protection circuit including at least one pair of transistors sharing a gate terminal to adjust, based on the first inverted voltage and the second inverted voltage, one of a first intermediate voltage and a second intermediate voltage of the protection circuit. a cross-coupling circuit configured to adjust the other of the first intermediate voltage and the second intermediate voltage, and an output circuit configured to invert the first intermediate voltage to output an output voltage that swings between a second ground voltage and a second power supply voltage.

Systems, methods, and apparatuses can detect whether an electrical cable between a source device and a sink device has become disconnected. The source device and / or the sink device can be compliant with a version of a Universal Serial Bus (USB) standard, for example, USB 3.x. These systems, methods, and apparatuses can monitor peak voltage swings of data signals flowing between the source device and the sink device. The peak voltage swing of these data signals can be at a first value when the electrical cable is connected to the source device and the sink device or at a second value greater than the first value when the electrical cable is disconnected from the source device or the sink device. The peak voltage swing can switch from the first value to the second value in response to the electrical cable being disconnected from the source device or the sink device. As such, these systems, methods, and apparatuses can determine that the electrical cable has become disconnected from the source device or the sink device in response to detecting the second value for the peak voltage swing of the data signals flowing from the source device to the sink device.

To reduce the area requirements for sensing circuits of 3D NAND-based vector-matrix multiplication circuitry where weight values for a neural network are stored differentially as current levels on pairs of memory cells, techniques are presented for reducing the common mode current levels during sensing operations. When discharging a first capacitor through a first of a memory cell of a pair of memory cells storing a weight value by a first bit line and discharging second capacitor through a second memory cell of the pair by a second bit line, a reference current is applied to the bit lines. The product of a weight value with an input vector values is then determined by comparing the voltage levels on the two capacitors. The use of the reference current reduces the amount of voltage swing in the two capacitors, reducing the size requirements for the capacitors.

A system includes a voltage-controlled oscillator (VCO), a first second-order harmonic filter coupled to the VCO, wherein the first second-order harmonic filter includes a first tunable capacitor, and a second second-order harmonic filter coupled to the VCO, wherein the second second-order harmonic filter includes a second tunable capacitor. The system also includes a measurement circuit coupled to the VCO, wherein the measurement circuit is configured to measure a voltage swing of the VCO. The system also includes a control circuit coupled to the measurement circuit, the first tunable capacitor, and the second tunable capacitor.

The application provides a common-source common-gate amplifier, comprising a signal input module, which is used for generating an input signal according to a power supply voltage; a cross-coupling module, which is electrically connected with the signal input module and is used for forming internal positive feedback according to an output signal; a first biasing module, which is electrically connected with the cross-coupling module; a first branch module, which is electrically connected with the first biasing module; a second biasing module, which is electrically connected with the cross-coupling module; a second branch module, which is electrically connected with the second biasing module; wherein the first biasing module and the second biasing module are used for providing biasing after an input common-mode feedback voltage, the first branch module and the second branch module are used for providing large-swing output biasing, and the first branch module and the second branch module are respectively electrically connected with the signal input module, and the signal input module is further used for outputting branch signals to the first branch module and the second branch module. The application improves the voltage swing, the gain and the bandwidth of the circuit under the single-stage amplifier structure.

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

Embodiments according to the present disclosure relate to semiconductor switches with ESD protection circuits. In the following a clamping circuit for protection against ESD events is described. According to one embodiment the circuit has a first transistor with a control terminal and a load current path, the first transistor being connected between a first contact and a second contact, an amplifier circuit with an amplifier input and an amplifier output, the amplifier circuit being connected with the control terminal of the transistor, and a trigger circuit connected between the first contact and the second contact and having a second transistor. The trigger circuit is designed to generate a voltage swing at the amplifier input in response to a discharge current at the first contact by driving a control terminal of the second transistor with at least a part of the discharge current through an intrinsic capacitance of the second transistor.

The application discloses a transistor device, a semiconductor epitaxial structure and a preparation method thereof. The transistor device comprises a substrate, a compound semiconductor composite structure generating a two-dimensional electron gas, which is arranged on the substrate; a first cap layer arranged on the compound semiconductor composite structure; an insertion layer arranged on the first cap layer; a second cap layer arranged on the insertion layer; the band gap of the material of the insertion layer is greater than the band gap of the material of the first cap layer and the second cap layer; along the direction from the first cap layer to the second cap layer, the band gap of the material of the insertion layer first increases and then decreases; and a gate metal arranged on the second cap layer. In this way, the on-state gate leakage is reduced, the gate voltage resistance and the voltage swing of the device are increased, and the gate reliability of the device is improved.

Embodiments herein relate to a driver circuit for an optical modulator such as a micro-ring modulator (MRM). The driver circuit includes first and second drivers which receive respective differential data signals, and which have their output nodes coupled to a cathode and anode, respectively of the MRM. One or both of the drivers can have their output nodes alternating-current (AC)-coupled to a bias circuit which biases the voltage of the output signal to shift its voltage swing. The bias circuit can include a latch which receives Vbc_high at its power supply terminal and Vbc_low at its ground terminal, where Vbc_high>Vbc_low>0 V.

The present invention relates to the field of integrated circuit technology, and more particularly to an LVDS transmitter with slew control. The present invention utilizes the characteristics of resistor and capacitor delay to output a portion of the data signal output by the LVDS circuit after a delay controlled by slew control resistors (RD1 and RD2) and the parasitic capacitance of the gate of the switch tube (M3 and M4). This process absorbs the external load resistor R L The reflection of the output signal (OUTN and OUTP) is then controlled to control the voltage swing of the output signal. On the one hand, the introduction of the slew control circuit does not increase the extra power consumption of the circuit. On the other hand, the introduction of the slew control circuit can improve the ringing phenomenon of the signal at the inversion point. Secondly, due to the use of a much larger than R L RCM1 and RCM2 thus avoid increasing the current flowing through the internal matching resistor, thereby reducing the power consumption of the transmitter. Ultimately, the present invention solves the ringing phenomenon while reducing the power consumption of the LVDS transmitter.

An RFA (radio frequency amplifier) includes an NCSA (N-type common-source amplifier) established upon a first source node and configured to receive a first signal and output a first internal current; a first NCGA (N-type common-gate amplifier) configured to receive the first internal current and output a second internal current; a second NCGA configured to receive the second internal current and output a first output current; a PCSA (P-type common-source amplifier) established upon a second source node and configured to receive a second signal and output a third internal current; a first PCGA (P-type common-gate amplifier) configured to receive the third internal current and output a fourth internal current; a second PCGA configured to receive the fourth internal current and output a second output current; and a load network comprising a parallel connection of a primary inductor and a tuning capacitor configured to establish an output signal.

According to one embodiment, a method, computer system, and computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system is provided. The present invention may include training a neural network, recording, in real time, lane input data of PCIe lanes comprising a PCIe link, generating eye diagrams representing the PCIe lanes based on the lane input data, predicting, by the trained neural network, predicted eye heights for the PCIe lanes, and adjusting a current output swing voltage of one or more PCIe lanes based on the predicted eye heights.

The embodiment of the present application provides an output stage circuit and an operational amplifier, which comprises: a first input end and a second input end for being connected with an input stage circuit; an output end for providing an output signal; a first power supply node for being connected with a first power supply; a second power supply node for being connected with a second power supply; a first transistor connected in a pull-up current path; wherein the pull-up current path extends from the first power supply node to the output end; a gate of the first transistor is connected with the first input end; a second transistor connected in a pull-down current path; wherein the pull-down current path extends from the output end to the second power supply node; a gate of the second transistor is connected with the second input end; a cascade transistor module is vertically connected with the first transistor in the pull-up current path and / or is vertically connected with the second transistor in the pull-down current path. In this way, the output voltage swing of the output stage circuit is improved without changing the first transistor and the second transistor.

The invention provides an analog-to-digital converter driving stage control circuit, which comprises an in-phase and out-phase input end, a capacitance coupling closed-loop amplifier, a level lifting capacitance loop and an in-phase and out-phase output end, wherein the non-inverting input end is connected with the input end of the capacitance coupling closed-loop amplifier and the input end of the level lifting capacitance loop; the capacitance coupling closed-loop amplifier is connected in parallel with the level lifting capacitance loop; the non-inverting output end is connected with the analog-to-digital converter; in each period of the analog-to-digital converter, the input voltage of the analog-to-digital converter is adjusted by opening and closing a switch in the level lifting capacitor loop. Related level lifting is carried out on the sampling capacitor of the analog-to-digital converter successively by adopting the level lifting capacitor loop and the sampling period of the analog-to-digital converter, so that the voltage swing output by the amplifier is greatly reduced, the linearity of the output of the amplifier is improved, and the amplifier can be applied to a high-precision signal chain scene.

The dynamic memory array of a DRAM device is operated using at least two voltages. The first voltage, which is used to power the sense amplifiers during sense (i.e., read) operations and most other column operations (e.g., precharge, activate, write), is the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The second voltage, which determines the voltage written to the capacitor of the DRAM cells (i.e., bitline voltage) is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage written to the capacitors of the DRAM array. This allows lower voltage swing digital logic to be used for a majority of the logic on the DRAM device while writing a larger voltage to the DRAM cells.

The invention relates to the technical field of amplifiers, and discloses a high-reliability low-noise amplifier chip, the circuit comprises an active bias circuit, a cascode low-noise amplifier circuit, a feedback circuit and a large input power protection circuit, a first diode D1 is added in the active bias circuit of the low-noise amplifier, and a second diode D2 is added in the active bias circuit of the low-noise amplifier. The Vgs of the fourth transistor M4 in the cascode low-noise amplification circuit is raised due to the existence of the first diode D1, and after the Vgs are increased, the output power 1dB compression point of the circuit is increased, so that the low-noise amplifier chip can realize high output 1dB compression point and low noise coefficient. When a high-power signal is input, the existence of the high-input-power protection circuit provides a power discharge path for the fourth transistor M4, so that the dynamic voltage swing of the fourth transistor M4 is within a normal range, and the fourth transistor M4 is prevented from being burnt out due to overhigh input power; due to the existence of the twelfth resistor R12, the branch current of the high-input-power protection circuit is reduced, a post-stage diode is protected from being burnt out due to overlarge current, and therefore the reliability of the low-noise amplifier chip is improved.

A technique for reducing the effects of charge injection when a charge pump in a fractional-N frequency synthesizer switches from an error cancellation phase of error current generation to a full-scale phase of error current generation uses a dummy digital-to-analog converter to steer excess current from the error cancellation phase to a voltage regulated node. As a result, the voltage swing of an inactive branch of a digital-to-analog converter of the charge pump is the same as the voltage swing of the active branch of the charge pump, i.e., the device overlap capacitance charge injection is in phase for the branches of a digital-to-analog converter in the charge pump.

The utility model relates to the technical field of chips, in particular to a transient enhanced quick response ldo circuit, which comprises an operational amplifier, a buffer stage circuit, a super source follower circuit and a power transistor, an SSF super source follower framework is added to serve as a transient enhanced quick response branch circuit, and the circuit is ultra-large in bandwidth and high in reliability. When the load current jumps from 17ns to 12mA, the change of the output voltage is within 2%, and the recovery time is 20ns; the ldo circuit directly monitors and feeds back the output voltage, so that a sampling signal transmission path is effectively shortened, voltage signal transmission is accelerated, and the influence of parasitism, matching and the like on sampling accuracy is minimized; the operational amplifier circuit adopts an output current mirror structure, so that the output voltage swing of the operational amplifier can be effectively improved, and the input voltage range of the grid voltage of the power tube is effectively improved; the technical problems of minimum voltage jump and rapid recovery of an ldo output voltage value during abrupt load change are solved.

This application relates to the field of electronic circuit technology, providing a current-steering charge pump circuit and a charge pump phase-locked loop. The current-steering charge pump circuit includes: a reference current mirror connected to the analog circuit's positive power supply, current source, first switch, and the non-inverting input of the first rail-to-rail operational amplifier; a discharge current mirror connected to the first switch, the output of the first rail-to-rail operational amplifier, a second switch, a fifth switch, a seventh switch, and analog ground; a charging current mirror connected to the analog circuit's positive power supply, a third switch, a fourth switch, a sixth switch, and the output of the second rail-to-rail operational amplifier; a third switch connected to the second switch and the non-inverting input of the second rail-to-rail operational amplifier; and a fourth switch connected to the fifth switch and the output of the third rail-to-rail operational amplifier. This circuit can increase the output voltage swing while ensuring that the charging and discharging currents are equal.

This invention provides a level-shifting enable latch, comprising a level shifter circuit and a latch circuit. The level shifter circuit receives a first data input signal and generates a first data output signal, wherein the first data input signal and the first data output signal have different voltage swings. When the latch enable signal is set to a first logic value, the latch circuit sets a second data output signal in response to the first data output signal, and latches the second data output signal when the latch enable signal is set to a second logic value different from the first logic value. The latch circuit includes a first control circuit. The first control circuit enables the latch feedback loop of the latch circuit when the latch enable signal is set to the second logic value, and disables the latch feedback loop of the latch circuit when the latch enable signal is set to the first logic value.

This invention provides a power amplifier circuit, amplification method, a chip, and an electronic product. The power amplifier circuit includes: a control signal generation module that generates a PWM control signal based on a comparison between an input signal and a carrier signal; and a switching amplification module that generates a PWM signal based on the switching control of the PWM control signal. The power amplifier circuit of this invention has a large output swing and high output power. In one example, under the same power supply voltage, the load voltage swing is twice that of the single-ended connection, and the theoretical maximum output power is four times that of the single-ended connection. The power amplifier circuit of this invention is simple in structure when applied with a single-ended connection to the load; and only one filter module is needed, eliminating the need for a DC blocking capacitor. Therefore, the required PCB space is small, and the system cost is greatly reduced.

A pixel circuit includes a photodiode configured to photogenerate charge in response to reflected modulated light incident upon the photodiode. A first floating diffusion is configured to store a first portion of charge photogenerated in the photodiode. A first transfer transistor is configured to transfer the first portion of charge from the photodiode to the first floating diffusion in response to a first phase signal. A first storage node is configured to store the first portion of charge from the first floating diffusion. A first decoupling circuit has a first output responsive to a first input. The first input is coupled to the first floating diffusion and the first output is coupled to first storage node. A voltage swing at the first output is greater than a voltage swing at the first input.

The invention provides a power detection circuit and method and a power detector. A switching tube module is used for generating an output signal according to a preset input signal; the capacitance shunting module is used for shunting an alternating current signal in the output signal, so that the shunted first signal flows into the capacitance shunting module; and the direct current generation module is used for filtering residual signals in the alternating current signals and outputting a voltage result according to direct current signals in the output signals. The capacitance shunting module is additionally arranged at the output end of the switching tube module, when the frequency of the preset input signal is higher, the first signal flowing into the capacitance shunting module in the alternating current signal is more, and correspondingly, the residual signal flowing into the direct current generation module is less, so that the alternating current voltage swing generated by the parasitic inductor can be effectively controlled, and the stability of the device is improved. When the power supply voltage is low voltage, it can be ensured that the switch tube in the switch tube module works in a normal bias state, and then the accuracy of the corresponding relation between the finally output voltage result and the input signal is improved.

The application provides a high-precision reference voltage circuit, which comprises an anti-interference circuit module, a gain circuit module and an amplification buffer circuit module, so that the output voltage of the circuit has a low temperature coefficient, high precision and large output voltage swing. The circuit also comprises a bias circuit and a voltage stabilizing output circuit. The bias circuit comprises an anti-interference circuit, so that the bias circuit can work normally in a high-frequency electromagnetic interference environment. The bias circuit is based on the circuit structure, so that the output bias voltage is stable and unchanged. The voltage stabilizing output circuit comprises a gain circuit, so that the system has high gain and high power supply rejection ratio. The amplification buffer circuit in the voltage stabilizing output circuit has a frequency compensation function, so that the system can work stably in a low-frequency and high-frequency range. Meanwhile, the amplification buffer circuit is based on the circuit structure, so that the system has low output impedance, the current output capacity of the system is improved, and the output voltage has a large voltage swing.