110 results about "Voltage swing" patented technology

The present application provides an all-digital multi-phase DC-DC controller. The digital DC-DC controller includes time-based analog-to-digital converters (ADCs) for converting analog voltage signals into digital-domain signals so as to benefit from gate length scaling without limited by the low voltage swing. Also, the DC-DC controller further includes a digital control circuit and a time-based modulator. The digital control circuit can control the time-based modulator in a digital domain, thereby reducing the affection caused by process, voltage and temperature (PVT) variation. Also, the time-based modulator can adjust the timing of the PWM signals and avoid the performance degradation caused by circuit mismatch. Since the digital control circuit can be fully synthesizable, it allows implementations in all kinds of digital CMOS processes with a small chip area.

Systems, methods, and apparatuses can detect whether an electrical cable between a source device and a sink device has become disconnected. The source device and / or the sink device can be compliant with a version of a Universal Serial Bus (USB) standard, for example, USB 3.x. These systems, methods, and apparatuses can monitor peak voltage swings of data signals flowing between the source device and the sink device. The peak voltage swing of these data signals can be at a first value when the electrical cable is connected to the source device and the sink device or at a second value greater than the first value when the electrical cable is disconnected from the source device or the sink device. The peak voltage swing can switch from the first value to the second value in response to the electrical cable being disconnected from the source device or the sink device. As such, these systems, methods, and apparatuses can determine that the electrical cable has become disconnected from the source device or the sink device in response to detecting the second value for the peak voltage swing of the data signals flowing from the source device to the sink device.

To reduce the area requirements for sensing circuits of 3D NAND-based vector-matrix multiplication circuitry where weight values for a neural network are stored differentially as current levels on pairs of memory cells, techniques are presented for reducing the common mode current levels during sensing operations. When discharging a first capacitor through a first of a memory cell of a pair of memory cells storing a weight value by a first bit line and discharging second capacitor through a second memory cell of the pair by a second bit line, a reference current is applied to the bit lines. The product of a weight value with an input vector values is then determined by comparing the voltage levels on the two capacitors. The use of the reference current reduces the amount of voltage swing in the two capacitors, reducing the size requirements for the capacitors.

A system includes a voltage-controlled oscillator (VCO), a first second-order harmonic filter coupled to the VCO, wherein the first second-order harmonic filter includes a first tunable capacitor, and a second second-order harmonic filter coupled to the VCO, wherein the second second-order harmonic filter includes a second tunable capacitor. The system also includes a measurement circuit coupled to the VCO, wherein the measurement circuit is configured to measure a voltage swing of the VCO. The system also includes a control circuit coupled to the measurement circuit, the first tunable capacitor, and the second tunable capacitor.

The application provides a common-source common-gate amplifier, comprising a signal input module, which is used for generating an input signal according to a power supply voltage; a cross-coupling module, which is electrically connected with the signal input module and is used for forming internal positive feedback according to an output signal; a first biasing module, which is electrically connected with the cross-coupling module; a first branch module, which is electrically connected with the first biasing module; a second biasing module, which is electrically connected with the cross-coupling module; a second branch module, which is electrically connected with the second biasing module; wherein the first biasing module and the second biasing module are used for providing biasing after an input common-mode feedback voltage, the first branch module and the second branch module are used for providing large-swing output biasing, and the first branch module and the second branch module are respectively electrically connected with the signal input module, and the signal input module is further used for outputting branch signals to the first branch module and the second branch module. The application improves the voltage swing, the gain and the bandwidth of the circuit under the single-stage amplifier structure.

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

Embodiments according to the present disclosure relate to semiconductor switches with ESD protection circuits. In the following a clamping circuit for protection against ESD events is described. According to one embodiment the circuit has a first transistor with a control terminal and a load current path, the first transistor being connected between a first contact and a second contact, an amplifier circuit with an amplifier input and an amplifier output, the amplifier circuit being connected with the control terminal of the transistor, and a trigger circuit connected between the first contact and the second contact and having a second transistor. The trigger circuit is designed to generate a voltage swing at the amplifier input in response to a discharge current at the first contact by driving a control terminal of the second transistor with at least a part of the discharge current through an intrinsic capacitance of the second transistor.

The application discloses a transistor device, a semiconductor epitaxial structure and a preparation method thereof. The transistor device comprises a substrate, a compound semiconductor composite structure generating a two-dimensional electron gas, which is arranged on the substrate; a first cap layer arranged on the compound semiconductor composite structure; an insertion layer arranged on the first cap layer; a second cap layer arranged on the insertion layer; the band gap of the material of the insertion layer is greater than the band gap of the material of the first cap layer and the second cap layer; along the direction from the first cap layer to the second cap layer, the band gap of the material of the insertion layer first increases and then decreases; and a gate metal arranged on the second cap layer. In this way, the on-state gate leakage is reduced, the gate voltage resistance and the voltage swing of the device are increased, and the gate reliability of the device is improved.

Embodiments herein relate to a driver circuit for an optical modulator such as a micro-ring modulator (MRM). The driver circuit includes first and second drivers which receive respective differential data signals, and which have their output nodes coupled to a cathode and anode, respectively of the MRM. One or both of the drivers can have their output nodes alternating-current (AC)-coupled to a bias circuit which biases the voltage of the output signal to shift its voltage swing. The bias circuit can include a latch which receives Vbc_high at its power supply terminal and Vbc_low at its ground terminal, where Vbc_high>Vbc_low>0 V.

The present invention relates to the field of integrated circuit technology, and more particularly to an LVDS transmitter with slew control. The present invention utilizes the characteristics of resistor and capacitor delay to output a portion of the data signal output by the LVDS circuit after a delay controlled by slew control resistors (RD1 and RD2) and the parasitic capacitance of the gate of the switch tube (M3 and M4). This process absorbs the external load resistor R L The reflection of the output signal (OUTN and OUTP) is then controlled to control the voltage swing of the output signal. On the one hand, the introduction of the slew control circuit does not increase the extra power consumption of the circuit. On the other hand, the introduction of the slew control circuit can improve the ringing phenomenon of the signal at the inversion point. Secondly, due to the use of a much larger than R L RCM1 and RCM2 thus avoid increasing the current flowing through the internal matching resistor, thereby reducing the power consumption of the transmitter. Ultimately, the present invention solves the ringing phenomenon while reducing the power consumption of the LVDS transmitter.

An RFA (radio frequency amplifier) includes an NCSA (N-type common-source amplifier) established upon a first source node and configured to receive a first signal and output a first internal current; a first NCGA (N-type common-gate amplifier) configured to receive the first internal current and output a second internal current; a second NCGA configured to receive the second internal current and output a first output current; a PCSA (P-type common-source amplifier) established upon a second source node and configured to receive a second signal and output a third internal current; a first PCGA (P-type common-gate amplifier) configured to receive the third internal current and output a fourth internal current; a second PCGA configured to receive the fourth internal current and output a second output current; and a load network comprising a parallel connection of a primary inductor and a tuning capacitor configured to establish an output signal.

According to one embodiment, a method, computer system, and computer program product for adjusting output swing voltage of a Peripheral Component Interconnect Express (PCIe) system is provided. The present invention may include training a neural network, recording, in real time, lane input data of PCIe lanes comprising a PCIe link, generating eye diagrams representing the PCIe lanes based on the lane input data, predicting, by the trained neural network, predicted eye heights for the PCIe lanes, and adjusting a current output swing voltage of one or more PCIe lanes based on the predicted eye heights.

The embodiment of the present application provides an output stage circuit and an operational amplifier, which comprises: a first input end and a second input end for being connected with an input stage circuit; an output end for providing an output signal; a first power supply node for being connected with a first power supply; a second power supply node for being connected with a second power supply; a first transistor connected in a pull-up current path; wherein the pull-up current path extends from the first power supply node to the output end; a gate of the first transistor is connected with the first input end; a second transistor connected in a pull-down current path; wherein the pull-down current path extends from the output end to the second power supply node; a gate of the second transistor is connected with the second input end; a cascade transistor module is vertically connected with the first transistor in the pull-up current path and / or is vertically connected with the second transistor in the pull-down current path. In this way, the output voltage swing of the output stage circuit is improved without changing the first transistor and the second transistor.

The invention relates to the technical field of amplifiers, and discloses a high-reliability low-noise amplifier chip, the circuit comprises an active bias circuit, a cascode low-noise amplifier circuit, a feedback circuit and a large input power protection circuit, a first diode D1 is added in the active bias circuit of the low-noise amplifier, and a second diode D2 is added in the active bias circuit of the low-noise amplifier. The Vgs of the fourth transistor M4 in the cascode low-noise amplification circuit is raised due to the existence of the first diode D1, and after the Vgs are increased, the output power 1dB compression point of the circuit is increased, so that the low-noise amplifier chip can realize high output 1dB compression point and low noise coefficient. When a high-power signal is input, the existence of the high-input-power protection circuit provides a power discharge path for the fourth transistor M4, so that the dynamic voltage swing of the fourth transistor M4 is within a normal range, and the fourth transistor M4 is prevented from being burnt out due to overhigh input power; due to the existence of the twelfth resistor R12, the branch current of the high-input-power protection circuit is reduced, a post-stage diode is protected from being burnt out due to overlarge current, and therefore the reliability of the low-noise amplifier chip is improved.

A technique for reducing the effects of charge injection when a charge pump in a fractional-N frequency synthesizer switches from an error cancellation phase of error current generation to a full-scale phase of error current generation uses a dummy digital-to-analog converter to steer excess current from the error cancellation phase to a voltage regulated node. As a result, the voltage swing of an inactive branch of a digital-to-analog converter of the charge pump is the same as the voltage swing of the active branch of the charge pump, i.e., the device overlap capacitance charge injection is in phase for the branches of a digital-to-analog converter in the charge pump.

The utility model relates to the technical field of chips, in particular to a transient enhanced quick response ldo circuit, which comprises an operational amplifier, a buffer stage circuit, a super source follower circuit and a power transistor, an SSF super source follower framework is added to serve as a transient enhanced quick response branch circuit, and the circuit is ultra-large in bandwidth and high in reliability. When the load current jumps from 17ns to 12mA, the change of the output voltage is within 2%, and the recovery time is 20ns; the ldo circuit directly monitors and feeds back the output voltage, so that a sampling signal transmission path is effectively shortened, voltage signal transmission is accelerated, and the influence of parasitism, matching and the like on sampling accuracy is minimized; the operational amplifier circuit adopts an output current mirror structure, so that the output voltage swing of the operational amplifier can be effectively improved, and the input voltage range of the grid voltage of the power tube is effectively improved; the technical problems of minimum voltage jump and rapid recovery of an ldo output voltage value during abrupt load change are solved.

This application relates to the field of electronic circuit technology, providing a current-steering charge pump circuit and a charge pump phase-locked loop. The current-steering charge pump circuit includes: a reference current mirror connected to the analog circuit's positive power supply, current source, first switch, and the non-inverting input of the first rail-to-rail operational amplifier; a discharge current mirror connected to the first switch, the output of the first rail-to-rail operational amplifier, a second switch, a fifth switch, a seventh switch, and analog ground; a charging current mirror connected to the analog circuit's positive power supply, a third switch, a fourth switch, a sixth switch, and the output of the second rail-to-rail operational amplifier; a third switch connected to the second switch and the non-inverting input of the second rail-to-rail operational amplifier; and a fourth switch connected to the fifth switch and the output of the third rail-to-rail operational amplifier. This circuit can increase the output voltage swing while ensuring that the charging and discharging currents are equal.

This invention provides a level-shifting enable latch, comprising a level shifter circuit and a latch circuit. The level shifter circuit receives a first data input signal and generates a first data output signal, wherein the first data input signal and the first data output signal have different voltage swings. When the latch enable signal is set to a first logic value, the latch circuit sets a second data output signal in response to the first data output signal, and latches the second data output signal when the latch enable signal is set to a second logic value different from the first logic value. The latch circuit includes a first control circuit. The first control circuit enables the latch feedback loop of the latch circuit when the latch enable signal is set to the second logic value, and disables the latch feedback loop of the latch circuit when the latch enable signal is set to the first logic value.

This invention provides a power amplifier circuit, amplification method, a chip, and an electronic product. The power amplifier circuit includes: a control signal generation module that generates a PWM control signal based on a comparison between an input signal and a carrier signal; and a switching amplification module that generates a PWM signal based on the switching control of the PWM control signal. The power amplifier circuit of this invention has a large output swing and high output power. In one example, under the same power supply voltage, the load voltage swing is twice that of the single-ended connection, and the theoretical maximum output power is four times that of the single-ended connection. The power amplifier circuit of this invention is simple in structure when applied with a single-ended connection to the load; and only one filter module is needed, eliminating the need for a DC blocking capacitor. Therefore, the required PCB space is small, and the system cost is greatly reduced.

A pixel circuit includes a photodiode configured to photogenerate charge in response to reflected modulated light incident upon the photodiode. A first floating diffusion is configured to store a first portion of charge photogenerated in the photodiode. A first transfer transistor is configured to transfer the first portion of charge from the photodiode to the first floating diffusion in response to a first phase signal. A first storage node is configured to store the first portion of charge from the first floating diffusion. A first decoupling circuit has a first output responsive to a first input. The first input is coupled to the first floating diffusion and the first output is coupled to first storage node. A voltage swing at the first output is greater than a voltage swing at the first input.

The application provides a high-precision reference voltage circuit, which comprises an anti-interference circuit module, a gain circuit module and an amplification buffer circuit module, so that the output voltage of the circuit has a low temperature coefficient, high precision and large output voltage swing. The circuit also comprises a bias circuit and a voltage stabilizing output circuit. The bias circuit comprises an anti-interference circuit, so that the bias circuit can work normally in a high-frequency electromagnetic interference environment. The bias circuit is based on the circuit structure, so that the output bias voltage is stable and unchanged. The voltage stabilizing output circuit comprises a gain circuit, so that the system has high gain and high power supply rejection ratio. The amplification buffer circuit in the voltage stabilizing output circuit has a frequency compensation function, so that the system can work stably in a low-frequency and high-frequency range. Meanwhile, the amplification buffer circuit is based on the circuit structure, so that the system has low output impedance, the current output capacity of the system is improved, and the output voltage has a large voltage swing.

This disclosure provides an adjustment circuit and an amplifier circuit for a stacked power amplifier. The stacked power amplifier includes multiple stacked transistors, with the output of one transistor connected to the input of the next transistor. The adjustment circuit includes: a voltage swing detection module connected to the output of each transistor, comprising a voltage detection unit and a difference unit, for detecting and comparing the voltage swing between the transistor input and output, and outputting multiple voltage swings; a limiting comparison module connected to the voltage swing detection module, for comparing a preset threshold voltage with the voltage swing of any one or more transistors, and outputting a comparison result; the limiting comparison module is connected to a control module, which outputs a control signal based on the comparison result; and an attenuator connected to the input of each transistor, for attenuating the voltage input to the transistor according to the control signal.

Techniques to utilize thin-oxide devices, such as gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs), in high voltage environments, such as to provide a high-voltage based low-power, temperature dependent, thin-oxide-only on-chip high current low drop out (LDO) regulator in a system-on-chip (SoC), such as provide power to configuration random-access memory (CRAM) cells distributed throughout configurable / programmable circuitry. Thin-oxide only circuitry may include thin-oxide-only amplifier circuitry, thin-oxide-only power gate circuitry, thin-oxide-only level shifters that shift voltage swings of control signals to voltage domains of the power gate circuitry, and thin-oxide-only clamp circuitry.

The present disclosure provides a compensation circuit module, a power amplifier component, a compensation method and an apparatus. The compensation circuit module includes at least: a variable resistor, a detection component and a control component; the detection end of the detection component is connected to the DC blocking capacitor of the power amplifier for detecting the voltage swing of the input signal of the DC blocking capacitor; the control component is connected to the detection component for outputting a control signal according to the input signal detected by the detection component; the variable resistor is connected to the output end of the control component for changing the resistance connected to the power amplifier according to the control signal, and the resistance of the variable resistor connected to the power amplifier is used to constitute the feedback resistance of the power amplifier; the feedback resistance is used to increase when the gain of the power amplifier decreases; the increased feedback resistance is used to keep the gain in the flat section of the gain change curve; the resistance of the variable resistor can be adjusted by the input signal to achieve compensation for the gain of the power amplifier and maintain the linearity of the input and output of the power amplifier.

The application discloses a kind of chopper switch circuit driving circuit and chopper.The driving circuit is with first level shift module and second level shift module respectively with the input common-mode voltage of chopper switch circuit as reference to obtain first pair of complementary clock signals and second pair of complementary clock signals, and the low level of first pair of complementary clock signals is lower than input common-mode voltage, and the high level of second pair of complementary clock signals is higher than input common-mode voltage, then through gating combination module in the same period alternatively the low level of first pair of complementary clock signals and the high level of second pair of complementary clock signals are alternately transmitted to drive clock output end, to synthesize the drive clock pair with greater voltage swing, so that when the input differential voltage of chopper switch circuit is larger or even close to power supply voltage, reliable conduction and turn-off of switch can still be realized, effectively avoid the generation of high-temperature leakage channel, improve the integrity of signal transmission and system reliability.

The invention belongs to the technical field of power semiconductor device testing, and particularly relates to a GaN device dynamic on-resistance testing device which comprises a testing main circuit and an auxiliary testing clamping circuit. Three test reserved interfaces are arranged in the test main circuit, when the test reserved interface 1 is connected with the test reserved interface 3, the test main circuit is in a hard switch working mode, and when the test reserved interface 2 is connected with the test reserved interface 3, the test main circuit is in a soft switch working mode; the auxiliary test clamping circuit is connected in parallel with two ends of a to-be-tested switch tube DUT in the test main circuit; the auxiliary test clamping circuit is connected in parallel to the two ends of the to-be-tested GaN device, so that the voltage swing of the to-be-tested GaN device in the switching state switching process is reduced, drain-source voltage clamping in the whole test process is achieved, meanwhile, the conduction voltage drop of the to-be-tested GaN device can be accurately represented, and the measurement accuracy of the oscilloscope is improved.

A power converter includes a piezoelectric transformer comprising a piezoelectric material and metalized electrodes that form two or more ports, at least one of the two or more ports being an input port having an input port surface area, at least one of the at least two ports being an output port having an output port surface area, wherein, the piezoelectric transformer has a physical characteristic of a geometry term H comprised of piezoelectric transformer dimensions at least one of input port and output port measurements, including and a voltage swing across the input port, a voltage swing across the output port, a charge utilization at the input port, a charge utilization at the output port, an input voltage, an output voltage, and a transformation ratio.

The utility model provides a capacitance compensation circuit, a switch, a radio frequency circuit and a communication device, and relates to the technical field of antennas, and the method is used for realizing the more balanced voltage swing of each stage of switching circuit on the basis of realizing the lower total capacitance value. The circuit is applied to a radio frequency switch, the radio frequency switch is provided with an input end and an output end, the capacitance compensation circuit comprises N cascaded switch circuits, the output end of the upper-stage switch circuit in the N switch circuits is connected with the input end of the lower-stage switch circuit, and the output end of the lower-stage switch circuit in the N switch circuits is connected with the input end of the lower-stage switch circuit. The input end of the first stage of switch circuit in the N cascaded switch circuits is connected with the input end of the radio frequency switch, the output end of the last stage of switch circuit in the N cascaded switch circuits is connected with the output end of the radio frequency switch, and N is greater than or equal to 2; and at least one compensation capacitor, wherein any compensation capacitor is bridged between the at least two stages of switching circuits.

The invention discloses an output stage circuit, a driving chip and a driving device, and relates to the technical field of electronics. The circuit comprises a gain adjusting circuit, a differential output circuit and a feedback circuit. The differential output circuit converts the differential input signal provided by the gain adjusting circuit into a differential output signal based on the first working voltage provided by the working power supply so as to drive a post-stage load. Meanwhile, the differential output circuit also outputs a corresponding sampling signal to the feedback circuit, and the feedback circuit can generate a corresponding second working voltage based on the voltage of the sampling signal and a preset reference voltage. The gain adjusting circuit amplifies the voltage of the differential input signal provided by the pre-stage circuit through the real-time amplification gain corresponding to the gain adjusting signal and the second working voltage, so that the voltage swing range of the differential output signal generated by the differential output circuit is enough, linear distortion is avoided, and the stability of the differential output signal is improved. Therefore, the linearity between input and output of the whole circuit is ensured.