54 results about "Content-addressable memory" patented technology

The present disclosure is directed to key-value data storage systems using content addressable memory. A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys and a value data block. The memory system additionally includes a processing device that receives an input search key and identifies one of the plurality of stored search keys that matches the input search key, the one of the plurality of stored search keys having an associated matching orientation in the CAM block. The processing device further determines a corresponding value orientation in the value data block using the associated matching orientation and retrieves data representing a value associated with the input search key from the value orientation in the value data block.

Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array and a number of content-addressable control cells. Each control cell controls a respective display pixel of the pixel active array. Each control cell includes a comparator to generate a control signal to control the respective display pixel of the pixel active array based on a comparison between pixel data for the respective display pixel and one or more counters corresponding to a gray level.

Embodiments of the present disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learned storage memory. The analog output of the differentiable CAM can provide input to a learning algorithm that can compute gradients in comparison to historical values and reduce data inaccuracies and power consumption.

Methods, devices, and systems are provided for content addressable memory (CAM) loading in a semiconductor device. In one aspect, an example memory device includes a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit includes a CAM, a data path, and a buffer circuit coupled to the CAM through the data path. The buffer circuit includes a multiplexer coupled to a memory device and a command / address (CA) interface. The multiplexer is configured to dynamically select either the memory or the CA interface.

This invention provides a Content Addressable Memory (CAM) unit, a CAM memory device, an operation method thereof, and a data search and comparison method. The CAM unit includes: a first flash memory unit, a first terminal of which receives a first search voltage; and a second flash memory unit, a first terminal of which receives a second search voltage, and a second terminal of the first flash memory unit electrically connected to a second terminal of the second flash memory unit; wherein the first flash memory unit and the second flash memory unit are connected in series, and a stored data in the content addressable memory unit is determined by a combination of multiple threshold voltages of the first flash memory unit and the second flash memory unit.

A memory system includes a memory device comprising a content addressable memory (CAM) block storing a clustered or non-clustered index database comprising a plurality of stored search keys, wherein the plurality of stored search keys are sorted according to respective values of a first feature of a plurality of features. The memory system further comprises a processing device that receives an input search key comprising a search value for a second feature of the plurality of features, and identifies, without re-sorting the plurality of stored search keys, a subset of the plurality of stored search keys from the CAM block that match at least a portion of the input search key comprising the search value for the second feature of the plurality of features.

A satisfiability modulo theories (SMT) solver accelerator is implemented with analog content addressable memory (CAM) cells. A job-shop scheduling problem (JSSP) may be mapped to expression clauses that are stored in an analog CAM array. A test cycle may be performed by searching for a test vector of input variables in the analog CAM array, selecting a candidate variable of the test vector that is violating a largest number of the expression clauses, and changing the candidate variable of the test vector. The test cycle may be repeated until none of the expression clauses are violated by the test vector of the input variables. The resulting test vector of the input variables that violates no expression clauses is a solution for the JSSP.

The invention provides a message editing method and device, a medium and electronic equipment. The message editing method comprises the following steps: receiving an entry message; performing analysis processing on the message to obtain analysis information of the message; matching a destination media access control (DMAC) address in the two-layer information with a router port media access control (MAC) address to obtain a matching result of the DMAC address; if the matching result is successful matching, performing matching processing on a preset binary content addressable memory (BCAM) entry based on the two-layer information, the three-layer information, the four-layer information and the type information to obtain behavior information in the successfully matched preset BCAM entry, otherwise, reporting the entry message to a CPU system; and carrying out editing processing on the entrance message based on the behavior information to obtain an exit message. The method can reduce the processing time delay and relieve the processing pressure of the CPU.

This invention provides a 3-SAT completeness solver supporting CDCL non-temporally sequential backtracking. The completeness solver includes: a content-addressable memory-propagation unit (CAM) for single-word matching using CAM, performing word propagation and decision operations in a word watch loop, and generating a structured implication graph; an implication graph caching unit, connected at one end to the CAM and at the other to an in-memory computation learning unit, for storing the structural information of the structured implication graph; and an in-memory computation learning unit for performing conflict-driven clause learning CDCL based on the structural information of the structured implication graph, thereby achieving completeness analysis with non-temporally sequential backtracking. This invention enables completeness analysis of SAT problems using CDCL non-temporally sequential backtracking, fully utilizing the inherent structural characteristics of SAT problems, and providing an efficient completeness solution for complex SAT problems in practical applications.

This application discloses a device, method, and switching chip for preventing host hang-up, belonging to the field of computer bus and interface technology. The device for preventing host hang-up includes a message analysis and filtering module, an address and resource control module, a caching module, a content addressable memory module, a message inspection module, and a response message generation module. It parses, verifies, and timestamps messages sent to endpoint devices and caches their field information; it checks whether the message response has timed out or the destination port is faulty through a polling mechanism; when a response timeout or fault is detected, it automatically constructs a response message based on the original message fields and returns it to the host, releasing the host's occupied resources in a timely manner and preventing the system from hanging up.

The present invention is a process and structure of a ferroelectric neural network cell with self-learning capability and enhanced character recognition length. The ferroelectric neural network cell is a content addressable memory (CAM) structure (or FeCAM for short) based on a ferroelectric field-effect transistor (FeFET), and the FeCAM is a 1N1P-FeCAM including an N-type FeFET and a P-type FeFET. Therefore, the present invention reduces the number of devices to minimize cell area, and each cell consists of two complementary FeFETs to achieve a density that is 33% higher than that of Ternary CAM (TCAM). H2 plasma treatment (HPT) is effective in enhancing symmetry between ION1 and ION2 to increase the number of mismatch cells (Max HD, MHD). Therefore, the present invention is useful to graphic recognition and can be applied to various fields of artificial intelligence.

The present disclosure relates to dual address command management using content addressable memory. A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device performs operations including, in response to receiving a memory access command, determining that the memory access command is a dual address command including a source address and a destination address, generating a first content addressable memory (CAM) entry associated with a read command of the dual address command, where the first CAM entry references the source address, generating a second CAM entry associated with a write command of the dual address command, where the second CAM entry references the destination address, inserting the first CAM entry and the second CAM entry into a CAM, and issuing the read command associated with the first CAM entry to the memory device.

The invention discloses a system and a method for realizing a content addressable memory (CAM) in a field programmable gate array (FPGA), electronic equipment and a medium, and belongs to the technical field of semiconductor memorizers, the system comprises a storage table item updating module for recoding data and addresses which need to be stored in a current content addressable memory (CAM), generating new write-in signals, addresses and data, and storing the new write-in signals, addresses and data in the FPGA; preparing to write data into the BlockRAM module; the Block RAM module is used for storing the encoded table items; and the matching result output module is used for inputting to-be-matched contents, reading the storage data from the BlockRAM module, decoding the storage data and generating matching address information. The method has the advantages of low complexity, low power consumption, high performance and easiness in implementation.

According to the technical scheme, the MCAM storage unit is characterized in that the MCAM storage unit is composed of five transistors and a multi-level unit resistive random access memory. The second aspect of the technical scheme of the invention is to disclose a multi-bit content addressable memory which is characterized by comprising an MCAM storage array consisting of the MCAM storage units. Aiming at the problems that a traditional CAM based on an SRAM or a single-bit storage unit is large in unit area, limited in bit density, difficult to support multi-state matching and similarity search and the like, the invention provides a novel architecture based on an RRAM, by optimizing a storage unit structure and an input circuit, the storage density and the matching precision are remarkably improved, and the reliability of the CAM is improved. And multi-state Hamming distance operation is supported. The technology disclosed by the invention is suitable for calculation scenes needing high-density storage and high-parallel approximate search, such as artificial intelligence retrieval accelerators, gene sequence alignment, vector database search, network classification and the like.

A semiconductor device capable of operating a content addressable memory at higher speed is provided. The semiconductor device 1 includes a memory array 4 with a master block 2 storing a first portion of a bit string constituting data entries, and a slave block 3 storing the remaining second portion of the bit string, and a search unit 21 included in the master block 2 to determine a match between a portion corresponding to the first portion of the search data and any of the first portions of the data entries. Master block 2 controls to activate the slave block 3 in response to the start of determination by the search unit 21, and controls to continue the activation or inactivate the slave block 3 according to the result of the determination by the search unit 21.

A photonic content addressable memory employs cross coupled optical inverters to provide a bistable element that can be set or reset and interrogated optically. Optical switches controlled by the state of the bistable element can compare that state to optically conveyed pattern bits providing a “wired OR” on an output line quickly indicating matching along a logical row of data so stored. The bistable element can be simultaneously interrogated with different search patterns using parallel banks of optical switches tuned to different frequencies.

Methods, devices, and systems for content addressable memory (CAM) loading in semiconductor devices are provided. In one aspect, an example memory device includes a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit includes CAMs, a data path, and a buffer circuit coupled to the CAMs through the data path. The buffer circuit includes a multiplexer coupled to a storage unit and a command / address (CA) interface. The multiplexer is configured to dynamically select either the storage unit or the CA interface.

A photonic content addressable memory employs cross coupled optical inverters to provide a bistable element that can be set or reset and interrogated optically. Optical switches controlled by the state of the bistable element can compare that state to optically conveyed pattern bits providing a "wired OR" on an output line quickly indicating matching along a logical row of data so stored. The bistable element can be simultaneously interrogated with different search patterns using parallel banks of optical switches tuned to different frequencies.

A content addressable memory (CAM) circuit includes a word line driver that incorporates a digital-to-analog converter (DAC), which enables the CAM circuit to store an n-bit value only with n CAM cells. The CAM circuit includes one or more of CAM cells configured to store bit values, at least one word line driver coupled to word lines of the CAM cells and configured to supply word line output to drive the CAM cells, and at least one bit line driver coupled to bit lines of the CAM cells and configured to supply bit line outputs to drive the CAM cells. The word line driver and the bit line driver include DAC circuits that include PFETs and NFETs.

This invention provides a species gene classification system, method, apparatus, electronic device, and storage medium, belonging to the field of integrated circuit technology. It includes: a preprocessing module for converting a first serial current signal corresponding to a gene of a species to be tested into a hash vector representing that gene; a content-addressable memory (MAP) for performing vector-matrix multiplication on the hash vectors to obtain multiple first cumulative currents; the MAP is an RRAM array structure, and its conductance is positively correlated with a reference hash vector, where each reference hash vector represents a gene from a species gene pool; and a first comparison module for comparing the various first cumulative currents to determine the species to which the gene belongs. This invention achieves species gene classification through in-memory computation, reducing data movement and eliminating the need for complex algorithms to correct noise, thereby accelerating system operation, reducing sequencing time, and lowering system energy consumption.

Systems, methods, and devices are described for memory device security and row hammer mitigation. Control mechanisms can be implemented in a front-end and / or back-end of a memory subsystem to flush rows of the memory. A row activate command can be received at control circuitry of a memory subsystem with a row address and increment a first count of a row counter stored in a content addressable memory (CAM) of the memory subsystem corresponding to the row address. The control circuitry can determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count can be incremented each time the CAM has been full. When it is determined that the first count is greater than the RHT minus the second count, a flush command can be issued to the row address.

Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, this disclosure presents an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting transmission lines to develop a delay-line memory system. The fully superconducting design is operable at frequencies ranging from approximately 20 GHz to 100 GHz and achieves data densities on the order of tens to thousands of megabits per square centimeter. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories.

A content addressable memory includes a cell array capable of storing a plurality of data entries, a plurality of valid cells provided for each of the data entries and configured to store valid bits indicating valid or invalid of the data entry, an All-invalid detection circuit configured to detect that the plurality of valid bits all indicate invalid, a search unit configured to determine matching or mismatching between the plurality of data entries and search data, and a control unit configured to stop the search unit when the All-invalid detection circuit detects that the valid bits all indicate invalid.

The technology is directed to systems and methods of memory repair that make use of content addressable memory ("CAM") structures. A repair CAM may be used to efficiently identify repair data for addressing defects or faults of multiple memory dies, or other forms of memory. These memories may be associated with the subsystem based on a subsystem ID, and the repair CAM may associate repair data with memories within identified subsystems. The CAM can be configured to read those CAM locations that are associated with an identified subsystem ID and return repair data from each CAM location that is associated with a memory within the identified subsystem.

The invention discloses a capacitance variable memory array testing device, which belongs to the technical field of semiconductor memory device testing, and comprises an array to be tested, a switch matrix, an ADC (Analog to Digital Converter) module, a high-speed pulse DAC (Digital to Analog Converter) module and a control logic module based on a ZYNQ platform, the array to be tested is in communication connection with the ADC module; an array to be tested is connected with the high-speed pulse DAC module; the control logic module based on the ZYNQ platform comprises a processing system PS and a programmable logic module PL; the output end of the ADC module is connected with the programmable logic module PL; the programmable logic module PL is connected with the switch matrix; the programmable logic module PL is in communication connection with the high-speed pulse DAC module; and the control logic module based on the ZYNQ platform is in communication connection with the upper computer. According to the invention, high integration and collaboration are realized, the high flexibility and programmability of the system are improved, and the test efficiency is greatly improved; high performance and high precision are ensured, the cost is reduced, and the cost performance is increased.

The present disclosure provides a content addressable memory (CAM). The CAM includes a CAM register configured to store a mapping table, N comparators coupling to the CAM register, and N multiplexers coupling to the N comparators respectively and to the CAM register. The mapping table includes first addresses and second addresses. Each one of the first addresses corresponds to one of the second addresses. Each of the N comparators is configured to compare the first addresses with one of N input signals, where N is an integer greater than 1. The N input signals come from N microcontroller units. The N multiplexers is configured to generate N output signals. At least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.

Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array to display an image frame over a series of subframes content-addressable control circuitry. The content-addressable control circuitry may control the pixel active array. The content-addressable control circuitry may include circuitry to perform subframe dithering to generate control signals to control the display pixels of the pixel active array. The control signals may correspond to different gray levels for different subframes of the series of subframes of the image frame to be displayed on the pixel active array.

The present disclosure provides a storage cell for an analog content addressable memory and an analog content addressable memory device. The storage cell for the analog content addressable memory includes an N-type transistor, a P-type transistor, and a current control circuit. A gate of the N-type transistor is configured to receive a first input signal. A gate of the P-type transistor is configured to receive a second input signal. The current control circuit is coupled to at least one of the N-type transistor and the P-type transistor and configured to generate at least one conduction current. When an input voltage of the first input signal and an input voltage of the second input signal are within a matching range, the N-type transistor and the P-type transistor are both turned on, and the corresponding conduction current is substantially a fixed current value. The matching range is related to a threshold voltage of the N-type transistor, a threshold voltage of the P-type transistor, and the fixed current value.

Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.