92 results about "Content-addressable memory" patented technology

Techniques for maintaining cache coherency while sharing data among multiple processors are disclosed. Multiple coherent elements are arranged in an M×N mesh topology. An element can include a compute coherency block (CCB), and a coherency ordering agent (COA). The COAs include a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic. The CCB and COA include functions for interfacing with a hierarchical cache and directory snoop filter (DSF). A CCB from within one of the multiple coherent elements issues a read request. The corresponding directory snoop filter (DSF) is inspected to determine if there is a slot (way) available for storing information pertaining to the read request. In the event that no eligible vacancies are present in the DSF, a multi-pass process for handling a capacity limit in a DSF is performed.

Embodiments described herein relate to content addressable memory (CAM). An example CAM device comprises a back-end-of-line (BEOL) layer that is disposed over a front-end-of-line layer. A plurality of CAM cells are provided in the device, wherein each cell comprises a storage portion and a compare portion. In the example CAM device, the storage portion of each cell of the plurality of CAM cells is disposed in the FEOL layer and the compare portion of each cell of the plurality of CAM cells is disposed in the BEOL layer.

The present disclosure is directed to key-value data storage systems using content addressable memory. A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys and a value data block. The memory system additionally includes a processing device that receives an input search key and identifies one of the plurality of stored search keys that matches the input search key, the one of the plurality of stored search keys having an associated matching orientation in the CAM block. The processing device further determines a corresponding value orientation in the value data block using the associated matching orientation and retrieves data representing a value associated with the input search key from the value orientation in the value data block.

Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array and a number of content-addressable control cells. Each control cell controls a respective display pixel of the pixel active array. Each control cell includes a comparator to generate a control signal to control the respective display pixel of the pixel active array based on a comparison between pixel data for the respective display pixel and one or more counters corresponding to a gray level.

Embodiments of the present disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learned storage memory. The analog output of the differentiable CAM can provide input to a learning algorithm that can compute gradients in comparison to historical values and reduce data inaccuracies and power consumption.

Various embodiments provide for using data search on content-addressable memory (CAM), such as CAM implemented using a NOT-AND (NAND)-type memory device, to facilitate data de-duplication, where the CAM and the data search can be part of a memory system (e.g., memory sub-system).

The present disclosure relates to a non-volatile content-addressable memory based on ferroelectric capacitors and an electronic device. The memory includes: a plurality of storage cells, each of which comprises: a first switch and a second switch connected to a first capacitor and a second capacitor, respectively; a first capacitor and a third capacitor, and a gate of a first transistor, all connected to a first node; a second capacitor and a fourth capacitor, and a gate of a second transistor, all connected to a second node; at least one of the first and third capacitors is a ferroelectric capacitor, and at least one of the second and fourth capacitors is a ferroelectric capacitor; and a control unit for inputting a control signal to control the storage cell to perform a target operation. The disclosed embodiments achieve non-destructive reading of data, improve the service life of the memory, and reduce operation delays and energy consumption.

Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

Methods, devices, and systems are provided for content addressable memory (CAM) loading in a semiconductor device. In one aspect, an example memory device includes a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit includes a CAM, a data path, and a buffer circuit coupled to the CAM through the data path. The buffer circuit includes a multiplexer coupled to a memory device and a command / address (CA) interface. The multiplexer is configured to dynamically select either the memory or the CA interface.

The present disclosure provides a content addressable memory (CAM). The CAM includes a CAM register configured to store a mapping table, N comparators coupling to the CAM register, and N multiplexers coupling to the N comparators respectively and to the CAM register. The mapping table includes first addresses and second addresses. Each one of the first addresses corresponds to one of the second addresses. Each of the N comparators is configured to compare the first addresses with one of N input signals, where N is an integer greater than 1. The N input signals come from N microcontroller units. The N multiplexers is configured to generate N output signals. At least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.

This invention provides a Content Addressable Memory (CAM) unit, a CAM memory device, an operation method thereof, and a data search and comparison method. The CAM unit includes: a first flash memory unit, a first terminal of which receives a first search voltage; and a second flash memory unit, a first terminal of which receives a second search voltage, and a second terminal of the first flash memory unit electrically connected to a second terminal of the second flash memory unit; wherein the first flash memory unit and the second flash memory unit are connected in series, and a stored data in the content addressable memory unit is determined by a combination of multiple threshold voltages of the first flash memory unit and the second flash memory unit.

A memory system includes a memory device comprising a content addressable memory (CAM) block storing a clustered or non-clustered index database comprising a plurality of stored search keys, wherein the plurality of stored search keys are sorted according to respective values of a first feature of a plurality of features. The memory system further comprises a processing device that receives an input search key comprising a search value for a second feature of the plurality of features, and identifies, without re-sorting the plurality of stored search keys, a subset of the plurality of stored search keys from the CAM block that match at least a portion of the input search key comprising the search value for the second feature of the plurality of features.

A satisfiability modulo theories (SMT) solver accelerator is implemented with analog content addressable memory (CAM) cells. A job-shop scheduling problem (JSSP) may be mapped to expression clauses that are stored in an analog CAM array. A test cycle may be performed by searching for a test vector of input variables in the analog CAM array, selecting a candidate variable of the test vector that is violating a largest number of the expression clauses, and changing the candidate variable of the test vector. The test cycle may be repeated until none of the expression clauses are violated by the test vector of the input variables. The resulting test vector of the input variables that violates no expression clauses is a solution for the JSSP.

The invention provides a message editing method and device, a medium and electronic equipment. The message editing method comprises the following steps: receiving an entry message; performing analysis processing on the message to obtain analysis information of the message; matching a destination media access control (DMAC) address in the two-layer information with a router port media access control (MAC) address to obtain a matching result of the DMAC address; if the matching result is successful matching, performing matching processing on a preset binary content addressable memory (BCAM) entry based on the two-layer information, the three-layer information, the four-layer information and the type information to obtain behavior information in the successfully matched preset BCAM entry, otherwise, reporting the entry message to a CPU system; and carrying out editing processing on the entrance message based on the behavior information to obtain an exit message. The method can reduce the processing time delay and relieve the processing pressure of the CPU.

This invention provides a 3-SAT completeness solver supporting CDCL non-temporally sequential backtracking. The completeness solver includes: a content-addressable memory-propagation unit (CAM) for single-word matching using CAM, performing word propagation and decision operations in a word watch loop, and generating a structured implication graph; an implication graph caching unit, connected at one end to the CAM and at the other to an in-memory computation learning unit, for storing the structural information of the structured implication graph; and an in-memory computation learning unit for performing conflict-driven clause learning CDCL based on the structural information of the structured implication graph, thereby achieving completeness analysis with non-temporally sequential backtracking. This invention enables completeness analysis of SAT problems using CDCL non-temporally sequential backtracking, fully utilizing the inherent structural characteristics of SAT problems, and providing an efficient completeness solution for complex SAT problems in practical applications.

This application discloses a device, method, and switching chip for preventing host hang-up, belonging to the field of computer bus and interface technology. The device for preventing host hang-up includes a message analysis and filtering module, an address and resource control module, a caching module, a content addressable memory module, a message inspection module, and a response message generation module. It parses, verifies, and timestamps messages sent to endpoint devices and caches their field information; it checks whether the message response has timed out or the destination port is faulty through a polling mechanism; when a response timeout or fault is detected, it automatically constructs a response message based on the original message fields and returns it to the host, releasing the host's occupied resources in a timely manner and preventing the system from hanging up.

The present invention is a process and structure of a ferroelectric neural network cell with self-learning capability and enhanced character recognition length. The ferroelectric neural network cell is a content addressable memory (CAM) structure (or FeCAM for short) based on a ferroelectric field-effect transistor (FeFET), and the FeCAM is a 1N1P-FeCAM including an N-type FeFET and a P-type FeFET. Therefore, the present invention reduces the number of devices to minimize cell area, and each cell consists of two complementary FeFETs to achieve a density that is 33% higher than that of Ternary CAM (TCAM). H2 plasma treatment (HPT) is effective in enhancing symmetry between ION1 and ION2 to increase the number of mismatch cells (Max HD, MHD). Therefore, the present invention is useful to graphic recognition and can be applied to various fields of artificial intelligence.

The invention belongs to the field of computer part manufacturing, and particularly discloses an NAND type content addressable memory circuit and an operation method. The circuit comprises an NAND type analog content addressable memory array, a pre-charging circuit and a comparator circuit. The input fixed-point number is compared with the stored fixed-point number bit by bit, a discharge path is formed according to a comparison result, and a word line load capacitor discharges through the path to obtain a corresponding word line voltage; and the voltage is input into the comparator circuit, and finally a data comparison result is output. According to the method, the size comparison of fixed-point numbers can be efficiently realized in parallel, the calculation complexity is greatly reduced, and the calculation rate is improved. In a big data or artificial intelligence application scene needing large-scale data comparison, a large amount of calculation overhead can be saved, and the calculation speed is improved.

The present disclosure relates to dual address command management using content addressable memory. A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device performs operations including, in response to receiving a memory access command, determining that the memory access command is a dual address command including a source address and a destination address, generating a first content addressable memory (CAM) entry associated with a read command of the dual address command, where the first CAM entry references the source address, generating a second CAM entry associated with a write command of the dual address command, where the second CAM entry references the destination address, inserting the first CAM entry and the second CAM entry into a CAM, and issuing the read command associated with the first CAM entry to the memory device.

A device includes a first programmable computing block with an analog content addressable memory array, sense amplifiers, inverters, and a format converter circuit. The array includes analog content addressable memory cells arranged in rows and columns. The format converter circuit is configured to receive a Gray code from the inverters and convert it to a binary code. The device may also include additional programmable computing blocks. A system calculates decimal outputs of a predetermined function for a set of decimal inputs, encodes the outputs into Gray codes, generates mappings associating ranges of the decimal inputs with values for bit positions within the Gray codes, and programs the analog content addressable memory device based on the mappings to directly output the values for the bit positions.

The invention discloses a service flow replication method, device and system based on a switch chip, and relates to the technical field of communication, and the method comprises the following steps: S001, constructing a full-link telemetering mechanism in a main data channel, collecting time delay fluctuation and packet loss tracks in real time, generating a replication pressure index heat map, and transmitting the replication pressure index heat map to a main data channel; the resource occupation range of the mirror session on the forwarding plane is represented; and S002, based on the copy pressure index heat map and in combination with port real-time statistical information, generating a conflict fingerprint in the three-state content addressing storage, and positioning a high-frequency copy hot spot, a cross-port strategy conflict and a repeated entry path by using the conflict fingerprint to provide a reference for strategy convergence. According to the method, resource occupation is perceived through a telemetering heat map, strategy partitioning is realized by utilizing conflict fingerprints and an access control list, redundant traffic is duplicated in combination with signatures and hash chains, resources are adaptively allocated by fusing a fault-tolerant and regulation mechanism, a copy closed loop is constructed, the stability and the execution efficiency are improved, the load of core equipment is reduced, and the method has engineering feasibility.

The invention discloses a system and a method for realizing a content addressable memory (CAM) in a field programmable gate array (FPGA), electronic equipment and a medium, and belongs to the technical field of semiconductor memorizers, the system comprises a storage table item updating module for recoding data and addresses which need to be stored in a current content addressable memory (CAM), generating new write-in signals, addresses and data, and storing the new write-in signals, addresses and data in the FPGA; preparing to write data into the BlockRAM module; the Block RAM module is used for storing the encoded table items; and the matching result output module is used for inputting to-be-matched contents, reading the storage data from the BlockRAM module, decoding the storage data and generating matching address information. The method has the advantages of low complexity, low power consumption, high performance and easiness in implementation.

According to the technical scheme, the MCAM storage unit is characterized in that the MCAM storage unit is composed of five transistors and a multi-level unit resistive random access memory. The second aspect of the technical scheme of the invention is to disclose a multi-bit content addressable memory which is characterized by comprising an MCAM storage array consisting of the MCAM storage units. Aiming at the problems that a traditional CAM based on an SRAM or a single-bit storage unit is large in unit area, limited in bit density, difficult to support multi-state matching and similarity search and the like, the invention provides a novel architecture based on an RRAM, by optimizing a storage unit structure and an input circuit, the storage density and the matching precision are remarkably improved, and the reliability of the CAM is improved. And multi-state Hamming distance operation is supported. The technology disclosed by the invention is suitable for calculation scenes needing high-density storage and high-parallel approximate search, such as artificial intelligence retrieval accelerators, gene sequence alignment, vector database search, network classification and the like.

A semiconductor device capable of operating a content addressable memory at higher speed is provided. The semiconductor device 1 includes a memory array 4 with a master block 2 storing a first portion of a bit string constituting data entries, and a slave block 3 storing the remaining second portion of the bit string, and a search unit 21 included in the master block 2 to determine a match between a portion corresponding to the first portion of the search data and any of the first portions of the data entries. Master block 2 controls to activate the slave block 3 in response to the start of determination by the search unit 21, and controls to continue the activation or inactivate the slave block 3 according to the result of the determination by the search unit 21.

A device that includes a first circuit, an analog content addressable memory (ACAM), and a result analyzer is disclosed. The first circuit can be programmed with a matrix. The first circuit can be configured to receive an input vector comprising a first set of values; perform a matrix multiplication by multiplying the input vector by the matrix to obtain a matrix multiplication result; and output the matrix multiplication result, where the matrix multiplication result corresponds to a feature vector. The ACAM can be configured to receive the feature vector and perform an operation using the feature vector to obtain a set of output match results. The result analyzer can be configured to output a machine learning algorithm result based on the set of output match results. In some implementations, the matrix multiplication can be performed using a dot product engine of the first circuit.

A photonic content addressable memory employs cross coupled optical inverters to provide a bistable element that can be set or reset and interrogated optically. Optical switches controlled by the state of the bistable element can compare that state to optically conveyed pattern bits providing a “wired OR” on an output line quickly indicating matching along a logical row of data so stored. The bistable element can be simultaneously interrogated with different search patterns using parallel banks of optical switches tuned to different frequencies.

A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising a complement of the first sequence of bits. The search pattern is provided as input to a search line of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to conduct, and a signal is provided to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer, and the location is output.

Methods, devices, and systems for content addressable memory (CAM) loading in semiconductor devices are provided. In one aspect, an example memory device includes a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit includes CAMs, a data path, and a buffer circuit coupled to the CAMs through the data path. The buffer circuit includes a multiplexer coupled to a storage unit and a command / address (CA) interface. The multiplexer is configured to dynamically select either the storage unit or the CA interface.