126 results about "Content-addressable memory" patented technology

Techniques for maintaining cache coherency while sharing data among multiple processors are disclosed. Multiple coherent elements are arranged in an M×N mesh topology. An element can include a compute coherency block (CCB), and a coherency ordering agent (COA). The COAs include a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic. The CCB and COA include functions for interfacing with a hierarchical cache and directory snoop filter (DSF). A CCB from within one of the multiple coherent elements issues a read request. The corresponding directory snoop filter (DSF) is inspected to determine if there is a slot (way) available for storing information pertaining to the read request. In the event that no eligible vacancies are present in the DSF, a multi-pass process for handling a capacity limit in a DSF is performed.

Systems, apparatus, articles of manufacture, and methods are disclosed to configure content-addressable memory resources. An example apparatus includes interface circuitry to access parameters to be used to configure content-addressable memory (CAM) of a compute device to implement a packet flow table, machine-readable instructions, and at least one programmable circuit to be programmed by the machine-readable instructions. The at least one programmable circuit is to convert the parameters into a hardware representation of the packet flow table, generate, based on the hardware representation, candidate configurations of two or more CAM slices of the compute device that satisfy the parameters, select one of the candidate configurations of the two or more CAM slices to implement the packet flow table based on respective performance characteristics of the candidate configurations, and configure the two or more CAM slices based on the selected one of the candidate configurations.

Examples described herein relate to a network interface device. In some examples, the network interface device is configured to determine routing information for a packet by: access a content addressable memory (CAM) to retrieve an Internet Protocol (IP) subnetwork identifier based on a portion of a destination address of the packet; determine a starting memory address of a subnetwork in a memory based on the subnetwork identifier; determine an offset from the starting memory address based on a second portion of the destination address; access the memory to retrieve the routing information for the packet based on the offset and the starting memory address.

The present invention proposes a method for realizing in-memory computing based on a small-signal ferroelectric capacitor with non-destructive readout, belonging to the field of novel computing architectures. The present invention realizes the linearly inseparable comparison operation of a content-addressable memory (CAM) unit and the local multiplication operation of a signed synaptic unit on a ferroelectric capacitor, reducing the hardware cost. Compared with the method of distance measurement based on the traditional CAM architecture, it has higher computational linearity and detection range, as well as lower search power consumption; at the same time, compared with the resistive synaptic array, it has no DC power consumption and no potential DC conduction path, avoiding the "IR drop" problem of large-scale arrays, and has lower computational power consumption, showing significant advantages in edge machine learning tasks based on feature retrieval and neural network hardware acceleration.

A cache is used for efficiently storing a graph structure. The graph cache may be used in a computing system to accelerate processing of a graph by a graph neural network, and is different than a general-purpose memory of the computing system. Embeddings for the nodes of a graph are stored in the memory of the computing system, while the structure of the graph is stored in the graph cache. The graph cache may include a content addressable memory array, which may be suitable for efficiently representing a graph structure.

A cache is used for efficiently storing a graph structure. The graph cache may be used in a computing system to accelerate processing of a graph by a graph neural network, and is different than a general-purpose memory of the computing system. Embeddings for the nodes of a graph are stored in the memory of the computing system, while the structure of the graph is stored in the graph cache. The graph cache may include a content addressable memory array, which may be suitable for efficiently representing a graph structure.

Embodiments described herein relate to content addressable memory (CAM). An example CAM device comprises a back-end-of-line (BEOL) layer that is disposed over a front-end-of-line layer. A plurality of CAM cells are provided in the device, wherein each cell comprises a storage portion and a compare portion. In the example CAM device, the storage portion of each cell of the plurality of CAM cells is disposed in the FEOL layer and the compare portion of each cell of the plurality of CAM cells is disposed in the BEOL layer.

The present disclosure is directed to key-value data storage systems using content addressable memory. A memory system includes a memory device comprising a content addressable memory (CAM) block storing a plurality of stored search keys and a value data block. The memory system additionally includes a processing device that receives an input search key and identifies one of the plurality of stored search keys that matches the input search key, the one of the plurality of stored search keys having an associated matching orientation in the CAM block. The processing device further determines a corresponding value orientation in the value data block using the associated matching orientation and retrieves data representing a value associated with the input search key from the value orientation in the value data block.

Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array and a number of content-addressable control cells. Each control cell controls a respective display pixel of the pixel active array. Each control cell includes a comparator to generate a control signal to control the respective display pixel of the pixel active array based on a comparison between pixel data for the respective display pixel and one or more counters corresponding to a gray level.

Embodiments of the present disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learned storage memory. The analog output of the differentiable CAM can provide input to a learning algorithm that can compute gradients in comparison to historical values and reduce data inaccuracies and power consumption.

Various embodiments provide for using data search on content-addressable memory (CAM), such as CAM implemented using a NOT-AND (NAND)-type memory device, to facilitate data de-duplication, where the CAM and the data search can be part of a memory system (e.g., memory sub-system).

The present disclosure relates to a non-volatile content-addressable memory based on ferroelectric capacitors and an electronic device. The memory includes: a plurality of storage cells, each of which comprises: a first switch and a second switch connected to a first capacitor and a second capacitor, respectively; a first capacitor and a third capacitor, and a gate of a first transistor, all connected to a first node; a second capacitor and a fourth capacitor, and a gate of a second transistor, all connected to a second node; at least one of the first and third capacitors is a ferroelectric capacitor, and at least one of the second and fourth capacitors is a ferroelectric capacitor; and a control unit for inputting a control signal to control the storage cell to perform a target operation. The disclosed embodiments achieve non-destructive reading of data, improve the service life of the memory, and reduce operation delays and energy consumption.

Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

Methods, devices, and systems are provided for content addressable memory (CAM) loading in a semiconductor device. In one aspect, an example memory device includes a memory array and a peripheral circuit coupled to the memory array. The peripheral circuit includes a CAM, a data path, and a buffer circuit coupled to the CAM through the data path. The buffer circuit includes a multiplexer coupled to a memory device and a command / address (CA) interface. The multiplexer is configured to dynamically select either the memory or the CA interface.

The present disclosure provides a content addressable memory (CAM). The CAM includes a CAM register configured to store a mapping table, N comparators coupling to the CAM register, and N multiplexers coupling to the N comparators respectively and to the CAM register. The mapping table includes first addresses and second addresses. Each one of the first addresses corresponds to one of the second addresses. Each of the N comparators is configured to compare the first addresses with one of N input signals, where N is an integer greater than 1. The N input signals come from N microcontroller units. The N multiplexers is configured to generate N output signals. At least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.

This invention provides a Content Addressable Memory (CAM) unit, a CAM memory device, an operation method thereof, and a data search and comparison method. The CAM unit includes: a first flash memory unit, a first terminal of which receives a first search voltage; and a second flash memory unit, a first terminal of which receives a second search voltage, and a second terminal of the first flash memory unit electrically connected to a second terminal of the second flash memory unit; wherein the first flash memory unit and the second flash memory unit are connected in series, and a stored data in the content addressable memory unit is determined by a combination of multiple threshold voltages of the first flash memory unit and the second flash memory unit.

The invention relates to the field of artificial intelligence, and provides an in-memory computing system and method based on product cache, the system comprises a cache control module, an in-memory computing module, a feature cache module and a content addressable memory, the cache control module reads a current to-be-processed local feature map from the feature cache module, the content addressable memory is searched for according to the current local feature map to be processed, a corresponding hit address is obtained based on the inquired corresponding local feature map, and the hit address is input into the in-memory calculation module; and the in-memory calculation module reads the corresponding product result cached in advance according to the hit address, and obtains a task processing result according to the product result of all the corresponding images to be subjected to task processing. According to the method, on the basis of the data locality features in the visual task, the product of the pixel values of the locality features and the model weights is cached and reused, the multiplication calculation amount is effectively reduced, and high-energy-efficiency in-memory calculation is achieved.

A memory system includes a memory device comprising a content addressable memory (CAM) block storing a clustered or non-clustered index database comprising a plurality of stored search keys, wherein the plurality of stored search keys are sorted according to respective values of a first feature of a plurality of features. The memory system further comprises a processing device that receives an input search key comprising a search value for a second feature of the plurality of features, and identifies, without re-sorting the plurality of stored search keys, a subset of the plurality of stored search keys from the CAM block that match at least a portion of the input search key comprising the search value for the second feature of the plurality of features.

A satisfiability modulo theories (SMT) solver accelerator is implemented with analog content addressable memory (CAM) cells. A job-shop scheduling problem (JSSP) may be mapped to expression clauses that are stored in an analog CAM array. A test cycle may be performed by searching for a test vector of input variables in the analog CAM array, selecting a candidate variable of the test vector that is violating a largest number of the expression clauses, and changing the candidate variable of the test vector. The test cycle may be repeated until none of the expression clauses are violated by the test vector of the input variables. The resulting test vector of the input variables that violates no expression clauses is a solution for the JSSP.

The invention provides a message editing method and device, a medium and electronic equipment. The message editing method comprises the following steps: receiving an entry message; performing analysis processing on the message to obtain analysis information of the message; matching a destination media access control (DMAC) address in the two-layer information with a router port media access control (MAC) address to obtain a matching result of the DMAC address; if the matching result is successful matching, performing matching processing on a preset binary content addressable memory (BCAM) entry based on the two-layer information, the three-layer information, the four-layer information and the type information to obtain behavior information in the successfully matched preset BCAM entry, otherwise, reporting the entry message to a CPU system; and carrying out editing processing on the entrance message based on the behavior information to obtain an exit message. The method can reduce the processing time delay and relieve the processing pressure of the CPU.

The invention provides access error correction for content addressable memory. Examples of the disclosed technology provide a method for detecting and correcting errors (i.e., 'access' error correction) in a summed content addressable memory (sigma-CAM) when the sigma-CAM performs a compute task. The method involves adding redundant columns to a sigma-CAM for storing a task-driven matrix (i.e., a matrix having a value conforming to a computational task). Examples may utilize an encoder to calculate redundancy values for redundant columns such that the sigma-CAM stores codewords for linear codes (C) in each row. Examples also modify a linear code (C) used to calculate redundancy values. That is, examples modify the linear code (C) such that it includes an omni-vector. By this modification, the system of the present technology may detect and correct errors in the output vector from the sigma-CAM based on this modified / specific linear code (C).

This invention provides a 3-SAT completeness solver supporting CDCL non-temporally sequential backtracking. The completeness solver includes: a content-addressable memory-propagation unit (CAM) for single-word matching using CAM, performing word propagation and decision operations in a word watch loop, and generating a structured implication graph; an implication graph caching unit, connected at one end to the CAM and at the other to an in-memory computation learning unit, for storing the structural information of the structured implication graph; and an in-memory computation learning unit for performing conflict-driven clause learning CDCL based on the structural information of the structured implication graph, thereby achieving completeness analysis with non-temporally sequential backtracking. This invention enables completeness analysis of SAT problems using CDCL non-temporally sequential backtracking, fully utilizing the inherent structural characteristics of SAT problems, and providing an efficient completeness solution for complex SAT problems in practical applications.

This application discloses a device, method, and switching chip for preventing host hang-up, belonging to the field of computer bus and interface technology. The device for preventing host hang-up includes a message analysis and filtering module, an address and resource control module, a caching module, a content addressable memory module, a message inspection module, and a response message generation module. It parses, verifies, and timestamps messages sent to endpoint devices and caches their field information; it checks whether the message response has timed out or the destination port is faulty through a polling mechanism; when a response timeout or fault is detected, it automatically constructs a response message based on the original message fields and returns it to the host, releasing the host's occupied resources in a timely manner and preventing the system from hanging up.

The present invention is a process and structure of a ferroelectric neural network cell with self-learning capability and enhanced character recognition length. The ferroelectric neural network cell is a content addressable memory (CAM) structure (or FeCAM for short) based on a ferroelectric field-effect transistor (FeFET), and the FeCAM is a 1N1P-FeCAM including an N-type FeFET and a P-type FeFET. Therefore, the present invention reduces the number of devices to minimize cell area, and each cell consists of two complementary FeFETs to achieve a density that is 33% higher than that of Ternary CAM (TCAM). H2 plasma treatment (HPT) is effective in enhancing symmetry between ION1 and ION2 to increase the number of mismatch cells (Max HD, MHD). Therefore, the present invention is useful to graphic recognition and can be applied to various fields of artificial intelligence.

A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.

The invention belongs to the field of computer part manufacturing, and particularly discloses an NAND type content addressable memory circuit and an operation method. The circuit comprises an NAND type analog content addressable memory array, a pre-charging circuit and a comparator circuit. The input fixed-point number is compared with the stored fixed-point number bit by bit, a discharge path is formed according to a comparison result, and a word line load capacitor discharges through the path to obtain a corresponding word line voltage; and the voltage is input into the comparator circuit, and finally a data comparison result is output. According to the method, the size comparison of fixed-point numbers can be efficiently realized in parallel, the calculation complexity is greatly reduced, and the calculation rate is improved. In a big data or artificial intelligence application scene needing large-scale data comparison, a large amount of calculation overhead can be saved, and the calculation speed is improved.

The present disclosure relates to dual address command management using content addressable memory. A memory system includes a memory device and a processing device operatively coupled with the memory device. The processing device performs operations including, in response to receiving a memory access command, determining that the memory access command is a dual address command including a source address and a destination address, generating a first content addressable memory (CAM) entry associated with a read command of the dual address command, where the first CAM entry references the source address, generating a second CAM entry associated with a write command of the dual address command, where the second CAM entry references the destination address, inserting the first CAM entry and the second CAM entry into a CAM, and issuing the read command associated with the first CAM entry to the memory device.

Embodiments of the present disclosure relate to apparatus and methods for content-addressable memory (CAM) cells. Each CAM cell may include a latch portion that stores a bit of information. Each CAM cell may also include a comparator portion that compares an external bit with the stored bit. A group of CAM cells may be organized into a CAM register, wherein each CAM cell is commonly coupled to a signal line. If the external bit does not match the stored bit, any of the CAM cells may change the voltage on the signal line.

Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.