4 results about "Error detection and correction" patented technology

The invention discloses a multi-scene-oriented SRAM (Static Random Access Memory) adaptive error detection and correction control system and method, and relates to the technical field of SRAM unit error detection and correction, the system comprises a sensor, a sensor threshold judgment module, a CPU (Central Processing Unit), a register module, a parity check threshold judgment module and an intelligent decision control module; the CPU is connected with the register module through a CFGBUS bus; the output end of the register module is respectively connected with the sensor threshold judgment module and the parity check threshold judgment module; the output end of the sensor is connected with the sensor threshold judgment module; the intelligent decision control module is connected with the sensor threshold judgment module, the parity check threshold judgment module and the register module. According to the invention, through a multi-parameter sensing intelligent decision-making mechanism, the error processing strategies of different levels are dynamically and adaptively switched, so that on-demand optimization and real-time balance of chip performance, power consumption and reliability are realized.

A memory system includes a command buffer that services commands from a host processer via a memory controller to access data interleaved across multiple DRAM devices. The memory controller uses parity bits augmented with metadata for improved error detection and correction. Cache lines of data and parity bits are interleaved across the DRAM devices. Metadata for each cache line is stored in a separate, device-specific address in just one of the DRAM devices. The memory controller and command buffer save time and power by grouping accesses for metadata stored in different devices.

This disclosure provides a data access method, a memory controller, an electronic device, and a medium, relating to the field of chip technology. It includes: determining a first storage region in a memory cell of a dynamic random access memory (DRAM), the first storage region being used to store error detection and correction (ECC) data; responding to write command information corresponding to an access request, determining first ECC data corresponding to the write command information, the first ECC data being used to verify the write data corresponding to the write command information; storing the write data corresponding to the write command information and the first ECC data in the same first memory cell, the first ECC data being stored in the first storage region within the first memory cell. The method proposed in this disclosure, while ensuring data integrity, significantly reduces space overhead, row activation latency, and bandwidth usage, improving the effective bandwidth and access efficiency of DRAM.

The present application relates to the technical field of three-dimensional flash memory, and discloses a three-dimensional flash memory array system with vertically stacked multi-layer charge traps. The vertically stacked storage array module of the system determines an array structure configuration parameter set according to memory cell physical layout information; a gate voltage regulation module generates a gate voltage regulation parameter set based on the parameter set to optimize charge capture efficiency; a charge trap layer management module adjusts trap layer material and distribution accordingly to generate a dynamic regulation result; a data read-write optimization module adjusts voltage pulse parameters based on the result to generate read-write optimization data; and an error detection and correction module optimizes the error correction mechanism accordingly to generate a control table. Through the cooperation of multiple modules, the system realizes integrated optimization of charge storage, regulation, read-write and error correction under a multi-layer stacked structure, and adapts to performance improvement under high-density storage requirements.