13 results about "Error detection and correction" patented technology

To provide a monitoring control device capable of providing information usable to identify occurrence factors of bit errors in stored data.SOLUTION: Monitoring control devices 1a, 1b for monitoring facilities include: data creation parts 12 for creating monitoring control data on monitoring and controlling of facilities; information addition parts 13 for adding time stamps on the created monitoring control data when the monitoring control data are created; and coding parts 14 for creating check bits for detecting and correcting errors objective for the monitoring control data on which the time stamps are added to write them in store parts 15 by adding the created check bits to the monitoring control data in a state where the time stamps are added.SELECTED DRAWING: Figure 4

A NOR-type flash memory suitable for protection of data requiring high reliability and a method of operating the same are provided. The NOR-type flash memory of the present invention comprises: a memory cell array comprising a plurality of memory cells; an ECC circuit that performs error detection and correction of data read from the boot save area of the memory cell array; a means for storing, in the startup management area, identification information for identifying the error form of the faulty memory cell that has been subjected to error detection and correction by the ECC circuit; and a recovery component that recovers the faulty memory cell based on the identified error form to eliminate the error of the faulty memory cell.

The application provides a system and method for dual-BIOS starting of a spatial high-performance processor, comprising: a controller, configured to read a BIOS program before the processor is powered on, check the correctness of the BIOS program, correct BIOS program data errors if any, and forward the BIOS program that passes the check to the processor through an interface converter after the processor is powered on; the controller is also configured to control the power supply and reset of the processor, monitor the starting state and running state of the processor; and update the memory based on an update instruction; a memory, comprising a first BIOS memory and a second BIOS memory, configured to store the BIOS program and the check result of the controller; and a processor, configured to receive the BIOS program of the controller; the application can realize error detection and correction of single-bit errors, and can timely discover and correct single-bit errors through updating, thus meeting the demand of complex computing tasks and ensuring the stability and reliability of the system.

The present application provides a semiconductor memory device, which can shorten the processing time of error detection and correction. The flash memory (100) of the present application has a NAND chip (200) and an ECC chip (300). The NAND chip (200) has a dedicated input / output terminal (220) for transmitting data between the NAND chip (200) and the ECC chip (300), and the ECC chip (300) has a dedicated input / output terminal (320) for transmitting data between the NAND chip (200) and the ECC chip (300). When the readout operation is performed in the NAND chip (200), the NAND chip (200) transmits the readout data containing the parity data to the ECC chip (300) via the dedicated input / output terminal (220), and the ECC chip (300) performs error detection and correction of the readout data based on the parity data, and transmits the corrected data to the controller (400) via the input / output terminal (330).

The invention relates to the technical field of mine unmanned driving man-machine interaction, and particularly discloses a collaborative loading device and system for an unmanned mine vehicle, and the device comprises a loading point position adjustment module which is used for carrying out the initialization of a loading point position according to the loading data information of loading equipment, carrying out position and posture adjustment and intelligent maintenance of the loading point position; the mine vehicle scheduling module is used for carrying out queue planning of the unmanned mine vehicles and carrying out error detection and correction on loading points when the unmanned mine vehicles enter a loading area; and the mine vehicle abnormity processing module is used for monitoring the running state of the unmanned mine vehicle in real time and performing abnormity classification processing when the unmanned mine vehicle is determined to be abnormal according to the running state of the unmanned mine vehicle. According to the cooperative loading device for the unmanned mine vehicle, cooperative loading of the loading equipment and the unmanned mine vehicle is achieved through accurate positioning of the loading point position, intelligent matching of the loading strategy and safety linkage control.

The invention discloses a multi-scene-oriented SRAM (Static Random Access Memory) adaptive error detection and correction control system and method, and relates to the technical field of SRAM unit error detection and correction, the system comprises a sensor, a sensor threshold judgment module, a CPU (Central Processing Unit), a register module, a parity check threshold judgment module and an intelligent decision control module; the CPU is connected with the register module through a CFGBUS bus; the output end of the register module is respectively connected with the sensor threshold judgment module and the parity check threshold judgment module; the output end of the sensor is connected with the sensor threshold judgment module; the intelligent decision control module is connected with the sensor threshold judgment module, the parity check threshold judgment module and the register module. According to the invention, through a multi-parameter sensing intelligent decision-making mechanism, the error processing strategies of different levels are dynamically and adaptively switched, so that on-demand optimization and real-time balance of chip performance, power consumption and reliability are realized.

The invention discloses a multi-SOC-based camera controller on-orbit autonomous reconstruction system and method, and relates to the technical field of space camera master control. The invention aims to solve the problem that the single event effect (such as function error or disorder) of the SOC device is easily caused in the space intense radiation environment in the prior art. Comprising a main control unit, an SPI communication data line, a switch channel unit, a FLASH storage unit, a CAN bus communication unit, an RS-422 bus communication unit, a focusing control unit and a temperature control and detection unit. According to the invention, three SOCs are adopted to form hardware redundancy, on-orbit autonomous error detection and correction functions are realized, and the operation stability and reliability of the camera controller in a harsh space radiation environment are effectively improved. The switch channel unit is adopted to dynamically allocate the peripheral control right, when a certain SOC fails, the SOC can be seamlessly switched to a normal SOC to take over a peripheral channel of the SOC, and the function continuity is guaranteed; and after the fault SOC is recovered, the default configuration can be automatically switched back.

The invention relates to the technical field of three-dimensional flash memory storage, and discloses a three-dimensional flash memory array system with vertically stacked multi-layer charge traps. A vertical stacking storage array module of the system determines an array structure configuration parameter set according to physical layout information of a memory unit; a grid voltage regulation and control module generates a grid voltage regulation and control parameter set based on the parameter set so as to optimize the charge capture efficiency; the charge trap layer management module adjusts the material and distribution of the trap layer accordingly, and generates a dynamic regulation and control result; the data read-write optimization module adjusts voltage pulse parameters based on the result and generates read-write optimization data; and the error detection and correction module optimizes an error correction mechanism and generates a control table accordingly. According to the system, through cooperation of multiple modules, integrated optimization of charge storage, regulation and control, read-write and error correction under a multi-layer stacked structure is achieved, and performance improvement under the requirement of high-density storage is adapted.

A memory system includes a command buffer that services commands from a host processer via a memory controller to access data interleaved across multiple DRAM devices. The memory controller uses parity bits augmented with metadata for improved error detection and correction. Cache lines of data and parity bits are interleaved across the DRAM devices. Metadata for each cache line is stored in a separate, device-specific address in just one of the DRAM devices. The memory controller and command buffer save time and power by grouping accesses for metadata stored in different devices.

This disclosure provides a data access method, a memory controller, an electronic device, and a medium, relating to the field of chip technology. It includes: determining a first storage region in a memory cell of a dynamic random access memory (DRAM), the first storage region being used to store error detection and correction (ECC) data; responding to write command information corresponding to an access request, determining first ECC data corresponding to the write command information, the first ECC data being used to verify the write data corresponding to the write command information; storing the write data corresponding to the write command information and the first ECC data in the same first memory cell, the first ECC data being stored in the first storage region within the first memory cell. The method proposed in this disclosure, while ensuring data integrity, significantly reduces space overhead, row activation latency, and bandwidth usage, improving the effective bandwidth and access efficiency of DRAM.

The present application relates to the technical field of three-dimensional flash memory, and discloses a three-dimensional flash memory array system with vertically stacked multi-layer charge traps. The vertically stacked storage array module of the system determines an array structure configuration parameter set according to memory cell physical layout information; a gate voltage regulation module generates a gate voltage regulation parameter set based on the parameter set to optimize charge capture efficiency; a charge trap layer management module adjusts trap layer material and distribution accordingly to generate a dynamic regulation result; a data read-write optimization module adjusts voltage pulse parameters based on the result to generate read-write optimization data; and an error detection and correction module optimizes the error correction mechanism accordingly to generate a control table. Through the cooperation of multiple modules, the system realizes integrated optimization of charge storage, regulation, read-write and error correction under a multi-layer stacked structure, and adapts to performance improvement under high-density storage requirements.

The invention discloses an AI digital human real-time communication technology optimization method and system, and belongs to the technical field of digital human real-time communication, and the method comprises the steps: employing a lightweight deep learning model, and reducing the model parameters and calculation amount, thereby reducing the occupation of a video memory; the model pruning and quantification technology is implemented, and the model size and the video memory requirement are further reduced; dynamically adjusting the video memory distribution of the digital human model according to the current video memory use condition and task requirements; when the video memory is insufficient, the model resolution is automatically reduced or part of non-key functions are closed, so that the communication fluency is ensured; a low-delay communication protocol is adopted, and data transmission delay is reduced; the data compression and transmission optimization technology is implemented, and the data transmission quantity is reduced; a timestamp synchronization technology is adopted to ensure real-time synchronization of actions and voices of the digital human; an error detection and correction mechanism is implemented to improve the reliability of data transmission. According to the invention, the efficiency and fluency of the digital human real-time communication can be improved, and the optimization of the digital human real-time communication is realized.

The invention discloses a modulation cancellation translation error detection method suitable for a super-large array element synthetic aperture system. The method comprises the following steps: firstly, applying translation error modulation to a reference sub-aperture to obtain a PSF image sequence, and performing spectrum cancellation on adjacent images to obtain a feature image sequence; then extracting a plurality of groups of feature values corresponding to translation error information of each sub-aperture from the feature image sequence, and fitting an optimal response position in a change process by using a Gaussian function to realize coarse calibration of translation errors of each non-reference sub-aperture; and finally, phase modulation is applied to the reference sub-aperture, spectrum cancellation is carried out on PSF images before and after modulation, phase information is extracted from an obtained feature image, and fine calibration of translation errors of each non-reference sub-aperture is realized. Wide-range and high-precision translation error detection and correction can be realized under any aperture arrangement, additional optical elements and spectral prior information are not needed, the anti-noise capability is extremely high, and the method is suitable for the synthetic imaging requirement under the condition of ultra-large array element number in the future.