22 results about "Error detection and correction" patented technology

The invention discloses an AI-based online homework correction method and system, and the method comprises the steps: carrying out the feature extraction of text content, logic structure and language expression through a multi-dimensional feature extraction model according to the homework data submitted by a student; according to the multi-dimensional feature vectors, a subject knowledge base and logical reasoning rules are combined, and error detection and correction are conducted through a logical reasoning network; according to the homework feature vector, in combination with a teacher scoring standard and a student ability evaluation index, performing scoring and ability analysis by using a dynamic scoring and ability evaluation model; and generating a personalized feedback report by using a generative adversarial network according to a scoring result and a capability evaluation result. According to the embodiment of the invention, various errors in the homework can be efficiently and accurately identified and corrected, personalized feedback is provided, and the quality and effect of online education are improved.

To provide a monitoring control device capable of providing information usable to identify occurrence factors of bit errors in stored data.SOLUTION: Monitoring control devices 1a, 1b for monitoring facilities include: data creation parts 12 for creating monitoring control data on monitoring and controlling of facilities; information addition parts 13 for adding time stamps on the created monitoring control data when the monitoring control data are created; and coding parts 14 for creating check bits for detecting and correcting errors objective for the monitoring control data on which the time stamps are added to write them in store parts 15 by adding the created check bits to the monitoring control data in a state where the time stamps are added.SELECTED DRAWING: Figure 4

The present invention relates to an information transmission method, device, and storage medium, wherein the method comprises: step S1: obtaining a predicted value of information transmission efficiency based on real-time network bandwidth data; step S2: based on the predicted value of information transmission efficiency and in combination with real-time network load, adjusting the capacity division of data packets and configuring the transmission priority, thereby generating a data packet transmission configuration; step S3: based on the data packet transmission configuration and in combination with real-time network bandwidth, calculating the data packet transmission time and determining the data packet compression level; step S4: generating a hierarchically compressed data packet based on the compression hierarchical calculation result; and step S5: performing error detection and correction during transmission based on the hierarchically compressed data packet, performing data integrity verification on the transmitted data packet, and generating an information transmission verification result. Compared with the prior art, the present invention has the advantages of reducing data transmission time and improving network utilization.

A NOR-type flash memory suitable for protection of data requiring high reliability and a method of operating the same are provided. The NOR-type flash memory of the present invention comprises: a memory cell array comprising a plurality of memory cells; an ECC circuit that performs error detection and correction of data read from the boot save area of the memory cell array; a means for storing, in the startup management area, identification information for identifying the error form of the faulty memory cell that has been subjected to error detection and correction by the ECC circuit; and a recovery component that recovers the faulty memory cell based on the identified error form to eliminate the error of the faulty memory cell.

The application provides a system and method for dual-BIOS starting of a spatial high-performance processor, comprising: a controller, configured to read a BIOS program before the processor is powered on, check the correctness of the BIOS program, correct BIOS program data errors if any, and forward the BIOS program that passes the check to the processor through an interface converter after the processor is powered on; the controller is also configured to control the power supply and reset of the processor, monitor the starting state and running state of the processor; and update the memory based on an update instruction; a memory, comprising a first BIOS memory and a second BIOS memory, configured to store the BIOS program and the check result of the controller; and a processor, configured to receive the BIOS program of the controller; the application can realize error detection and correction of single-bit errors, and can timely discover and correct single-bit errors through updating, thus meeting the demand of complex computing tasks and ensuring the stability and reliability of the system.

A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

The invention discloses a double-driven-shaft synchronous error correction system based on grating displacement detection, and relates to the technical field of grating detection, the double-driven-shaft synchronous error correction system comprises a double-driven-shaft structure, the double-driven-shaft structure comprises a moving frame, a transverse moving screw rod is rotatably installed on the moving frame, a sliding rod is fixedly installed on the moving frame, and a moving sliding block is slidably installed on the sliding rod; the moving sliding block and the transverse moving screw rod are in threaded fit, a moving sliding rod is fixedly installed on the moving sliding block, an adjusting sliding block is installed on the moving sliding rod in a sliding mode, a turnover frame is rotatably installed on the adjusting sliding block, a sliding sleeve is rotatably installed on the turnover frame, a grating emission source is installed on the sliding sleeve in a sliding mode, and a transverse moving sliding frame is installed on the moving frame in a sliding mode. Double-driven-shaft synchronous movement detection is carried out on grating displacement, and error detection and correction are carried out by comparing the overlapping degree of two groups of symmetrical gratings.

The present application provides a semiconductor memory device, which can shorten the processing time of error detection and correction. The flash memory (100) of the present application has a NAND chip (200) and an ECC chip (300). The NAND chip (200) has a dedicated input / output terminal (220) for transmitting data between the NAND chip (200) and the ECC chip (300), and the ECC chip (300) has a dedicated input / output terminal (320) for transmitting data between the NAND chip (200) and the ECC chip (300). When the readout operation is performed in the NAND chip (200), the NAND chip (200) transmits the readout data containing the parity data to the ECC chip (300) via the dedicated input / output terminal (220), and the ECC chip (300) performs error detection and correction of the readout data based on the parity data, and transmits the corrected data to the controller (400) via the input / output terminal (330).

The invention relates to the technical field of mine unmanned driving man-machine interaction, and particularly discloses a collaborative loading device and system for an unmanned mine vehicle, and the device comprises a loading point position adjustment module which is used for carrying out the initialization of a loading point position according to the loading data information of loading equipment, carrying out position and posture adjustment and intelligent maintenance of the loading point position; the mine vehicle scheduling module is used for carrying out queue planning of the unmanned mine vehicles and carrying out error detection and correction on loading points when the unmanned mine vehicles enter a loading area; and the mine vehicle abnormity processing module is used for monitoring the running state of the unmanned mine vehicle in real time and performing abnormity classification processing when the unmanned mine vehicle is determined to be abnormal according to the running state of the unmanned mine vehicle. According to the cooperative loading device for the unmanned mine vehicle, cooperative loading of the loading equipment and the unmanned mine vehicle is achieved through accurate positioning of the loading point position, intelligent matching of the loading strategy and safety linkage control.

The present invention provides a semiconductor memory device and a readout method, which can realize high-speed error detection and correction processing and achieve miniaturization. The flash memory (100) of the present invention has a NAND chip (200) and an ECC chip (300). The NAND chip (200) includes a memory array and a page buffer / sensing circuit including a latch (L1) and a latch (L2). The ECC chip (300) includes RAM_E and RAM_O. The RAM_E and RAM_O store readout data output from the latches (L1, L2) of the NAND chip (200). RAM_E stores data of even-numbered sectors, and RAM_O stores data of odd-numbered sectors. The data size of RAM_E and RAM_O can be reduced by making RAM_E or RAM_O alternately store sector data.

The present invention provides a semiconductor storage device and an error detection and correction method, achieving coexistence of error detection and correction capabilities and write or read performance. The error detection and correction method of the flash memory of the present invention includes: a setting step of setting selection information for selecting a first error detection and correction function for performing 1-bit error detection and correction or a second error detection and correction function for performing multi-bit error detection and correction; and an execution step of executing the first error detection and correction function or the second error detection and correction function based on the set selection information during a read operation or a write operation.

To provide a game play analysis system capable of not only determining the presence or absence of a malfunction of a game but also specifying the details of the malfunction and providing such information to developers or the like.SOLUTION: A debug processing device 10 is a device for performing debugging (error detection and correction) for a given game executed by a game device 20, and is configured to execute a game play analysis process that analyzes the content of game play during game execution on the basis of predetermined determination criteria (information) and game play information output from the game device 20, and notify an administrator of information related to the analysis content of the game play.SELECTED DRAWING: Figure 4

The invention discloses a multi-scene-oriented SRAM (Static Random Access Memory) adaptive error detection and correction control system and method, and relates to the technical field of SRAM unit error detection and correction, the system comprises a sensor, a sensor threshold judgment module, a CPU (Central Processing Unit), a register module, a parity check threshold judgment module and an intelligent decision control module; the CPU is connected with the register module through a CFGBUS bus; the output end of the register module is respectively connected with the sensor threshold judgment module and the parity check threshold judgment module; the output end of the sensor is connected with the sensor threshold judgment module; the intelligent decision control module is connected with the sensor threshold judgment module, the parity check threshold judgment module and the register module. According to the invention, through a multi-parameter sensing intelligent decision-making mechanism, the error processing strategies of different levels are dynamically and adaptively switched, so that on-demand optimization and real-time balance of chip performance, power consumption and reliability are realized.

The invention discloses a multi-SOC-based camera controller on-orbit autonomous reconstruction system and method, and relates to the technical field of space camera master control. The invention aims to solve the problem that the single event effect (such as function error or disorder) of the SOC device is easily caused in the space intense radiation environment in the prior art. Comprising a main control unit, an SPI communication data line, a switch channel unit, a FLASH storage unit, a CAN bus communication unit, an RS-422 bus communication unit, a focusing control unit and a temperature control and detection unit. According to the invention, three SOCs are adopted to form hardware redundancy, on-orbit autonomous error detection and correction functions are realized, and the operation stability and reliability of the camera controller in a harsh space radiation environment are effectively improved. The switch channel unit is adopted to dynamically allocate the peripheral control right, when a certain SOC fails, the SOC can be seamlessly switched to a normal SOC to take over a peripheral channel of the SOC, and the function continuity is guaranteed; and after the fault SOC is recovered, the default configuration can be automatically switched back.

The invention discloses a mechanical arm control method and device capable of resisting single event upset, and the mechanical arm control method adopts a first processing unit with an error detection and correction function and a second processing unit without the error detection and correction function for control. Wherein an algorithm execution module of the second processing unit is embedded in the first processing unit, and the method comprises the following steps: the first processing unit receives a mode switching instruction sent by an external control end, and determines a mode flag bit according to the mode switching instruction; the first processing unit receives a mechanical arm control instruction; when the mode flag bit is in a first state, the first processing unit forwards a received mechanical arm control instruction to the second processing unit for execution; and when the mode flag bit is in the second state, the first processing unit calls the algorithm execution module to directly execute the mechanical arm control instruction. According to the invention, single event upset resistance can be realized with low cost and high reliability.

The invention relates to the technical field of three-dimensional flash memory storage, and discloses a three-dimensional flash memory array system with vertically stacked multi-layer charge traps. A vertical stacking storage array module of the system determines an array structure configuration parameter set according to physical layout information of a memory unit; a grid voltage regulation and control module generates a grid voltage regulation and control parameter set based on the parameter set so as to optimize the charge capture efficiency; the charge trap layer management module adjusts the material and distribution of the trap layer accordingly, and generates a dynamic regulation and control result; the data read-write optimization module adjusts voltage pulse parameters based on the result and generates read-write optimization data; and the error detection and correction module optimizes an error correction mechanism and generates a control table accordingly. According to the system, through cooperation of multiple modules, integrated optimization of charge storage, regulation and control, read-write and error correction under a multi-layer stacked structure is achieved, and performance improvement under the requirement of high-density storage is adapted.

A memory system includes a command buffer that services commands from a host processer via a memory controller to access data interleaved across multiple DRAM devices. The memory controller uses parity bits augmented with metadata for improved error detection and correction. Cache lines of data and parity bits are interleaved across the DRAM devices. Metadata for each cache line is stored in a separate, device-specific address in just one of the DRAM devices. The memory controller and command buffer save time and power by grouping accesses for metadata stored in different devices.

This disclosure provides a data access method, a memory controller, an electronic device, and a medium, relating to the field of chip technology. It includes: determining a first storage region in a memory cell of a dynamic random access memory (DRAM), the first storage region being used to store error detection and correction (ECC) data; responding to write command information corresponding to an access request, determining first ECC data corresponding to the write command information, the first ECC data being used to verify the write data corresponding to the write command information; storing the write data corresponding to the write command information and the first ECC data in the same first memory cell, the first ECC data being stored in the first storage region within the first memory cell. The method proposed in this disclosure, while ensuring data integrity, significantly reduces space overhead, row activation latency, and bandwidth usage, improving the effective bandwidth and access efficiency of DRAM.

The present application relates to the technical field of three-dimensional flash memory, and discloses a three-dimensional flash memory array system with vertically stacked multi-layer charge traps. The vertically stacked storage array module of the system determines an array structure configuration parameter set according to memory cell physical layout information; a gate voltage regulation module generates a gate voltage regulation parameter set based on the parameter set to optimize charge capture efficiency; a charge trap layer management module adjusts trap layer material and distribution accordingly to generate a dynamic regulation result; a data read-write optimization module adjusts voltage pulse parameters based on the result to generate read-write optimization data; and an error detection and correction module optimizes the error correction mechanism accordingly to generate a control table. Through the cooperation of multiple modules, the system realizes integrated optimization of charge storage, regulation, read-write and error correction under a multi-layer stacked structure, and adapts to performance improvement under high-density storage requirements.

The invention discloses an AI digital human real-time communication technology optimization method and system, and belongs to the technical field of digital human real-time communication, and the method comprises the steps: employing a lightweight deep learning model, and reducing the model parameters and calculation amount, thereby reducing the occupation of a video memory; the model pruning and quantification technology is implemented, and the model size and the video memory requirement are further reduced; dynamically adjusting the video memory distribution of the digital human model according to the current video memory use condition and task requirements; when the video memory is insufficient, the model resolution is automatically reduced or part of non-key functions are closed, so that the communication fluency is ensured; a low-delay communication protocol is adopted, and data transmission delay is reduced; the data compression and transmission optimization technology is implemented, and the data transmission quantity is reduced; a timestamp synchronization technology is adopted to ensure real-time synchronization of actions and voices of the digital human; an error detection and correction mechanism is implemented to improve the reliability of data transmission. According to the invention, the efficiency and fluency of the digital human real-time communication can be improved, and the optimization of the digital human real-time communication is realized.

The present invention discloses a system supporting distributed synchronous computing, including a motion control device group including a multi-core DSP processor, which is interconnected through an SRIO bus, a single-board computer, a switching card, a synchronous control module, a dynamic load balancing module, and a cross-core direct connection channel, with downlink directional distribution and error detection and correction functions. The synchronous control module has five synchronization signals, each with different functions and an internal priority judgment and queuing mechanism. The single-board computer has a predictive data pre-fetching mechanism and an encryption chip. The cross-core direct connection channel is established with a specific process. The machine learning algorithm of the dynamic load balancing module has an adaptive update mechanism. The local clock of the motion control device can be calibrated. The present invention has many advantages, such as improving operating efficiency, ensuring accurate and orderly data transmission, coordinating system synchronous operation, protecting data security, avoiding network congestion, and improving data transmission accuracy.

The invention discloses a modulation cancellation translation error detection method suitable for a super-large array element synthetic aperture system. The method comprises the following steps: firstly, applying translation error modulation to a reference sub-aperture to obtain a PSF image sequence, and performing spectrum cancellation on adjacent images to obtain a feature image sequence; then extracting a plurality of groups of feature values corresponding to translation error information of each sub-aperture from the feature image sequence, and fitting an optimal response position in a change process by using a Gaussian function to realize coarse calibration of translation errors of each non-reference sub-aperture; and finally, phase modulation is applied to the reference sub-aperture, spectrum cancellation is carried out on PSF images before and after modulation, phase information is extracted from an obtained feature image, and fine calibration of translation errors of each non-reference sub-aperture is realized. Wide-range and high-precision translation error detection and correction can be realized under any aperture arrangement, additional optical elements and spectral prior information are not needed, the anti-noise capability is extremely high, and the method is suitable for the synthetic imaging requirement under the condition of ultra-large array element number in the future.