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Semiconductor memory device

a semiconductor memory and memory device technology, applied in the field of semiconductor memory devices, can solve the problems of increasing the error rate of data rewrite operations, the error rate of flash memories, and the error rate of non-volatile semiconductor memory devices,

Inactive Publication Date: 2008-04-03
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0015] a warning signal generating circuit configured to generate a warning signal designating that there are 4-bit or more errors in case syndromes are not in an all “0” state, and in case no error location is searched with whichever of the 3EC system and 2EC system.

Problems solved by technology

Electrically rewritable and non-volatile semiconductor memory devises, i.e., flash memories, increase in error rate with increasing of the number of data rewrite operations.
In particular, as a memory capacity increases and the miniaturization is enhanced, the error rate increases more.

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
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Examples

Experimental program
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Embodiment Construction

[0084] Illustrative embodiments of this invention will be explained with reference to the accompanying drawings below.

[0085] There has already been provided by this inventor such a method that 2-bit error correction may be performed with a high-speed operation in place of the conventional method, in which finite elements are sequential substituted in the error searching equation to solve it.

[0086] That is, to perform error location search at a high rate with BCH code on GF(256), form a table for designating solution candidacy, and compare syndrome indexes calculated from read out data of a memory with the table to obtain a solution. In detail, an error searching equation including syndromes calculated from the read data is solved. In this case, the error searching equation is divided into a part including only unknown numbers (refer to as a variable part, hereinafter) and another part to be calculated by syndromes (refer to as a syndrome part) by use of variable transformation, so...

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Abstract

A semiconductor memory device including an error detecting and correcting system, wherein the error detecting and correcting system includes a 3EC system configured to be able to detect and correct 3-bit errors, and wherein the 3EC system is configured to search errors in such a manner that 3-degree error searching equation is divided into a first part containing only unknown numbers and a second part calculative with syndromes via variable transformation by use of two or more parameters, and previously nominated solution indexes collected in a table and syndrome indexes are compared to each other.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2006-230375, filed on Aug. 28, 2006, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to a semiconductor memory device, more specifically, to an error detection and correction system adaptable for use therein. [0004] 2. Description of the Related Art [0005] Electrically rewritable and non-volatile semiconductor memory devises, i.e., flash memories, increase in error rate with increasing of the number of data rewrite operations. In particular, as a memory capacity increases and the miniaturization is enhanced, the error rate increases more. In this view point, it becomes a material technique to mount an ECC circuit on a flash memory chip. [0006] There has been provided such a technique that an ECC circuit is formed on a fl...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F11/00
CPCG06F11/1068H03M13/1575H03M13/152
Inventor TODA, HARUKI
Owner KK TOSHIBA
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