460results about "Code conversion" patented technology

A distributed system and method uses a virtual management layer to classify incoming heterogeneous data streams by type, attach association flags to related streams, and route each stream to a selected compression or decompression subsystem executing on available computing devices. The virtual layer allocates tasks using live resource conditions to enable parallel processing across devices and per-type optimization (e.g., statistical, codebook, or neural techniques). Outputs returned from disparate devices are collected and deterministically regrouped using the association flags so related streams are preserved regardless of where processing occurred. The architecture supports both compression and decompression workflows, load-balanced scheduling, and scalable operation across multiple devices, improving throughput while maintaining relationships among multi-type data.

An embodiment according to the invention relates to a decoder for providing decoded parameters of a neural network based on an encoded representation, the decoder configured to use decoding of neural network parameters to obtain a first multidimensional array comprising a plurality of neural network parameter values, the decoder configured to use reordering to obtain a reordered multidimensional array, wherein a first dimension of the first multidimensional array is rearranged to a different dimension within the reordered multidimensional array. Further disclosed is an encoder, a method and a computer program using reordering.

This invention relates to the fields of near-memory computing and integrated circuits, and discloses a sparse data compression circuit and a near-memory computing chip for near-memory computing. The invention includes: a first rearrangement unit, which rearranges the sparse input data of the current cycle into locally compact data; a buffer unit, which stores the buffer data of the previous cycle; a control unit, connected to the buffer unit, which generates an offset control signal based on the buffer data; a second rearrangement unit, connected to the first rearrangement unit, the buffer unit, and the control unit, which, based on the offset control signal, concatenates the effective data of the locally compact data and the buffer data, and outputs the concatenated data; and an output unit, connected to the buffer unit and the second rearrangement unit, which, when the concatenated data reaches a preset transmission bit width, extracts data corresponding to the preset transmission bit width from the concatenated data as target data for output, and stores the remaining data in the concatenated data as buffer data in the buffer unit. This addresses the overall data throughput performance problem in near-memory computing systems.

According to one embodiment, a magnetic disk device includes a disk, a write head, a volatile buffer memory, a parity generation unit, a write processing unit, an error correction unit, a storage processing unit, and a conventional correction limit prediction unit. The parity generation unit generates first conventional parity, first potential parity, second conventional parity and second potential parity. The storage processing unit overwrites the second potential parity to a first recoding area if the first prediction information is normal information, and leaves the first potential parity in the first recording area and stores the second potential parity in a second recording area if the first prediction information is replaced with abnormal information.

One approach may include at least partially initializing the mesh of the SE engine based at least in part on predetermined state information about the communication channel associated with the incoming data stream; and processing the incoming data stream via the MLSE engine to further initialize the mesh and decode the incoming data stream.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a wireless communication device may transmit, via a first transmission of a hybrid automatic repeat request (HARQ) procedure, a first set of information bits, wherein the first set of information bits are encoded into a first polar codeword of a first size. The wireless communication device may transmit, via a second transmission of the HARQ procedure, the first set of information bits and a second set of information bits, wherein the first set of information bits and the second set of information bits are jointly encoded into a second polar codeword of a second size. Numerous other aspects are described.

A data processing method using a plurality of devices for Artificial Intelligence (AI) task, the method comprising: transmitting transmission data including detection data, determining whether an error has occurred in the transmission data based on the detection data, and when the error has not occurred in the transmission data, performing an operation task based on the transmission data, wherein receiving side detection data is derived based on the transmission data, and whether the error has occurred in the transmission data is determined based on the receiving side detection data and the detection data included in the transmission data.

Methods and system for converting a plurality of weights of a filter of a Deep Neural Network (DNN) in a first number format to a second number format, the second number format having less precision than the first number format, to enable the DNN to be implemented in hardware logic. The method comprising: determining, for each of the plurality of weights, a quantisation error associated with quantising that weight to the second number format in accordance with a first quantisation method; determining a total quantisation error for the plurality of weights based on the quantisation errors for the plurality of weights; identifying a subset of the plurality of weights to be quantised to the second number format in accordance with a second quantisation method based on the total quantisation error for the plurality of weights; and generating a set of quantised weights representing the plurality of weights in the second number format, the quantised weight for each weight in the subset of the plurality of weights based on quantising that weight to the second number format in accordance with the second quantisation method and the quantised weight for each of the remaining weights of the plurality of weights based on quantising that weight to the second number format in accordance with the first quantisation method.

The present application provides a kind of data processing method and data processing device, electronic equipment and non-transient computer readable storage medium, the method includes in response to the decompression instruction of data, the check of received compressed data is executed;In the case where check passes, according to the preset continuous data length, the compressed data is divided into multiple data segments, wherein the compressed data is compressed according to the preset continuous data length;The decompression operation of the multiple data segments in the preset address space is respectively executed, and the decompressed data is obtained;Whether the decompressed data is consistent with the data amount of the original data corresponding to the compressed data is compared;In the case where data amount is consistent, the decompression task of the compressed data is ended.According to embodiment, by dividing compressed data into multiple data segments and performing double check on decompressed data, not only the accuracy of data decoding is improved, but also the speed and efficiency of decompression are improved.

An error correction circuit includes an error processing circuit, a poison processing circuit, and a data pattern conversion circuit. The error processing circuit receives data, generates delayed data, a parity signal, and syndrome information, and outputs error correction data generated by correcting errors in the data according to the syndrome information. The poison processing circuit outputs one of a write poison flag and a read poison flag as a poison pattern control signal in accordance with a write command. The data pattern conversion circuit converts the delayed data and the parity signal into a poison pattern according to the poison pattern control signal and outputs the poison pattern.

The present application relates to the field of microwave photon, provide a kind of microwave photon array system cross-scale simulation data compression method, equipment, medium and product, the method comprises: preprocessing original microwave photon signal data, obtain denoising signal data and noise signal data;Based on DCT transformation and adaptive quantization, the denoising signal data is compressed;Noise signal data is extracted statistical characteristic parameter;According to the compression result of denoising signal data, reconstruct denoising signal data;According to the statistical characteristic parameter of noise signal data, reconstruct noise signal data;According to the denoising signal data and noise signal data of reconstruction, obtain reconstructed microwave photon signal data.The present application can effectively reduce the data scale of transmission and storage in the cross-scale simulation of microwave photon array system, help to improve system simulation evaluation efficiency.

Innovations in range asymmetric numeral systems (“RANS”) encoding and decoding are described herein. Some of these innovations relate to hardware implementations of RANS decoding that organize operations in two stages, which can improve computational efficiency of RANS decoding. Other innovations relate to adapting RANS encoding / decoding to different distributions or patterns of values for symbols. For example, RANS encoding / decoding can be adapted by switching a default symbol width (number of bits per symbol), adjusting the symbol width on a per-fragment basis for different symbol fragments, switching between different static probability models on a per-fragment basis for different symbol fragments, and / or selectively flushing (or preserving) a state of a RANS decoder on a per-fragment basis for different symbol fragments. In many cases, such innovations can improve compression efficiency while also providing computationally efficient performance.

An LDPC code-based communication method and a communication apparatus are provided. There is a nested relationship between base graphs, so that a base graph of a small scale can be derived based on a base graph of a large scale. The communication apparatus may store a base graph of a largest scale. When another base graph needs to be used for encoding or decoding, the communication apparatus may derive a required base graph based on the base graph of the largest scale. In this way, content that needs to be stored by the communication apparatus can be reduced.

Systems and methods for fast multi-length payload error correcting includes at least a decoder circuit. The decoder circuit receives a first input and receives a second input. The decoder circuit generates, based on the first input, a first decoded payload. The first decoded payload includes at least a first data or a first length and a first flip bit. The decoder circuit generates, based on the second input, a second decoded payload. The second decoded payload includes at least a second data of a second length and a second flip bit, the second length being different from the first length.

Various aspects of the present disclosure generally relate to wireless communication, and to supporting physical broadcast channel (PBCH) scrambling and soft combining that supports larger synchronization signal block (SSB) periodicity. For example, a network node may transmit multiple SSBs in accordance with an SSB periodicity. The SSBs respectively include multiple PBCHs, and the PBCHs respectively include multiple master information blocks (MIBs) in accordance with an MIB periodicity. Each of the PBCHs includes a respective scrambled portion and a respective unscrambled portion. The unscrambled portions each include timing information in accordance with the SSB periodicity and the MIB periodicity. The UE decodes the PBCHs by soft combining the PBCHs in accordance with the timing information and descrambles resulting scrambled PBCH payloads in accordance with scrambling sequences associated with the unscrambled portions.

The invention relates to a method for operating an ultrasonic sensor, the associated sensor, the data transmission to a computer system and the associated decompression method in the computer system that controls the ultrasonic sensor.The compression procedure comprises the steps of acquiring an ultrasound received signal from an ultrasound transducer, providing a signal-free ultrasound echo signal model (610), performing the following steps at least once, optionally multiple times: subtracting a reconstructed ultrasound echo signal model (610) from the ultrasound received signal (1) and generating a residual signal (660); performing a procedure for detecting signal objects in the residual signal (660); supplementing the ultrasound echo signal model (610) with the parameterized signal waveform of a detected signal object (600 to 605); and terminating the repetition of these steps when the magnitude values ​​of the residual signal are below the magnitude values ​​of a predetermined threshold signal.This is followed by the transmission of at least some of the detected signal objects, in the form of symbols for these detected signal objects, to the computer system, where at least some of the detected signal objects are used. Preferably, these are reconstructed in the computer system into a reconstructed ultrasound echo signal model.

The application provides a digital content adaptive generation method and system based on scene semantic understanding, and relates to the technical field of data processing. The method comprises the following steps: copying each data unit in an input data set to generate at least two mirror data units, alternately inserting the mirror data units with different sequence bias identifiers to construct multiple data chains, setting a breakpoint position in each data chain to construct a multi-chain interlaced network, identifying the concentration degree of the data units to obtain a structure aggregation amount, dividing each data chain into several sections according to the change amplitude of the data units, folding the data units in the sections, recording the number of path bifurcations in the tracing process, identifying the change offset degree of the data to obtain a sequence offset amount, combining different levels of intervals with each other and establishing a rule code, matching content units for different rule codes, and obtaining target content data. The application ensures that the generated digital content matches the actual input state through semantic understanding.

The present application relates to multi-candidate successive cancellation list (SCL) decoding of polar codes. In an example, an apparatus processes multiple candidate codewords using a same SCL decoder. The SCL decoder may be cyclic redundancy code (CRC)-aided. The multiple candidate codewords may have different code configurations and / or different inputs. In an example, the multiple candidate codewords are packaged so that at most one of the candidate codewords in the package is valid.

The application provides a multimodal large model compression method and device based on sparse codebook quantization, and relates to the technical field of computer vision, wherein the method comprises the following steps: optimizing a visual encoder to make the weight significance distribution of an arbitrary large-scale visual-language model more concentrated; evaluating the influence of each layer weight of the optimized language model on the output through second-order information, and dynamically allocating the code word quantity of each weight group according to the significance; determining the optimal sparse combination from a large-scale codebook by adopting a two-stage strategy of high-level candidate search and low-level subset refinement; and completing model quantization by combining the combination and sparse coefficients, so as to balance the compression and inference performance. The dynamic code word allocation and hierarchical search method based on sparse coding does not need additional training, can adaptively allocate the optimal sparse code word combination, can keep the model expression ability under extremely low bits, and can improve the quantization compression efficiency and inference performance.

A processing-in-memory (PIM) device implements block quantization techniques for matrix-vector operations. The PIM device performs matrix-vector operations between portions of a weight matrix and an input vector, and copies results to a register. A read operation retrieves the copied results while additional matrix-vector operations are performed in parallel. The device may apply scaling factors to the results using multipliers within the PIM device. In some implementations, the weight matrix includes data columns and scaling factor columns interspersed at regular intervals. The scaling factors may be applied to accumulated results using parallel multiplication operations. Disclosed techniques enable efficient implementation of block quantization for applications such as Large Language Models while managing computational resources within the PIM architecture.

A data compression device (100) that compresses discrete time series data including a plurality of continuous values, the continuous values being constituted by one or more data points representing the same value that are consecutive in the time series, includes a noise determination section (11). When each continuous value included in the time series data is taken as a target continuous value, the noise determination section (11) determines the target continuous value to be noise in a case where the duration of the target continuous value is less than a specified duration and the difference between the value of the target continuous value and the value of the data point immediately preceding the start point of the target continuous value in the time series is equal to or less than a difference threshold. The noise determination section (11) determines the target continuous value to be not noise in a case where the duration of the target continuous value is equal to or more than the specified duration and the difference between the value of the target continuous value and the value of the data point immediately preceding the start point of the target continuous value in the time series is equal to or less than the difference threshold. The noise determination section (11) generates compressed data that is data in which each continuous value determined to be noise is not represented, each continuous value determined to be not noise is represented, and the time series data is compressed.

The application discloses a finite field error correction encoding and decoding method and system for an integrated storage and calculation system, which is suitable for error correction tasks after sum and accumulation in analog in-memory calculation and error correction tasks of reading data from a general memory. The application uses non-binary q-order finite field operation to process input code words, uses a preprocessed generating matrix to obtain an encoding result belonging to the finite field and generate an error correction code, and restores at an output end, so that the error rate of in-memory calculation results is reduced and the reliability is improved. Based on the encoding and decoding method, the application discloses a corresponding decoding circuit system design, which is divided into a check node and a variable node, the connection between the check node and the variable node is defined by a check matrix, and belief propagation based on a finite field is adopted. After multiple iterations of belief propagation between the check node and the variable node, the error correction result converges and the final decoding result is obtained.

A communication device may include: a processor configured to perform a procedure comprising: receiving a first consensus check code from a first communication device; receiving a second consensus check code from a second communication device; generating a combination code by network encoding the first consensus check code and the second consensus check code; and instructing the transmission of the combination code to the first communication device and to the second communication device.

In some implementations, an apparatus may include a transmitter and one or more processors. The one or more processors may be configured to identify, according to a code rate of 3 / 4 and a code block size of 3888 bits, a first binary parity check matrix for a quasi-cyclic-low-density parity-check (QC-LDPC) code. The first binary parity check matrix may correspond to a first exponent matrix having 144 values. The one or more processors may be configured to encode data using the first binary parity check matrix. The one or more processors may be configured to transmit the encoded data.

This invention provides an encoding and decoding method and apparatus for Structured Low-Density Parity-Check (LDPC) codes. The encoding method includes: determining a base matrix for encoding, the base matrix comprising one or more submatrices, the submatrices including a top-left submatrix Hb1 and a top-left submatrix Hb2, wherein the number of rows and columns of the top-left submatrix Hb1 and Hb2 are both less than the number of rows and columns of the base matrix Hb, and the top-left submatrix Hb1 is the top-left submatrix of the top-left submatrix Hb2; performing LDPC encoding operations on the source information bit sequence based on the base matrix and the corresponding extension factor Z to obtain a codeword sequence, where Z is a positive integer greater than or equal to 1. The above technical solution provided by this invention solves the problems of insufficient flexibility and inability to support incremental redundancy HARQ in related technologies for LDPC encoders and decoders.

The application provides a cache-restricted LT code degree distribution optimization method based on reinforcement learning, comprising the following steps: S1, generating a source symbol sequence with a length of k; S2, constructing a reinforcement learning agent for determining a degree distribution of a transmitting end, the reinforcement learning agent is composed of a 2-node input layer, a 2k-node hidden layer and a k-node output layer; S3, updating a current degree value through the reinforcement learning agent, and performing LT coding on the degree value and the source symbol by an encoder to obtain a coded symbol and send the coded symbol to a receiving end decoder; S4, judging the degree value of the received coded symbol according to the currently recovered source symbol by the decoder, and performing a cache or decoding according to the degree value; S5, training the reinforcement learning agent by using the reinforcement learning environment in step S3, and finally obtaining a degree distribution that makes the reward tend to be maximum through iterative training. The application can obtain a degree distribution with smaller redundancy overhead required for full recovery under the condition of cache restriction.

An apparatus (200) of decoding a video, a method of encoding a video and a computer-readable storage medium are disclosed. Embodiments obtain a bin string corresponding to a transformation coefficient level syntax element indicating a size of transformation coefficient included in a transformation unit from a bit stream. Embodiments determine whether to update a previous parameter by comparing a size of a previous transformation coefficient that is restored before a current transformation coefficient. Embodiments obtain the size of the current transformation coefficient by de-binarizing the current transformation coefficient level syntax element by using the obtained current parameter.