768results about "Cyclic codes" patented technology

The invention provides a multi-feature information hidden document integrity verification and tampering positioning method, and relates to the field of network security and digital document protection. The multi-feature information hidden document integrity verification and tampering positioning method comprises the following steps: S1, document multi-dimensional feature extraction and encryption: based on an original Word document, adopting an SHA-3 algorithm to calculate a full-text hash value as a content feature, and extracting document object model features such as paragraph hierarchy, table structure and the like through a DOM tree analyzer; after the two types of features are combined into a feature matrix, a dynamic secret key is generated through Logistic chaotic mapping for XOR encryption, and an encrypted document feature matrix is generated. A dynamic key is generated by combining Logistic chaotic mapping encryption through a multi-dimensional extraction technology fusing document content hash values and structural features, so that the anti-cracking capability of a feature matrix is remarkably improved, the confidentiality of document features in open network transmission is ensured, the block information retention rate is simulated and predicted by adopting Monte Carlo, and the watermark embedding weight is dynamically allocated.

The present invention belongs to the technical field of decoding algorithms, and specifically relates to normalized minimum sum decoding of BCH codes and post-processing decoding methods thereof, the steps of which include optimizing the standard form of the check matrix of the BCH code to obtain the best check matrix; inputting the received sequence into the improved normalized minimum sum decoding algorithm NMS based on the best check matrix for decoding; if the decoding is successful, outputting the best decoding estimate; if the decoding fails, inputting the sequence iteration trajectory after the NMS decoding failure into the DIA neural network model, analyzing and outputting the reliability metric of each bit, and then decoding again through the ordered statistical decoder OSD to obtain the best decoding estimate. The present invention successfully achieves the low density of the check matrix, the reduction of the number of short loops, and the uniform distribution of column weights through an innovative check matrix optimization algorithm, and provides a more efficient and better performance BCH code decoding solution.

The invention relates to the field of distributed storage, in particular to an erasure code algorithm processing method for cold and hot fragmented data in a distributed storage system in a local area network or a wide area network, and solves the problems caused by using an erasure code algorithm to process cold and hot data in the prior art. The method comprises the steps of data block partitioning, a parameter strategy of data cold and hot judgment, a parameter strategy of node cold and hot judgment, data writing, an erasure code algorithm processing mechanism of different types of data, processing after erasure code algorithm processing, data cold and hot conversion processing and the like. Meanwhile, normal read-write performance is kept not affected by erasure code processing in the EC coding processing process, and the rationality of cold and hot data division in the distributed storage system is improved; layered storage and migration are performed according to cold and hot data, the read-write performance of distributed storage is considered, and the capacity utilization rate is increased; and the reliability, fault tolerance and performance of the storage system are improved.

The invention belongs to the technical field of decoding algorithms, and particularly relates to a normalized minimum sum decoding and post-processing decoding algorithm of a BCH code, which comprises the following steps of: for the BCH code, optimizing a check matrix in a standard form of the BCH code to obtain an optimal check matrix; inputting the receiving sequence into an improved normalized minimum sum (NMS) decoding algorithm based on the optimal check matrix for decoding; if the decoding is successful, outputting the optimal decoding estimation; and if the decoding fails, inputting a sequence iteration track after the NMS decoding fails into the DIA neural network model, analyzing and outputting the reliability measurement of each bit, and then decoding again through an ordered statistical decoder OSD to obtain the optimal decoding estimation. Through an innovative check matrix optimization algorithm, low density of the check matrix, reduction of the number of short rings and uniform distribution of column weights are successfully realized, and a BCH code decoding scheme which is more efficient and better in performance is provided.

The present invention belongs to the technical field of BCH code decoding, and specifically relates to an error correction decoding method based on BCH codes. The steps include constructing a neural network model suitable for UDE detection. If the output result is approval, decoding ends; otherwise, it is determined to be an undetectable decoding error (UDE), triggering an ordered statistical decoder (OSD) for further decoding; constructing a DIA correction model to improve the bit reliability metric of the received sequence before OSD decoding; using the ALMLT algorithm to obtain the order of test error patterns as the initial value of the OSD decoding path, and then obtaining the frequency distribution characteristics of the actual error pattern or estimated error pattern corresponding to the decoded codeword, continuously fine-tuning the order of the test error patterns, obtaining an optimized decoding path, and performing OSD decoding on the BCH code. The present invention significantly improves the reliability and efficiency of BCH codes in NMS decoding, while reducing computational complexity and latency.

At least one embodiment of the invention provides a data processing method, a data processing device and a data transmission system. The data processing method comprises the steps that coding operation is carried out based on original data to generate N independent error correction code words, each error correction code word in the N independent error correction code words comprises a data code and a check code, and N is an integer and is larger than or equal to 2; data codes and check codes included in the N independent error correction code words are interleaved to obtain interleaved data; and sending the interleaved data. According to the data processing method, the complexity of coding, decoding and error correction can be effectively reduced, the corresponding coding, decoding and error correction time is shortened, and the data transmission delay is reduced.

This application discloses an Ethernet coding method and apparatus, to adapt to a scenario in which a higher transmission bit error rate is caused by a high bandwidth. The method includes: a transmit end encodes first to-be-encoded information by using a first forward error correction (FEC) codeword, to obtain first encoded data, where the first forward error correction FEC codeword is a Reed-Solomon forward error correction (RS-FEC) codeword; and the transmit end encodes the first encoded data by using a second FEC codeword, to obtain second encoded data, where a code length N and an information bit length K of the second FEC codeword satisfy the following formula: M1*N / K≤M2, where M1 is a throughput of the first encoded data, and M2 is a throughput of the second encoded data.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G systems and 6G systems. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality (XR) service or a low-delay service.

Embodiments of the present disclosure include techniques for error correction. Multiple successive odd syndromes are generated from input data comprising parity bits. Coefficients are generated and applied to a finite element field to detect multiple bit errors. Error correction circuitry corrects detected error bits. A single bit error detector may detect single bit errors. The error correction circuit may select between a single bit error vector and a multibit error vector based on one of the coefficients. The circuitry may be implemented in combinational logic to perform detection and correction in a single clock cycle.

A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.

The embodiment of the invention discloses a data writing method and device which are used for reducing memory consumption of a client in a distributed storage system. The method comprises the steps that the client receives a first data block written by a user, wherein the first data block is used for being written into a target stripe in the storage device; the client generates a first temporary check block based on the first data block. And the client sends the first data block and the first temporary verification block to the server. And the server stores the first data block and the first temporary verification block to a storage device. The server determines that the first data block is a tail data block of the target stripe, erasure code merging is carried out on the first temporary check block and a second temporary check block, a merged target check block is obtained, and the second temporary check block comprises one or more temporary check blocks generated by other data blocks except the first data block in the target stripe. And the server stores the target verification block to a storage device.

Methods, systems, and devices for wireless communications are described. A user equipment (UE) may transmit an indication to a network entity that the UE is capable of decoding Reed-Solomon codes and that the UE is capable of performing near maximal likelihood demodulation. The network entity may transmit a message indicating that a Reed-Solomon code is applied to one or more scheduled signals based at least in part on the indication. The network entity may apply Reed-Solomon coding to a signal of the one or more scheduled signals based at least in part on the message. The UE may apply near maximal likelihood demodulation and Reed-Solomon decoding to a received signal of the one or more scheduled signals based at least in part on the message.

The embodiment of the invention provides a data coding method and a related device. The coding complexity is reduced while the code word length and the redundancy cost of an inner code are not changed. Specifically, for a first data stream subjected to outer code coding, every continuous k bits in the first data stream need to be subjected to inner code coding, and k is an odd number greater than 1. The other bits except one target bit in the k bits are subjected to XOR pairwise to obtain (k-1) / 2 bits in total. Further, a bit sequence including (k-1) / 2 bits and a target bit is subjected to second FEC coding to obtain p check bits. Wherein the n bits in the code word of the inner code after the inner code is coded comprise continuous k bits and p check bits. It can be seen that the embodiment of the invention adopts a mode of first exclusive OR and then encoding, for example, code word processing of (128, 119) can be realized through an encoder of (69, 60), and the encoding complexity is reduced while the code word length of an inner code and the redundancy cost are not changed.

The invention discloses an encoder, an encoding method and a chip, relates to the technical field of encoding, and aims to overcome the technical defect that a feedback loop in the encoder cannot converge in time sequence under the scene of large-bandwidth and high-parallelism input. The encoder comprises a feed-forward module which is used for receiving data to be encoded at the parallelism degree of n symbols per beat, and calculating a single-beat polynomial corresponding to the current beat in a finite field according to the symbols in the data to be encoded received by the current beat. The feedback module is used for receiving the single-beat polynomial which is output by the feed-forward module and corresponds to the current beat, and performing calculation in a finite field according to the single-beat polynomial which corresponds to the current beat and a first polynomial which represents symbols received by historical beats to obtain a second polynomial, and the second polynomial is used for determining a target polynomial which represents data to be coded; the target polynomial is used for generating a check sequence of the to-be-coded data, so that code words obtained after the to-be-coded data is coded in a forward error correction coding mode are obtained.

An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

The embodiment of the invention discloses a data processing method and a related device. Specifically, for a first data stream subjected to outer code coding, the first data stream is subjected to inner code coding to obtain a second data stream comprising at least one inner code word. Wherein the inner code coding adopts GF (28) error correction 2-bit extended BCH coding, the inner code codeword comprises 119 information bits and 17 check bits, the total number of the bits is 136, and the 17 check bits comprise 1-bit CRC extended check bit. That is to say, the embodiment of the invention adopts single-bit extended BCH (136, 119) coding with 2 bits of error correction capability. In an existing 400G ZR scene, data filling and convolutional interleaving between outer code coding and inner code coding are realized by taking 119 bits as granularity, so that the inner code coding scheme provided by the embodiment of the invention is compatible with the 400G ZR scene, and meanwhile, the cascade coding performance is also improved.

A method includes monitoring processing of a writing process associated with a plurality of sets of encoded data slices to storage units of the storage network in accordance with error encoding parameters to produce write processing performance information, where for a set of encoded data slices of the plurality of sets of encoded data slices, the error encoding parameters include an error coding number and a decode threshold number. When the write processing performance information compares unfavorably to a desired write performance range, the method further includes adjusting at least one of the error coding number and the decode threshold number to produce adjusted error encoding parameters for writing subsequent sets of encoded data slices of the plurality of sets of encoded data slices.

The invention provides an anti-counterfeiting traceability system and method based on a Braille dot matrix code, and the method comprises the steps: associating the multi-dimensional information of a whole life cycle of a product with the Braille dot matrix code through constructing a Braille dot matrix code generation rule of a fusion encryption algorithm and an error correction mechanism; storing the associated braille dot matrix code and product information to a block chain node to form a non-tampering traceability data chain; during verification, braille dot matrix codes are analyzed through visual scanning or tactile recognition, product information is extracted and subjected to consistency verification with hash values stored in the block chain, and tactile feedback interaction is provided for visually impaired users; and finally, anti-counterfeiting verification and full-process traceability of the product are realized, the use requirements of common users and visually impaired users are considered, and the problems that the existing anti-counterfeiting technology is easy to copy, the traceability data are unreliable and the traceability data are not friendly to visually impaired groups are solved.

This document discloses techniques, apparatuses, and systems for secure multi-rail control for sparsely encoded signals. Integrated circuits (ICs) may transmit various signals to manage interactions between circuit components of the IC. These critical signals are common targets for malicious attacks because, when altered, they can cause the IC to perform differently than is intended, and in some cases, bypass security measures. While various strategies may be used to protect against these attacks, modern circuit synthesis tools may optimize away these security measures, leaving the IC vulnerable to manipulation. In contrast, the secure multi-rail control for sparsely encoded signals described herein utilizes multiple rails to transmit sparsely encoded critical signals. Each rail may be controlled by a separate finite state machine (FSM) to reduce vulnerabilities that may arise due to circuit synthesis, provide an adjustable solution that may be leveraged differently based on implementation, and provide comportability to different ICs.

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

An apparatus may receive T copies of data that includes a cyclic redundancy check (CRC). T is an even number greater than or equal to 4. The apparatus may determine a first set of bit positions, at each of which T / 2 copies of the data have a same first bit value different from a same second bit value of the other T / 2 copies of the data, determine a second set of bit positions, at each of which more than T / 2 copies of the data have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the first set of bit positions and the second set of bit positions, an error contained in the first copy.

An apparatus may receive a first copy, a second copy and a third copy of data including a cyclic redundancy check (CRC) code, determine that a number of one or more bit positions, at each of which at least two of the first copy, the second copy or the third copy have bit values different from each other, is greater than a threshold value, divide the one or more bit positions into a first set of bit positions corresponding to the threshold value and remaining bit positions, determine, among the remaining bit positions, a second set of bit positions at each of which both the second copy and the third copy have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the second set of bit positions, an error in the first copy.

Methods and apparatus for replication of data in storage networks. In an embodiment, a processing module(s) of a computing device identifies a first storage set and a second storage set for replicated storage of data. The processing module(s) maintains a synchronization log for the first storage set and the second storage set. After initiating storage of a data object in the first storage set and the second storage set, the processing module(s) detects an unavailability of one or more storage units of the second storage set. In response to detecting a return to availability of the one or more storage units, the processing module(s) determines, based on the synchronization log, that the second storage set requires at least a portion of the data object to maintain synchronization with the first storage set, and facilitates storage of the at least a portion of the data object in the second storage set.

In an alignment marker search method, a first module receives a first data stream, where the first data stream is obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream includes an AM and data from at least one FEC codeword, and the reference granularity is a quantity of bits corresponding to n symbols included in the FEC codeword; obtains a first data segment from a first location in the first data stream at the reference granularity; and performs AM search on the first data segment. The reference granularity is the quantity of bits corresponding to the n symbols. Therefore, when a burst bit error occurs in the first data stream, a quantity of symbols affected by the burst bit error is small.

The invention relates to a robust watermarking method of a diffusion model based on an error correction code, which belongs to the technical field of large model watermarking, and comprises the following steps of: encoding a watermark message by using a Reed-Solomon error correction code to generate a code word containing redundancy check information; carrying out randomization processing on the code word to generate a pseudo-random bit stream; embedding the pseudo-random bit stream into a variable of an initial Gaussian potential space of a diffusion model by adopting a distribution preserving sampling technology; and finally, generating an image with a watermark through a denoising process of the diffusion model. When the watermark is extracted, reverse diffusion processing is carried out on an image which is possibly damaged to recover an approximate value of a potential space variable, a code word which is possibly damaged is extracted from the approximate value, and original watermark information is recovered by utilizing the error correction capability of a Reed-Solomon decoder. On the premise of keeping the generation performance, the robustness of the watermark to compression, noise, cutting and other potential tampering attacks is enhanced.

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

According to various embodiments of the present disclosure, the provided operation method of a first node in a communication system comprises the steps of: receiving at least one synchronization signal from a second node; receiving control information from the second node; determining one of two entanglement distillation protocols (EDPs) by using a predicted resource usage amount based on an initial fidelity and a target fidelity shared in advance with the second node, the two EDPs including a quantum error correcting codes (QECCs)-based EDP and a quantum private authentication (QPA) protocol; determining one or more parameters related to the EDP on the basis of the initial fidelity and the target fidelity by using an EDP parameter table shared in advance with the second node; performing the EDP on the basis of the one or more parameters; and, on the basis of the EDP result, preserving one or more Einstein-Podolsky-Rosen (EPR) states related to the EDP result, or discarding the one or more EPR states related to the EDP result and repeating the EDP.

The present method relates to a method by which a device receives a signal in a communication system, and an apparatus therefor, and to a method by which a reception device processes a signal in a communication system, and an apparatus therefor, the method comprising the steps of: receiving an encoded bit sequence; and decoding the encoded bit sequence in the direction from a root node to the lowest node on the basis of a binary tree structure, wherein, in the decoding step, decoding for a child node is skipped on the basis that a syndrome of a parent node satisfies a predetermined condition, and decoding for the child node is performed on the basis that the syndrome of the parent node does not satisfy the predetermined condition.