303results about "Cyclic codes" patented technology

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G systems and 6G systems. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality (XR) service or a low-delay service.

The invention provides an anti-counterfeiting traceability system and method based on a Braille dot matrix code, and the method comprises the steps: associating the multi-dimensional information of a whole life cycle of a product with the Braille dot matrix code through constructing a Braille dot matrix code generation rule of a fusion encryption algorithm and an error correction mechanism; storing the associated braille dot matrix code and product information to a block chain node to form a non-tampering traceability data chain; during verification, braille dot matrix codes are analyzed through visual scanning or tactile recognition, product information is extracted and subjected to consistency verification with hash values stored in the block chain, and tactile feedback interaction is provided for visually impaired users; and finally, anti-counterfeiting verification and full-process traceability of the product are realized, the use requirements of common users and visually impaired users are considered, and the problems that the existing anti-counterfeiting technology is easy to copy, the traceability data are unreliable and the traceability data are not friendly to visually impaired groups are solved.

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

An apparatus may receive T copies of data that includes a cyclic redundancy check (CRC). T is an even number greater than or equal to 4. The apparatus may determine a first set of bit positions, at each of which T / 2 copies of the data have a same first bit value different from a same second bit value of the other T / 2 copies of the data, determine a second set of bit positions, at each of which more than T / 2 copies of the data have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the first set of bit positions and the second set of bit positions, an error contained in the first copy.

An apparatus may receive a first copy, a second copy and a third copy of data including a cyclic redundancy check (CRC) code, determine that a number of one or more bit positions, at each of which at least two of the first copy, the second copy or the third copy have bit values different from each other, is greater than a threshold value, divide the one or more bit positions into a first set of bit positions corresponding to the threshold value and remaining bit positions, determine, among the remaining bit positions, a second set of bit positions at each of which both the second copy and the third copy have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the second set of bit positions, an error in the first copy.

In an alignment marker search method, a first module receives a first data stream, where the first data stream is obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream includes an AM and data from at least one FEC codeword, and the reference granularity is a quantity of bits corresponding to n symbols included in the FEC codeword; obtains a first data segment from a first location in the first data stream at the reference granularity; and performs AM search on the first data segment. The reference granularity is the quantity of bits corresponding to the n symbols. Therefore, when a burst bit error occurs in the first data stream, a quantity of symbols affected by the burst bit error is small.

The invention relates to a robust watermarking method of a diffusion model based on an error correction code, which belongs to the technical field of large model watermarking, and comprises the following steps of: encoding a watermark message by using a Reed-Solomon error correction code to generate a code word containing redundancy check information; carrying out randomization processing on the code word to generate a pseudo-random bit stream; embedding the pseudo-random bit stream into a variable of an initial Gaussian potential space of a diffusion model by adopting a distribution preserving sampling technology; and finally, generating an image with a watermark through a denoising process of the diffusion model. When the watermark is extracted, reverse diffusion processing is carried out on an image which is possibly damaged to recover an approximate value of a potential space variable, a code word which is possibly damaged is extracted from the approximate value, and original watermark information is recovered by utilizing the error correction capability of a Reed-Solomon decoder. On the premise of keeping the generation performance, the robustness of the watermark to compression, noise, cutting and other potential tampering attacks is enhanced.

The invention belongs to the technical field of spaceflight electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system capable of resisting single event upset, in particular to a bit-symbol double-layer error correction method of RS decoding operator error correction based on finite field algebra cascading on the basis of two-out-of-three majority voting logic. Single-particle independent upset and multi-copy common-mode failure can be corrected at the same time, and the problem of traditional TMR error locking is solved. Meanwhile, when configuration data are written into a nonvolatile memory, a cross-sector space staggered and dispersed storage mechanism is introduced, symbols in the same RS code word are separated as far as possible in physical positions, and therefore aggregated physical damage is converted into dispersed symbol-level errors.

The invention provides a temporary check block repairing method and system based on erasure codes in distributed block storage, and the method comprises the steps that a distributed block storage system detects that a check block fails to be written in, and a metadata service creates a temporary check block according to an erasure code mode; the temporary check block records an operation log and executes data writing, and replays IO operation according to a data version number; repairing the inconsistency of the data blocks by using the operation log of the temporary check block; and quickly recovering the check block data through the data bitmap of the temporary check block. According to the rapid recovery processing method for the temporary check block, the check block data can be directly recovered without a coding mode, the internal IO is reduced, and the recovery speed of the erasure code check block is increased.

An apparatus may include one or more processors and a receiver configured to receive first audio data having one or more gain spikes and retransmission of a first copy of the first audio data. The one or more processors may determine a first set of bit positions each having a sensitivity value higher than a threshold value, the sensitivity value indicating a degree of sensitivity of audio quality to bit errors at each bit position, determine that a second set of bit positions, at each of which the first audio data and the first copy have bit values different from each other, include at least one of the first set of bit positions, and modify the first audio data to eliminate a gain spike corresponding to the at least one of the first set of bit positions.

A method and apparatus for decoding syndromes of a quantum error correction code is disclosed. The method includes the steps of receiving syndrome data for a plurality of quantum error correction rounds performed on a plurality of qubits; identifying a plurality of first blocks within the syndrome data, wherein each first block has a respective first central block surrounded by one or more respective first buffer blocks; decoding each first block to obtain a first committed correction for each respective first central block; identifying a plurality of second blocks within the syndrome data, wherein each second block comprises at least part of at least one first buffer block; and decoding each second block to obtain a second committed correction for each second block. An apparatus including a plurality of block decoders and a process manager is disclosed.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G and 6G. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality XR service or another low-delay service.

Systems and methods for error detection in quantum computing systems are provided. In one example, the method includes obtaining a multi-dimensional quantum error detection map. The multi-dimensional quantum error detection map represents one or more quantum error detection measurements over a period of time. The method includes determining a partitioning scheme and a fusion scheme for the multi-dimensional quantum error detection map based at least in part on the decoding delay and the fusion delay. The method includes partitioning the multi-dimensional quantum error detection map into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection map based at least in part on the fusion scheme. The method includes operating a quantum computing system based at least in part on the decoded detection map.

This invention discloses an image-based scale recognition method, comprising the following steps: 1) Designing scale lines for computer recognition: 1.1) Setting patterns at the left and right ends of the scale lines to distinguish the left and right boundaries; 1.2) Encoding the middle scale value of the scale lines; 2) Attaching the scale lines to the side wall of the liquid container being measured; 3) Acquiring scale line images: Using a camera to capture images of the scale lines at the side wall of the liquid container; 4) Sending the acquired scale line images to an algorithm recognizer: 4.1) Detecting and locating the scale area through the left and right boundaries of the image; if there is inversion or tilt, correcting the scale area; 4.2) Recognizing the scale lines and converting the scale line encoding into a bit sequence; 4.3) Performing error detection and correction; 5) Outputting the scale value. This invention provides a novel scale encoding pattern that facilitates computer recognition and achieves high accuracy.

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Systems, apparatuses and methods provide technology that identifies a codeword associated with a fluid cooling system and a network system, generates a status update with the network system, embeds the codeword as a repeating cyclic codeword in a message containing the status update, transmits the message from the network system to the fluid cooling system over a data link, receives the message at the fluid cooling system, and determines, with the fluid cooling system, whether interference is inserted into the message based on the repeating cyclic codeword in the message.

The present invention teaches a method of pairing two user worn devices including collecting first and second biometric activity from respective first and second user worn devices to create first and second biometric signals, processing the first and second biometric signals to create first and second keys and determining if the keys match to allow for pairing of the two user worn devices. The first and second biometric activity may be the same or different biometric activities. The processing of the biometric signals is adjusted based upon the types of biometric activities being sensed.

Coded stream processing is provided. A system and method for encoding streaming data to facilitate recovery from faulty or slow processor (s) is described herein. A batch of processing stream data may be partitioned into a plurality of data blocks. The parity block (s) are used for a plurality of data blocks. The plurality of data blocks and parity block (s) may be provided to a processor for processing. Processed data of at least some (e.g., one or more) data blocks of the plurality of data blocks and processed data of parity block (s) are received. When it is determined that processed data for a predefined number of data blocks has not been received within a predefined time period, the parity block (s) is received based at least in part on the received processed parity block (s) and the received processed data block (s). The processed data is determined for the particular data block (s) of the particular processor (s) from which the processed data is not received.

A system includes a memory controller, multiple memories coupled to the memory controller, and multiple controlling components coupled to the memory controller. The memory controller calculates an error correction code (ECC) syndrome of a first type for a segment of data; stores the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories; receives a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component implementing an ECC syndrome of a second type; transforms the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type; detects a number of errors, if any, present in the segment of data; and takes further action depending on how many errors are detected.

This invention discloses a method for generating and repairing a system MSR code with the minimum number of packets, relating to the fields of computer and distributed storage technology. The method includes: for a distributed storage system consisting of n nodes, defining the structure of an (n,k,d) system MSR code; wherein the system MSR code has n code blocks, the first k code blocks are used as information nodes, and the remaining n-k code blocks are used as check nodes. All information is stored in the information nodes, and the k information nodes are grouped. The number of packets in the system MSR code is then calculated based on the defined system MSR code structure, generating the (n,k,d) system MSR code in a finite field. This invention employs a specific MSR construction method to construct the system MSR code, enabling it to have a smaller number of packets, and utilizes fixed parameters combined with code calculation to achieve a system MSR code with the minimum number of packets, and generates the corresponding check matrix.

Systems and methods for fast multi-length payload error correcting includes at least a decoder circuit. The decoder circuit receives a first input and receives a second input. The decoder circuit generates, based on the first input, a first decoded payload. The first decoded payload includes at least a first data or a first length and a first flip bit. The decoder circuit generates, based on the second input, a second decoded payload. The second decoded payload includes at least a second data of a second length and a second flip bit, the second length being different from the first length.

The invention belongs to the technical field of telecommunication, and discloses a two-dimensional RS code encoding and decoding method for streaming media data transmission. The method comprises the following steps: dynamically setting a coding parameter set based on network state data and application service data; constructing a finite field I and a finite field II based on the coding parameter set; constructing a Vandermonde matrix inverse matrix set based on the finite field 2; constructing an RS code generation matrix based on the finite field I, the finite field II and the Vandermonde matrix inverse matrix set; performing two-dimensional coding on the K original data packets based on an RS code generation matrix and a Vandermonde matrix inverse matrix set to generate R redundant data packets; the receiving end carries out decoding according to the received original data packets and the redundant data packets, and if the number of the received data packets is K, the K original data packets are directly recovered; if the V redundant data packets and the K-V original data packets are received, decoding recovery operation is carried out; according to the invention, accurate error correction and controllable fault tolerance of streaming media data transmission are realized.

This disclosure describes techniques that include implementing network-efficient data durability or data reliability coding on a network. In one example, this disclosure describes a method that includes generating a plurality of data fragments from data to enable reconstruction of the data from a subset of the plurality of data fragments; storing, across a plurality of nodes in a network, the plurality of data fragments, wherein storing the plurality of data fragments includes storing the first fragment at a first node and the second fragment at a second node; and generating, by the first node, a plurality of secondary fragments derived from the first fragment to enable reconstruction of the first fragment from a subset of the plurality of secondary fragments; and storing the plurality of secondary fragments from the first fragment across a plurality of storage devices included within the first node.

The application provides a decoding method, an encoding method, a device, a chip and a computing device. The method comprises the following steps: a decoding device acquires a first matrix, and then decodes a first code word vector according to the first matrix to obtain a decoding result. The first matrix is a 0-1 matrix representing elements in a second matrix on a polynomial ring. The second matrix is a check matrix on a finite field 2q, and the number of rows is r and the number of columns is n. A first polynomial corresponding to the polynomial ring is a q-th irreducible polynomial on a binary field. The number of 1s in the first matrix is less than the number of 1s in the 0-1 matrix representation of the second matrix. The first code word vector comprises k information code elements and r check code elements, and n=k+r. Each code element comprises q data units, and each data unit comprises at least one bit. The scheme can effectively reduce the hardware implementation complexity and cost of RS encoding and decoding.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a soft-aided decoder (112) to produce decoded bits (118) using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal (soft-aided bit marking) that are computed by calculation (114) and marking blocks (116) based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. The hard-decision (HD) forward error correcting (FEC) coded signal may be, for example, a staircase code (SCC) coded signal or a product code (PC) coded signal.