162results about "Cyclic codes" patented technology

The invention provides an anti-counterfeiting traceability system and method based on a Braille dot matrix code, and the method comprises the steps: associating the multi-dimensional information of a whole life cycle of a product with the Braille dot matrix code through constructing a Braille dot matrix code generation rule of a fusion encryption algorithm and an error correction mechanism; storing the associated braille dot matrix code and product information to a block chain node to form a non-tampering traceability data chain; during verification, braille dot matrix codes are analyzed through visual scanning or tactile recognition, product information is extracted and subjected to consistency verification with hash values stored in the block chain, and tactile feedback interaction is provided for visually impaired users; and finally, anti-counterfeiting verification and full-process traceability of the product are realized, the use requirements of common users and visually impaired users are considered, and the problems that the existing anti-counterfeiting technology is easy to copy, the traceability data are unreliable and the traceability data are not friendly to visually impaired groups are solved.

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

The invention relates to a robust watermarking method of a diffusion model based on an error correction code, which belongs to the technical field of large model watermarking, and comprises the following steps of: encoding a watermark message by using a Reed-Solomon error correction code to generate a code word containing redundancy check information; carrying out randomization processing on the code word to generate a pseudo-random bit stream; embedding the pseudo-random bit stream into a variable of an initial Gaussian potential space of a diffusion model by adopting a distribution preserving sampling technology; and finally, generating an image with a watermark through a denoising process of the diffusion model. When the watermark is extracted, reverse diffusion processing is carried out on an image which is possibly damaged to recover an approximate value of a potential space variable, a code word which is possibly damaged is extracted from the approximate value, and original watermark information is recovered by utilizing the error correction capability of a Reed-Solomon decoder. On the premise of keeping the generation performance, the robustness of the watermark to compression, noise, cutting and other potential tampering attacks is enhanced.

The invention belongs to the technical field of spaceflight electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system capable of resisting single event upset, in particular to a bit-symbol double-layer error correction method of RS decoding operator error correction based on finite field algebra cascading on the basis of two-out-of-three majority voting logic. Single-particle independent upset and multi-copy common-mode failure can be corrected at the same time, and the problem of traditional TMR error locking is solved. Meanwhile, when configuration data are written into a nonvolatile memory, a cross-sector space staggered and dispersed storage mechanism is introduced, symbols in the same RS code word are separated as far as possible in physical positions, and therefore aggregated physical damage is converted into dispersed symbol-level errors.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G and 6G. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality XR service or another low-delay service.

Systems and methods for error detection in quantum computing systems are provided. In one example, the method includes obtaining a multi-dimensional quantum error detection map. The multi-dimensional quantum error detection map represents one or more quantum error detection measurements over a period of time. The method includes determining a partitioning scheme and a fusion scheme for the multi-dimensional quantum error detection map based at least in part on the decoding delay and the fusion delay. The method includes partitioning the multi-dimensional quantum error detection map into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection map based at least in part on the fusion scheme. The method includes operating a quantum computing system based at least in part on the decoded detection map.

This invention discloses an image-based scale recognition method, comprising the following steps: 1) Designing scale lines for computer recognition: 1.1) Setting patterns at the left and right ends of the scale lines to distinguish the left and right boundaries; 1.2) Encoding the middle scale value of the scale lines; 2) Attaching the scale lines to the side wall of the liquid container being measured; 3) Acquiring scale line images: Using a camera to capture images of the scale lines at the side wall of the liquid container; 4) Sending the acquired scale line images to an algorithm recognizer: 4.1) Detecting and locating the scale area through the left and right boundaries of the image; if there is inversion or tilt, correcting the scale area; 4.2) Recognizing the scale lines and converting the scale line encoding into a bit sequence; 4.3) Performing error detection and correction; 5) Outputting the scale value. This invention provides a novel scale encoding pattern that facilitates computer recognition and achieves high accuracy.

Systems, apparatuses and methods provide technology that identifies a codeword associated with a fluid cooling system and a network system, generates a status update with the network system, embeds the codeword as a repeating cyclic codeword in a message containing the status update, transmits the message from the network system to the fluid cooling system over a data link, receives the message at the fluid cooling system, and determines, with the fluid cooling system, whether interference is inserted into the message based on the repeating cyclic codeword in the message.

The present invention teaches a method of pairing two user worn devices including collecting first and second biometric activity from respective first and second user worn devices to create first and second biometric signals, processing the first and second biometric signals to create first and second keys and determining if the keys match to allow for pairing of the two user worn devices. The first and second biometric activity may be the same or different biometric activities. The processing of the biometric signals is adjusted based upon the types of biometric activities being sensed.

Coded stream processing is provided. A system and method for encoding streaming data to facilitate recovery from faulty or slow processor (s) is described herein. A batch of processing stream data may be partitioned into a plurality of data blocks. The parity block (s) are used for a plurality of data blocks. The plurality of data blocks and parity block (s) may be provided to a processor for processing. Processed data of at least some (e.g., one or more) data blocks of the plurality of data blocks and processed data of parity block (s) are received. When it is determined that processed data for a predefined number of data blocks has not been received within a predefined time period, the parity block (s) is received based at least in part on the received processed parity block (s) and the received processed data block (s). The processed data is determined for the particular data block (s) of the particular processor (s) from which the processed data is not received.

A system includes a memory controller, multiple memories coupled to the memory controller, and multiple controlling components coupled to the memory controller. The memory controller calculates an error correction code (ECC) syndrome of a first type for a segment of data; stores the segment of data and the ECC syndrome of the first type in a first memory of the multiple memories; receives a request from a controlling component of the multiple controlling components directed to the segment of data, the controlling component implementing an ECC syndrome of a second type; transforms the ECC syndrome of the first type for the segment of data to the ECC syndrome of the second type; detects a number of errors, if any, present in the segment of data; and takes further action depending on how many errors are detected.

Systems and methods for fast multi-length payload error correcting includes at least a decoder circuit. The decoder circuit receives a first input and receives a second input. The decoder circuit generates, based on the first input, a first decoded payload. The first decoded payload includes at least a first data or a first length and a first flip bit. The decoder circuit generates, based on the second input, a second decoded payload. The second decoded payload includes at least a second data of a second length and a second flip bit, the second length being different from the first length.

This disclosure describes techniques that include implementing network-efficient data durability or data reliability coding on a network. In one example, this disclosure describes a method that includes generating a plurality of data fragments from data to enable reconstruction of the data from a subset of the plurality of data fragments; storing, across a plurality of nodes in a network, the plurality of data fragments, wherein storing the plurality of data fragments includes storing the first fragment at a first node and the second fragment at a second node; and generating, by the first node, a plurality of secondary fragments derived from the first fragment to enable reconstruction of the first fragment from a subset of the plurality of secondary fragments; and storing the plurality of secondary fragments from the first fragment across a plurality of storage devices included within the first node.

The application provides a decoding method, an encoding method, a device, a chip and a computing device. The method comprises the following steps: a decoding device acquires a first matrix, and then decodes a first code word vector according to the first matrix to obtain a decoding result. The first matrix is a 0-1 matrix representing elements in a second matrix on a polynomial ring. The second matrix is a check matrix on a finite field 2q, and the number of rows is r and the number of columns is n. A first polynomial corresponding to the polynomial ring is a q-th irreducible polynomial on a binary field. The number of 1s in the first matrix is less than the number of 1s in the 0-1 matrix representation of the second matrix. The first code word vector comprises k information code elements and r check code elements, and n=k+r. Each code element comprises q data units, and each data unit comprises at least one bit. The scheme can effectively reduce the hardware implementation complexity and cost of RS encoding and decoding.

A hard-decision (HD) forward error correcting (FEC) coded signal is decoded by a soft-aided decoder (112) to produce decoded bits (118) using marked reliable bits of the HD-FEC coded signal and marked unreliable bits of the HD-FEC coded signal (soft-aided bit marking) that are computed by calculation (114) and marking blocks (116) based on an absolute value of log-likelihood ratios (LLRs) of the HD-FEC coded signal. The hard-decision (HD) forward error correcting (FEC) coded signal may be, for example, a staircase code (SCC) coded signal or a product code (PC) coded signal.

The application discloses a finite field error correction encoding and decoding method and system for an integrated storage and calculation system, which is suitable for error correction tasks after sum and accumulation in analog in-memory calculation and error correction tasks of reading data from a general memory. The application uses non-binary q-order finite field operation to process input code words, uses a preprocessed generating matrix to obtain an encoding result belonging to the finite field and generate an error correction code, and restores at an output end, so that the error rate of in-memory calculation results is reduced and the reliability is improved. Based on the encoding and decoding method, the application discloses a corresponding decoding circuit system design, which is divided into a check node and a variable node, the connection between the check node and the variable node is defined by a check matrix, and belief propagation based on a finite field is adopted. After multiple iterations of belief propagation between the check node and the variable node, the error correction result converges and the final decoding result is obtained.

An encoding method includes: obtaining m lanes of first data streams through m input lanes, where m is a positive integer; processing the m lanes of first data streams to obtain z lanes of second data streams, where z is a positive integer; separately performing encoding processing on each of the z lanes of second data streams to obtain z lanes of third data streams; and performing multiplex processing on the z lanes of third data streams to obtain n lanes of fourth data streams, where n is a positive integer.

A project success rate intelligent prediction method and device, comprising: acquiring multi-source data, and constructing a structured knowledge base containing project success cases and their characteristics; applying the merged tree representation technology and the extended transformation to the project data in the structured knowledge base to construct a data structure, realize feature extraction and substructure search; based on the project feature set, multi-dimensional feature analysis is carried out from the time dimension and the space dimension; based on the multi-dimensional feature vector, a project-platform allocation model with group fairness is constructed; for the allocation model, a polynomial time approximation algorithm based on linear programming and network flow is designed to solve the optimal allocation scheme; according to the optimal allocation scheme and the historical project success data, the improved Reed-Solomon code technology is used for feature coding to construct a project success rate prediction model; based on the prediction model, the success rate of the project to be evaluated is evaluated and the support intensity trend is predicted. The present application improves the accuracy and efficiency of project success rate prediction.

An apparatus (e.g., a transmitter) may transmit a message and one or more retransmissions of the message in a wireless communication network. The message may include a codeword that includes information bits and error correction bits (e.g., parity bits). The one or more retransmissions may include error correction bits associated with the information bits. To improve the decoding performance at a receiver, the transmitter may apply probabilistic shaping to the one or more retransmissions. In some aspects, the apparatus transmits a first message including information bits and a first set of error correction bits associated with the information bits. The apparatus transmits at least a second message associated with the first message, wherein the second message includes a second set of error correction bits associated with the information bits and a set of probabilistic shaping bits for the second set of error correction bits.

Systems and methods for error location and error correction includes receiving, at a processor circuit, an input. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines a number of errors present in the input. Responsive to determining the number of errors present in the input, the processor circuit corrects the number of errors.

The invention relates to the technical field of channel coding and decoding. The invention discloses a parity check polarization code construction method and device, a terminal and a storage medium. The parity check polarization code with error detection capability can be generated. The construction method of the parity check polarization code comprises the following steps: acquiring a polarization code constraint matrix; constructing an information set based on the polarization code constraint matrix, constructing a constraint set based on the polarization code constraint matrix, constructing a frozen set based on the constraint set, and constructing a verification set based on the constraint set; constructing a parity check polarization code based on the information set, the frozen set and the check set; in the decoding process of the parity check polar code, parity check bits in the check set are used as information bits, and check is carried out according to a linear constraint relationship between the parity check bits and the information bits in the information set after decoding, so that effective code words are obtained.

The application belongs to the technical field of aerospace electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system resisting single event upsets, a double-layer error correction method of "bit-symbol" based on RS decoding operator error correction of a finite field algebra on the basis of a "two out of three" majority voting logic, which can correct single particle independent upsets and multiple copy common mode failures at the same time, and solve the traditional TMR error locking problem. Meanwhile, when configuration data is written into a non-volatile memory, a cross-sector spatial staggered dispersion storage mechanism is introduced, so that the symbols in the same RS code word are separated as much as possible in the physical position, so as to convert the aggregation physical damage into dispersed symbol level errors.

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding and an apparatus performing the method are provided. The method includes receiving a code word x, wherein the received code word x has t = t + r errors for some r ≥ 1; calculating a minimal monomial basis of an affine space V = {λ(x) ∈ F[x]: λ(x) · S(x) = λ'(x) (mod x 2t ), λ(0) = 1, deg(λ(x) ≤ t + r} where λ(x) is an error locator polynomial and S(x) is a syndrome; calculating a matrix A ≡ (λ j (β i )) i∈[w],j∈[r+1] , where W = {β1,..., β w} is a set of weak bits in x; constructing an r + 1 row submatrix from r + 1 rows of a subset of A such that the last column is a linear combination of the other columns; forming a candidate error locator polynomial using coefficients of the minimal monomial basis resulting from the constructed submatrix; performing a fast Chien search to verify the candidate error locator polynomial; flipping channel hard decisions at error locations found in the candidate error locator polynomial.

A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter (S502), receiving an UNBOND set by a receiver (S504), waking up a second transmitter by a LASM when the receiver receives the UNBOND set (S506), transmitting a training sequence by the second transmitter (S508), transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence (S510), determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block (S512), stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block (S514), and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter (S516).

This document describes a system and method for encoding streaming data to facilitate recovery from a faulty or slow processor(s). A batch of processing streaming data can be divided into multiple data blocks. Multiple parity blocks are used for the multiple data blocks. The multiple data blocks and the multiple parity blocks(s) can be provided to a processor for processing. Processed data of at least some (e.g., one or more) of the multiple data blocks and processed data of the multiple parity blocks(s) are received. When it is determined that processed data for a predefined number of data blocks has not been received within a predefined time period, processed data for specific data blocks(s) from which processed data has not been received is determined, at least in part, based on the received processed parity blocks(s) and the received processed data blocks(s).

Methods and systems are described for receiving an input vector comprising a plurality of symbols, the plurality of symbols comprising redundancy symbols generated using a check matrix of a multi-error correction code (ECC) having an error capacity of t, wherein t is an integer greater than 1, generating a set of syndromes by applying the check matrix of a multi-error correction code (ECC) to the received input vector, generating an updated vector by correcting at least one symbol of the received input vector using the first subset of the set of syndromes, wherein a number of corrected symbols is less than t, updating a plurality of higher-order syndromes of the set of syndromes based on the updated vector and the check matrix, and detecting at least one unresolved error remains in the updated vector by determining one or more of the updated higher-order syndromes are non-zero.

This application provides a method and system for repairing temporary check blocks based on erasure coding in distributed block storage. The method includes: when the distributed block storage system detects a check block write failure, a metadata service creates a temporary check block according to the erasure coding pattern; the temporary check block records operation logs and performs data writing, replaying the IO operation according to the data version number; the operation logs of the temporary check block are used to repair data block inconsistencies; and the check block data is quickly restored using the data bitmap of the temporary check block. This method, through its rapid recovery processing of temporary check blocks, can directly restore check block data without encoding, reducing internal IO and accelerating the recovery speed of erasure-coded check blocks.