458results about "Cyclic codes" patented technology

The invention provides a multi-feature information hidden document integrity verification and tampering positioning method, and relates to the field of network security and digital document protection. The multi-feature information hidden document integrity verification and tampering positioning method comprises the following steps: S1, document multi-dimensional feature extraction and encryption: based on an original Word document, adopting an SHA-3 algorithm to calculate a full-text hash value as a content feature, and extracting document object model features such as paragraph hierarchy, table structure and the like through a DOM tree analyzer; after the two types of features are combined into a feature matrix, a dynamic secret key is generated through Logistic chaotic mapping for XOR encryption, and an encrypted document feature matrix is generated. A dynamic key is generated by combining Logistic chaotic mapping encryption through a multi-dimensional extraction technology fusing document content hash values and structural features, so that the anti-cracking capability of a feature matrix is remarkably improved, the confidentiality of document features in open network transmission is ensured, the block information retention rate is simulated and predicted by adopting Monte Carlo, and the watermark embedding weight is dynamically allocated.

The present invention belongs to the technical field of BCH code decoding, and specifically relates to an error correction decoding method based on BCH codes. The steps include constructing a neural network model suitable for UDE detection. If the output result is approval, decoding ends; otherwise, it is determined to be an undetectable decoding error (UDE), triggering an ordered statistical decoder (OSD) for further decoding; constructing a DIA correction model to improve the bit reliability metric of the received sequence before OSD decoding; using the ALMLT algorithm to obtain the order of test error patterns as the initial value of the OSD decoding path, and then obtaining the frequency distribution characteristics of the actual error pattern or estimated error pattern corresponding to the decoded codeword, continuously fine-tuning the order of the test error patterns, obtaining an optimized decoding path, and performing OSD decoding on the BCH code. The present invention significantly improves the reliability and efficiency of BCH codes in NMS decoding, while reducing computational complexity and latency.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G systems and 6G systems. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality (XR) service or a low-delay service.

The invention provides an anti-counterfeiting traceability system and method based on a Braille dot matrix code, and the method comprises the steps: associating the multi-dimensional information of a whole life cycle of a product with the Braille dot matrix code through constructing a Braille dot matrix code generation rule of a fusion encryption algorithm and an error correction mechanism; storing the associated braille dot matrix code and product information to a block chain node to form a non-tampering traceability data chain; during verification, braille dot matrix codes are analyzed through visual scanning or tactile recognition, product information is extracted and subjected to consistency verification with hash values stored in the block chain, and tactile feedback interaction is provided for visually impaired users; and finally, anti-counterfeiting verification and full-process traceability of the product are realized, the use requirements of common users and visually impaired users are considered, and the problems that the existing anti-counterfeiting technology is easy to copy, the traceability data are unreliable and the traceability data are not friendly to visually impaired groups are solved.

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

An apparatus may receive T copies of data that includes a cyclic redundancy check (CRC). T is an even number greater than or equal to 4. The apparatus may determine a first set of bit positions, at each of which T / 2 copies of the data have a same first bit value different from a same second bit value of the other T / 2 copies of the data, determine a second set of bit positions, at each of which more than T / 2 copies of the data have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the first set of bit positions and the second set of bit positions, an error contained in the first copy.

An apparatus may receive a first copy, a second copy and a third copy of data including a cyclic redundancy check (CRC) code, determine that a number of one or more bit positions, at each of which at least two of the first copy, the second copy or the third copy have bit values different from each other, is greater than a threshold value, divide the one or more bit positions into a first set of bit positions corresponding to the threshold value and remaining bit positions, determine, among the remaining bit positions, a second set of bit positions at each of which both the second copy and the third copy have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the second set of bit positions, an error in the first copy.

In an alignment marker search method, a first module receives a first data stream, where the first data stream is obtained by multiplexing a plurality of second data streams at a reference granularity, any second data stream includes an AM and data from at least one FEC codeword, and the reference granularity is a quantity of bits corresponding to n symbols included in the FEC codeword; obtains a first data segment from a first location in the first data stream at the reference granularity; and performs AM search on the first data segment. The reference granularity is the quantity of bits corresponding to the n symbols. Therefore, when a burst bit error occurs in the first data stream, a quantity of symbols affected by the burst bit error is small.

The invention relates to a robust watermarking method of a diffusion model based on an error correction code, which belongs to the technical field of large model watermarking, and comprises the following steps of: encoding a watermark message by using a Reed-Solomon error correction code to generate a code word containing redundancy check information; carrying out randomization processing on the code word to generate a pseudo-random bit stream; embedding the pseudo-random bit stream into a variable of an initial Gaussian potential space of a diffusion model by adopting a distribution preserving sampling technology; and finally, generating an image with a watermark through a denoising process of the diffusion model. When the watermark is extracted, reverse diffusion processing is carried out on an image which is possibly damaged to recover an approximate value of a potential space variable, a code word which is possibly damaged is extracted from the approximate value, and original watermark information is recovered by utilizing the error correction capability of a Reed-Solomon decoder. On the premise of keeping the generation performance, the robustness of the watermark to compression, noise, cutting and other potential tampering attacks is enhanced.

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

The present invention discloses an error correction method and system for FPGA, which relates to the technical field of data encoding and decoding, and includes: generating Galois field elements based on the received symbol vector and the primitive polynomial, and calculating the syndrome polynomial through 8-symbol parallel processing; calculating the coefficients of the error location polynomial through the BM iterative algorithm based on the syndrome polynomial; calculating the error location by parallel substituting 10 Galois field elements through the Chien search method based on the error location polynomial; establishing the evaluation polynomial and the error pattern calculation formula, and performing polynomial division calculation through the derivative of the error location polynomial to obtain the error pattern; performing error code judgment based on the error location and the error pattern, and correcting the error symbol through the XOR operation in the Galois field to obtain the updated symbol vector. The present application adopts a parallel pipeline design structure, which enables the FPGA to automatically and real-time correct the received error module data without retransmission, effectively improving the real-time performance and reliability of error correction.

The invention belongs to the technical field of spaceflight electronic integrated circuits, and particularly relates to a satellite load FPGA configuration data error correction method and system capable of resisting single event upset, in particular to a bit-symbol double-layer error correction method of RS decoding operator error correction based on finite field algebra cascading on the basis of two-out-of-three majority voting logic. Single-particle independent upset and multi-copy common-mode failure can be corrected at the same time, and the problem of traditional TMR error locking is solved. Meanwhile, when configuration data are written into a nonvolatile memory, a cross-sector space staggered and dispersed storage mechanism is introduced, symbols in the same RS code word are separated as far as possible in physical positions, and therefore aggregated physical damage is converted into dispersed symbol-level errors.

The invention provides a temporary check block repairing method and system based on erasure codes in distributed block storage, and the method comprises the steps that a distributed block storage system detects that a check block fails to be written in, and a metadata service creates a temporary check block according to an erasure code mode; the temporary check block records an operation log and executes data writing, and replays IO operation according to a data version number; repairing the inconsistency of the data blocks by using the operation log of the temporary check block; and quickly recovering the check block data through the data bitmap of the temporary check block. According to the rapid recovery processing method for the temporary check block, the check block data can be directly recovered without a coding mode, the internal IO is reduced, and the recovery speed of the erasure code check block is increased.

The invention belongs to the technical field of BCH code decoding, and particularly relates to an error correction decoding method based on a BCH code, which comprises the following steps: constructing a neural network model suitable for UDE detection, if an output result is approved, ending decoding, otherwise, judging that decoding error UDE cannot be detected, and triggering an ordered statistical decoder OSD for further decoding; constructing a DIA correction model, and improving the bit reliability measurement of a received sequence before OSD decoding; an ALMLT algorithm is utilized to obtain a sequence of test error modes, the sequence is used as an initial value of a decoding path of the OSD, then frequency distribution characteristics of a real error mode or an estimated error mode corresponding to a decoding code word are obtained, the sequence of the test error modes is continuously finely adjusted, an optimized decoding path is obtained, and OSD decoding is carried out on a BCH code. According to the method, the reliability and the efficiency of the BCH code in NMS decoding are remarkably improved, and meanwhile, the calculation complexity and the time delay are reduced.

The invention discloses a decoding method, a decoding device, a chip and a storage medium. The decoding method comprises the steps that according to a receiving vector, a corresponding first generalized syndrome is constructed, the receiving vector is a result obtained after a code word is subjected to error interference, and the first generalized syndrome comprises the receiving vector, a first polynomial and parameters of a check matrix corresponding to a code; obtaining an incidence relation between the receiving vector and the first generalized syndrome; calculating a first generalized syndrome based on the association relationship to obtain a calculation result of the first generalized syndrome; based on the calculation result of the first generalized syndrome, error information in the receiving vector is solved, and an error position and an error value are obtained; and correcting the receiving vector based on the error position and the error value and obtaining a code word. According to the decoding method, the complexity of calculating the generalized syndromes can be reduced, and unified decoding of various types of codes is realized.

Receiving a codeword of a forward error correction (FEC) code, each codeword in the FEC code having a minimum distance of at least seven to any other codeword in the FEC code, calculating multi-bit syndromes by applying columns of a check matrix to the received codeword using combinatorial logic, and responsively determining the received codeword comprises at least three errors, determining coefficients of an error locator polynomial using a coefficient combinatorial logic circuit by combining the multi-bit syndromes using non-iterative combinatorial logic performing arithmetic operations in a finite field F(2 n ), determining respective error positions for each error of the at least three errors by determining roots of the error locator polynomial using a non-iterative root-finding combinatorial logic circuit, the non-iterative root-finding combinatorial logic circuit performing arithmetic operations in the finite field F(2 n ), and correcting each of the at least three errors in the received codeword.

An apparatus may include one or more processors and a receiver configured to receive first audio data having one or more gain spikes and retransmission of a first copy of the first audio data. The one or more processors may determine a first set of bit positions each having a sensitivity value higher than a threshold value, the sensitivity value indicating a degree of sensitivity of audio quality to bit errors at each bit position, determine that a second set of bit positions, at each of which the first audio data and the first copy have bit values different from each other, include at least one of the first set of bit positions, and modify the first audio data to eliminate a gain spike corresponding to the at least one of the first set of bit positions.

A method may include generating a state signal indicating a state of error location polynomial (ELP) determination by an ELP determination circuit; and control the ELP determination by the ELP determination circuit in response, at least in part, to a value of the status signal.

A method and apparatus for decoding syndromes of a quantum error correction code is disclosed. The method includes the steps of receiving syndrome data for a plurality of quantum error correction rounds performed on a plurality of qubits; identifying a plurality of first blocks within the syndrome data, wherein each first block has a respective first central block surrounded by one or more respective first buffer blocks; decoding each first block to obtain a first committed correction for each respective first central block; identifying a plurality of second blocks within the syndrome data, wherein each second block comprises at least part of at least one first buffer block; and decoding each second block to obtain a second committed correction for each second block. An apparatus including a plurality of block decoders and a process manager is disclosed.

A data processing method and apparatus are disclosed, which may be applied to communication systems such as 5G and 6G. The method includes: obtaining an extended first codebook based on a second codebook by increasing a quantity of codewords or lengths of codewords, and performing first network coding or decoding based on the first codebook. Linear independence between codewords in the extended first codebook may be ensured as much as possible, so as to generate more valid redundant packets or check packets, thereby improving system reliability. Alternatively, flexible block lengths are supported, so as to perform efficient network coding or decoding on more original data packets, thereby improving system spectral efficiency. This application may be applied to an extended reality XR service or another low-delay service.

Systems and methods for error detection in quantum computing systems are provided. In one example, the method includes obtaining a multi-dimensional quantum error detection map. The multi-dimensional quantum error detection map represents one or more quantum error detection measurements over a period of time. The method includes determining a partitioning scheme and a fusion scheme for the multi-dimensional quantum error detection map based at least in part on the decoding delay and the fusion delay. The method includes partitioning the multi-dimensional quantum error detection map into a plurality of blocks based at least in part on the partitioning scheme. The method includes decoding each of the plurality of blocks. The method includes fusing the plurality of blocks into a decoded detection map based at least in part on the fusion scheme. The method includes operating a quantum computing system based at least in part on the decoded detection map.

This invention discloses an image-based scale recognition method, comprising the following steps: 1) Designing scale lines for computer recognition: 1.1) Setting patterns at the left and right ends of the scale lines to distinguish the left and right boundaries; 1.2) Encoding the middle scale value of the scale lines; 2) Attaching the scale lines to the side wall of the liquid container being measured; 3) Acquiring scale line images: Using a camera to capture images of the scale lines at the side wall of the liquid container; 4) Sending the acquired scale line images to an algorithm recognizer: 4.1) Detecting and locating the scale area through the left and right boundaries of the image; if there is inversion or tilt, correcting the scale area; 4.2) Recognizing the scale lines and converting the scale line encoding into a bit sequence; 4.3) Performing error detection and correction; 5) Outputting the scale value. This invention provides a novel scale encoding pattern that facilitates computer recognition and achieves high accuracy.

The present invention discloses a two-stage decoding method for algebraic codes, comprising: S1, performing hard decision based on a received sequence to obtain a hard decision sequence; S2, generating one or more test error pattern sequences based on the received sequence; S3, performing bitwise exclusive-OR on each error pattern sequence and the hard decision sequence to obtain a second-stage decoding input sequence; S4, determining whether second-stage algebraic code decoding is required for each second-stage decoding input sequence, and performing S5 for all input sequences requiring algebraic code decoding; S5, performing algebraic code decoding, returning a decoding status and a decoding result; and S6, selecting the optimal decoding result from the decoding output as the decoding output. The present invention can achieve performance close to the finite code length bound based on hard decision decoding when the list is small, achieving low-complexity and high-performance decoding. Furthermore, a specially introduced judgment skipping mechanism can significantly reduce the number of times the algebraic code decoder is called in the second stage, thereby significantly reducing decoding power consumption.

A transmitter includes: an input configured to receive, via an electrical interface, encoded data from a host device, the encoded data being encoded at the host device according to a first code; processing circuitry configured to process the encoded data to provide processed data; an encoder configured to encode the processed data according to a second code that is different than the first code, where encoding the processed data includes concatenating one or more parity bits to the processed data to provide forward error correction (FEC) blocks of data; and transmit circuitry to transmit the FEC data over an optical medium.

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Systems, apparatuses and methods provide technology that identifies a codeword associated with a fluid cooling system and a network system, generates a status update with the network system, embeds the codeword as a repeating cyclic codeword in a message containing the status update, transmits the message from the network system to the fluid cooling system over a data link, receives the message at the fluid cooling system, and determines, with the fluid cooling system, whether interference is inserted into the message based on the repeating cyclic codeword in the message.

The present invention teaches a method of pairing two user worn devices including collecting first and second biometric activity from respective first and second user worn devices to create first and second biometric signals, processing the first and second biometric signals to create first and second keys and determining if the keys match to allow for pairing of the two user worn devices. The first and second biometric activity may be the same or different biometric activities. The processing of the biometric signals is adjusted based upon the types of biometric activities being sensed.

Coded stream processing is provided. A system and method for encoding streaming data to facilitate recovery from faulty or slow processor (s) is described herein. A batch of processing stream data may be partitioned into a plurality of data blocks. The parity block (s) are used for a plurality of data blocks. The plurality of data blocks and parity block (s) may be provided to a processor for processing. Processed data of at least some (e.g., one or more) data blocks of the plurality of data blocks and processed data of parity block (s) are received. When it is determined that processed data for a predefined number of data blocks has not been received within a predefined time period, the parity block (s) is received based at least in part on the received processed parity block (s) and the received processed data block (s). The processed data is determined for the particular data block (s) of the particular processor (s) from which the processed data is not received.