7 results about "Chien search" patented technology

According to the RS error correction decoding method and system compatible with the multiple two-dimensional codes, a finite field and module value corresponding table is defined, a corresponding relation table between power and data is constructed, and the decoding requirements of the multiple two-dimensional code types are met. The method comprises the following steps: acquiring image data by using an image sensor, extracting two-dimensional code data, and converting the two-dimensional code data into a data code word stream; and performing error detection and correction on the two-dimensional code data based on a preset power data corresponding table, including judging whether an error exists or not by calculating a syndrome, if an error is detected, calculating an error position polynomial by using a Berlekamp-Massey algorithm, then positioning an error position by using a Chien search algorithm, and finally calculating an error value by using a Forne algorithm and performing correction. According to the method, the decoding efficiency and the fault-tolerant capability of the two-dimensional code are remarkably improved, the method is suitable for various standards, and especially when the two-dimensional code is partially damaged or an error occurs in data transmission, the original coding information can be effectively recovered.

The present invention relates to communication system and method for error-proportional energy-saving in encoding and decoding in Body Area Networks (BAN) using Human Body Communication (HBC). The method includes receiving message signal from data sources. Further, the method includes encoding data symbols using encoding algorithms. Furthermore, the method includes calculating syndrome values for the encoded data symbols. Furthermore, the method includes generating an error signal when the calculated syndrome values corresponds to a non-zero value. Furthermore, the method includes receiving the error signal from the syndrome module. Furthermore, the method includes activating an Error Location Polynomial (ELP) module when the syndrome values corresponds to a non-zero value. Subsequently, the method includes generating an error indication signal. Consequently, the method includes activating an Error Magnitude Polynomial (EMP) solver module and a chien search module. Finally, the method includes decoding the encoded data symbols.

The present invention discloses an error correction method and system for FPGA, which relates to the technical field of data encoding and decoding, and includes: generating Galois field elements based on the received symbol vector and the primitive polynomial, and calculating the syndrome polynomial through 8-symbol parallel processing; calculating the coefficients of the error location polynomial through the BM iterative algorithm based on the syndrome polynomial; calculating the error location by parallel substituting 10 Galois field elements through the Chien search method based on the error location polynomial; establishing the evaluation polynomial and the error pattern calculation formula, and performing polynomial division calculation through the derivative of the error location polynomial to obtain the error pattern; performing error code judgment based on the error location and the error pattern, and correcting the error symbol through the XOR operation in the Galois field to obtain the updated symbol vector. The present application adopts a parallel pipeline design structure, which enables the FPGA to automatically and real-time correct the received error module data without retransmission, effectively improving the real-time performance and reliability of error correction.

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding and an apparatus performing the method are provided. The method includes receiving a code word x, wherein the received code word x has t = t + r errors for some r ≥ 1; calculating a minimal monomial basis of an affine space V = {λ(x) ∈ F[x]: λ(x) · S(x) = λ'(x) (mod x 2t ), λ(0) = 1, deg(λ(x) ≤ t + r} where λ(x) is an error locator polynomial and S(x) is a syndrome; calculating a matrix A ≡ (λ j (β i )) i∈[w],j∈[r+1] , where W = {β1,..., β w} is a set of weak bits in x; constructing an r + 1 row submatrix from r + 1 rows of a subset of A such that the last column is a linear combination of the other columns; forming a candidate error locator polynomial using coefficients of the minimal monomial basis resulting from the constructed submatrix; performing a fast Chien search to verify the candidate error locator polynomial; flipping channel hard decisions at error locations found in the candidate error locator polynomial.

The application discloses a method for realizing an efficient general Reed-Solomon decoder on a chip, and solves the technical problems of poor generality, low decoding rate and low code reuse rate of the existing RS decoder on the chip. The method is based on the Galois field operation principle, and a five-module parallel architecture composed of an accompanying polynomial calculation, a key equation solving, a Chien search, a Forney transformation and an error calculation is constructed. The core parameters and operation logic of different RS codes are uniformly managed through a pre-defined general header file. The decoding rate is improved through parallel design, and multiple RS codes are compatible through the general header file. The code utilization rate is high, the hardware implementation complexity is low, the chip-level high-speed decoding scene is adapted, the method can be widely applied to various digital communication and storage systems requiring error control, the chip design cost and development cycle are significantly reduced, and the decoding efficiency and system reliability are improved.

A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a syndrome stage for generating a syndrome based on a BCH coded word, a Berlekamp-Massey stage for performing a Berlekamp-Massey (BM) algorithm on the syndrome to generate error location polynomial (ELP) coefficients, a Chien stage for performing a Chien search on the ELP coefficients using a fast Fourier transform (FFT) to generate error bits and iterative information, and a framer stage configured to reorder the error bits into an ordered frame based on the iterative information. The BCH decoder decodes the BCH coded word using the reordered error bits.

System and methods for RS / BCH decoding using a low-complexity Chien search architecture including methods to decompose a Vandermonde matrix for parallel Chien search in RS / BCH decoding. The Vandermonde matrix whose elements are in the order of consecutive power of the primitive element is decomposed into matrices with substantially smaller number of non-zero entries by utilizing the standard basis representation of finite field elements. In order to achieve efficient parallel design, additional reformulation is proposed for segments of the Vandermonde matrix so that the same constant multipliers can be utilized to implement the decomposed multiplications of each segment. Accordingly, a low-complexity parallel Chien search architecture is developed.