2 results about "Chien search" patented technology

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding and an apparatus performing the method are provided. The method includes receiving a code word x, wherein the received code word x has t = t + r errors for some r ≥ 1; calculating a minimal monomial basis of an affine space V = {λ(x) ∈ F[x]: λ(x) · S(x) = λ'(x) (mod x 2t ), λ(0) = 1, deg(λ(x) ≤ t + r} where λ(x) is an error locator polynomial and S(x) is a syndrome; calculating a matrix A ≡ (λ j (β i )) i∈[w],j∈[r+1] , where W = {β1,..., β w} is a set of weak bits in x; constructing an r + 1 row submatrix from r + 1 rows of a subset of A such that the last column is a linear combination of the other columns; forming a candidate error locator polynomial using coefficients of the minimal monomial basis resulting from the constructed submatrix; performing a fast Chien search to verify the candidate error locator polynomial; flipping channel hard decisions at error locations found in the candidate error locator polynomial.

The application discloses a method for realizing an efficient general Reed-Solomon decoder on a chip, and solves the technical problems of poor generality, low decoding rate and low code reuse rate of the existing RS decoder on the chip. The method is based on the Galois field operation principle, and a five-module parallel architecture composed of an accompanying polynomial calculation, a key equation solving, a Chien search, a Forney transformation and an error calculation is constructed. The core parameters and operation logic of different RS codes are uniformly managed through a pre-defined general header file. The decoding rate is improved through parallel design, and multiple RS codes are compatible through the general header file. The code utilization rate is high, the hardware implementation complexity is low, the chip-level high-speed decoding scene is adapted, the method can be widely applied to various digital communication and storage systems requiring error control, the chip design cost and development cycle are significantly reduced, and the decoding efficiency and system reliability are improved.