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BCH decoder for configuring error correcting capability according to Nand Flash extra space

An error correction capability and decoder technology, applied in the direction of data representation error detection/correction, using linear codes for error correction/detection, using block codes for error correction/detection, etc., can solve the problems of high error probability, non-configurability, Problems such as poor backward compatibility achieve good compatibility, low delay, and high hardware reuse rate

Active Publication Date: 2009-07-15
VERISILICON MICROELECTRONICS SHANGHAI +2
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AI Technical Summary

Problems solved by technology

However, due to the advancement of technology and the reduction of line width, the storage density of Nand Flash is getting higher and higher, and the error probability is also increasing. Therefore, the redundant space in the new generation of Nand Flash has been increased to 218 bytes / 4K bytes, which is also This enables the Nand Flash controller to use the BCH code that corrects more bit errors to reduce the error rate of Nand Flash, and it is far from enough to correct 4-bit or 8-bit errors.
On the other hand, the existing decoder that can correct errors below 15 bits, due to its non-configurability, makes the check bit length fixed and greater than 16 bytes, which can only be used for the new generation of MLC / QLC Nand Flash, and cannot be applied Compared with ordinary Nand Flash, its backward compatibility is not good

Method used

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  • BCH decoder for configuring error correcting capability according to Nand Flash extra space
  • BCH decoder for configuring error correcting capability according to Nand Flash extra space
  • BCH decoder for configuring error correcting capability according to Nand Flash extra space

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Embodiment Construction

[0056] see figure 1 , the BCH decoder that configures the error correction capability according to the Nand Flash redundant space of the present invention at least includes: an error correction capability indication module, an odd syndrome calculation module, an even syndrome calculation module, a solution to Newton's identity module, and a chien search module, which The (4200, 4096) shortened code or (4291, 4096) shortened code can be decoded.

[0057] The error correction capability indication module is used to configure the number of error correction bits of the decoder according to the excess space of the Nand Flash, and the configurable number of error correction bits is usually 8 bits or 15 bits.

[0058] The odd-numbered syndrome calculation module is used to calculate the corresponding odd-numbered syndrome in parallel by using an iterative method according to the number of error-correcting bits configured by the error-correcting capability indicating module and the in...

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Abstract

A BCH decoder which configures error correcting capability according to the spare space of Nand Flash comprises the following components: an error correcting capability indicating module which is used for collocating the error correcting bit number of decoder according to the spare space of Nand Flash; an odd syndrome calculating module which adopts an iterative method for parallel calculating the syndrome of corresponding odd number according to the configured error correcting bit number and the input code word; an even syndrome calculating module which is used for serially calculating the syndrome of oven number according to the calculated syndrome of odd number; a Newton's identity solving module which is used for iteratively solving each coefficient and error code word number of error position equation with the non-inverse simplified BMA algorithm according to the calculated syndrome of odd number and even number; and a chien searching module which is used for searching out the position of error bit according to each solved coefficient and the number of error code for further realizing decoding. The BCH decoder of the invention has the advantages of small decoding delay, excellent compatibility and high multiplexing rate of hardware.

Description

technical field [0001] The invention relates to a BCH decoder, in particular to a BCH decoder configured with error correction capability according to the redundant space of Nand Flash. Background technique [0002] GF(2 m ) is a Galois field, which is an extension field of the GF(2) field, which is generated by a primitive polynomial p(x) of degree m with coefficients on the GF(2) field, and has a primitive element in the field α, which is the root of the primitive polynomial. GF(2 m ) domains have the following basic properties: [0003] 1. There are 2 in the domain m elements, except for the 0 element, the other elements are all powers of α. [0004] 2. The sum of two elements in the field is still an element in the field, and is equal to the XOR of the components represented by the two element vectors. [0005] 3. Set β 1 = α i and beta 2 = α j are two elements in the field respectively, then β 1 ×β 2 is still an element in the field whose value is α (i+j)%n...

Claims

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Application Information

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IPC IPC(8): H03M13/15
Inventor 诸烜程周华姜启军
Owner VERISILICON MICROELECTRONICS SHANGHAI
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