269 results about "Bit numbering" patented technology

The invention discloses a fusion multiply-add operation circuit compatible with multiple floating-point number formats, and the circuit comprises an input device which is used for obtaining three floating-point numbers and control information in a fusion multiply-add operation instruction; the input decoding device is used for analyzing the control information and extracting the symbol, the index and the mantissa of each floating-point number; the multiplication correlation device is used for calculating an initial index, a mantissa product and an initial symbol; the addend aligning and shifting device is used for completing addend mantissa aligning and shifting; the additive operation correlation device is used for calculating an addition result, a symbol, a normalized shift bit number and a direction flag bit according to the mantissa product sum; the original result processing device is used for generating an initial rounding bit, a normalized shift pasting bit and intermediate result data; and the final result output device is used for outputting a final operation result compatible with the IEEE-754 or Point floating-point number according to the rounding information. The circuit area and power consumption are remarkably reduced through hardware integration, and meanwhile the calculation efficiency is improved.

The embodiment of the invention provides a color setting method, a graphic processing unit and a system on chip. The method applied to GPU user mode driving comprises the steps that under the condition that a rendering preparation instruction is received, a first bit field of a sampling descriptor is set as a first identifier, the first identifier is used for pointing to a preset table located in a memory, and the table is used for storing boundary colors with the color format exceeding the bit number of the sampling descriptor; writing a target color carried in the rendering preparation instruction into the preset table; acquiring a second identifier of the target color in the preset table; and writing a second identifier of the target color in the preset table into a second bit field of the sampling descriptor, and sending the sampling descriptor to GPU hardware, so that the GPU hardware realizes texture boundary color setting according to the sampling descriptor. According to the embodiment of the invention, the storage format and precision of the target color can be expanded, so that the setting of the texture boundary color can be improved, and the user experience is improved.

The invention discloses a fault injection and detection method based on RTL, and relates to the technical field of aerospace fault-tolerant calculation, the fault injection and detection method is compatible with three single-particle fault types of SEU, SET and SEL, the injection bit number, duration and position can be customized by a user, and based on random number file configuration, the problems of single fault type and parameter solidification of an existing tool are solved; a bypass injection mechanism controlled by a timer is adopted, and a fault data flow is switched in a specified clock period, so that a trunk data flow is not influenced, and the occupation of system resources is reduced; a forward detection module is designed based on (13, 8) extended Hamming codes, a receiving end quickly locates the fault type and position through a syndrome look-up table, original data does not need to be transmitted back, and detection delay is effectively controlled; a streamlined design is adopted, check bit generation, fault injection, syndrome generation and fault information output are executed in parallel, and hardware resource overhead is obviously optimized.

The invention discloses a magnetic flux regulation crosstalk calibration method for quantum bits, and relates to the technical field of quantum, and the method comprises the steps: S1, obtaining an initial calibration parameter of a target quantum system through employing an initial crosstalk matrix; s2, generating a plurality of groups of random magnetic flux configuration signals containing magnetic flux regulation and control values by using the initial crosstalk matrix; s3, constructing a modified crosstalk matrix by using the random magnetic flux configuration signal; and S4, acquiring a correction calibration parameter by using the correction crosstalk matrix, performing error evaluation, if the error evaluation is met, completing correction, and if the error evaluation is not met, returning to the step S2. Compared with the prior art, the method has the advantages that the frequency offset matrix is constructed, the crosstalk matrix is corrected, and the corrected crosstalk matrix is generated by using the quasi-Monte Carlo method and the frequency offset matrix, so that the high sampling complexity in direct proportion to the square of the bit number in two-dimensional spectrum scanning is avoided; the method has the advantages of improving the calibration precision and reducing the complexity of a phase measurement experiment process.

The invention relates to the technical field of automatic generation of sequence control codes, and provides a method and system for automatically generating sequence control codes of a DCS (Distributed Control System), and the method comprises the following steps: S1, formulating a standardized template rule of a sequence control scheme, the standard template rule defines a preset type of sequential control steps, and sets formats of required parameters and selectable parameters including the preset type, the equipment bit number and the bit number description of each step; s2, filling in a sequence control scheme according to the standardized template rule, determining the preset type of each step, the equipment bit number of the associated equipment and the bit number description, and supplementing control logic parameters required by the preset type of the corresponding step; and S3, analyzing the sequence control scheme through a conversion tool, and automatically converting the analyzed step information into a sequence control code which can be imported into the DCS based on a code grammar rule of the DCS. The invention aims to solve the problems of high difficulty in writing sequence control of a DCS (Distributed Control System), high time consumption and high error rate of codes.

The invention provides a hybrid precision quantification method and system based on neural network architecture search. The method comprises the following steps: dividing a whole model structure into a plurality of modules; performing a quantitative sensitivity test on the whole model and each module, and setting an initialization bit number of each module; building a search space based on the number of divided modules, a set weight and an activated quantization structure; based on the initialized bit number, under the constraint that the overall average quantization precision of the model is kept unchanged, the overall verification performance serves as an optimization target, searching is carried out in the search space, weight and activated bit width self-adaptive distribution is carried out, and an optimal quantization scheme of the mixed precision is obtained. According to the method, the model expression ability and the task performance are maximized under the limited bit budget by introducing an adaptive weight and activation bit width allocation mechanism based on NAS (Neural Network Architecture Search).

The present application relates to the technical field of video decoding. Provided in the embodiments of the present application are a video image decoding method and coding method, an apparatus, and a storage medium, which help to improving the image quality. The method comprises: acquiring channel-level complexity levels from a data stream, the data stream being a coding data stream of a current block; according to at least two channel-level complexity levels, determining the block-level complexity level of the current block, the channel-level complexity levels being used for representing the complexity degree of the channel-level texture of the current block; according to a code control parameter, determining a target bit number of the current block, the code control parameter comprising the block-level complexity level of the current block; on the basis of the target bit number, determining a quantization parameter of the current block; and on the basis of the quantization parameter, decoding the current block.

The embodiment of the invention discloses a data processing method capable of being applied to a high-speed optical transmission network. The method comprises the following steps: obtaining second bit data according to first bit data of which the number of bits is din, the second bit data comprising the bits in the din first bit data, dCRC check bits and / or dPAD filling bits; scrambling the second bit data to obtain third bit data, wherein the bit number dscr of the third bit data is equal to din + dCP, and dCP is equal to dCRC + dPAD; then probability constellation shaping PCS processing is carried out on a first bit subset in a first bit set with the bit number of m to obtain a second bit subset, and the first bit set is obtained from the third bit data; performing FEC coding and interleaving processing on the second bit subset and a third bit subset except the first bit subset in the first bit set to obtain a second bit set; according to the invention, different values of the din, the m and the dCP are given, the existing 400G network can be compatible, the performance is excellent, and the cost is low.

The application relates to a cement rotary kiln control parameter optimization method, which comprises the following steps: firstly, obtaining each target bit number data type related to the cement f-CaO content under the target cement rotary kiln working state; then, obtaining each to-be-referenced optimal control parameter vector based on a vector composed of each target bit number data type data value at each to-be-analyzed time point; then, obtaining the to-be-referenced optimal control parameter vector with the highest similarity to the current vector in each to-be-referenced optimal control parameter vector based on a current vector composed of the data values of each target bit number data type of the target cement rotary kiln under the current working state, and forming a target optimal control parameter vector; finally, adjusting each target bit number data type corresponding to the current working state of the target cement rotary kiln with the target optimal control parameter vector as the target; in this way, the working condition gradually approaches or reaches the historical best level, so that the output and quality of the clinker are effectively improved.

The invention discloses a quantum computing gate circuit expression and compression method and a medium, and relates to the technical field of quantum computing, and the method comprises the steps: setting a conversion expression character between a user side and a quantum computing cloud platform, or setting the conversion expression character between the quantum computing cloud platform and a terminal quantum computer for unifying quantum languages; the conversion expression character is divided into three segments which are an operation code, a bit code and a parameter code in sequence, the operation code refers to quantum gate operation, the bit code refers to a quantum bit number, and the parameter code refers to a floating-point number related to the operation code; the core of the method is that the file volume is compressed and the quantum language is unified, so that the problem of transmission efficiency of existing codes among different terminals is solved.

The invention discloses an HPLC (High Performance Liquid Chromatography) signal processing method based on bit loading, and belongs to the technical field of power line carrier communication. The HPLC signal processing method based on bit loading comprises the following steps: reading bit data from a channel interleaving module, and sequentially writing the bit data into a first bit buffer queue according to a preset read bit number of the channel interleaving module; in the bit loading mode, aiming at the modulation mode corresponding to each subcarrier, determining a target bit number required to be filled by each subcarrier; different modulation modes correspond to different target bit numbers; and sequentially reading the bit data of the target bit number from the first bit buffer queue according to the write-in sequence, and mapping the bit data read as required to the corresponding subcarrier for modulation and transmission. According to the invention, rate efficient matching of data processing in a bit loading mode and data transmission without subcarrier cross-physical blocks are realized.

The invention discloses a dual-mode communication chip, and belongs to the technical field of communication. The dual-mode communication chip comprises an HPLC (High Performance Liquid Chromatography) signal transmitting end and an HPLC signal receiving end; the HPLC signal transmitting end is configured as a coding module and is used for coding the load data to obtain coded load data; the first storage module is used for storing the coded load data; the channel interleaving module is used for carrying out interleaving processing on the bit data read out from the first storage module; the first bit buffer queue is used for sequentially writing the bit data from the channel interleaving module according to a first bit number and sequentially reading the bit data according to a writing sequence according to a second bit number; and the bit mapping module is used for mapping the bit data from the first bit buffer queue to each subcarrier with a second bit number. According to the invention, rate efficient matching of data processing in a high-order modulation mode and data transmission without subcarrier cross-physical blocks are realized.

The application relates to a calculation method for realizing a Tanh excitation function based on FPGA, which comprises the following steps: obtaining the quantization bit number during FPGA realization, determining the decimal bit quantization bit number, determining the accuracy of input and output values of the Tanh excitation function and the range of the output values based on the decimal bit quantization bit number, processing the values greater than 0 based on four linear fittings, one quadratic fitting and two table storage respectively, and mapping and processing the values less than 0 based on the odd symmetry of the Tanh function. The application can realize the Tanh function with high accuracy under the condition that the FPGA resource is limited.

The embodiment of the application discloses a data format conversion device and method, electronic equipment and computer storage medium, the data format conversion device comprises: a first shift module, which is used for first extended shift of a normalized format number to be converted integer, and obtains a shift integer; the bit number of the shift integer is n times of the bit number of the integer to be converted; n is a positive integer; a second shift module is used for second extended shift of a normalized format number to be converted decimal, and obtains a shift decimal; an addition module is used for adding the shift integer and the shift decimal, and obtains a shift number; a floating point conversion module is used for floating point format conversion of the shift number, and obtains a floating point format number of the shift number; the floating point format number of the shift decimal is a target floating point number.

The application provides an uplink control information transmission method, a receiving method, a terminal and a network device, and the method comprises the following steps: in the case that a first uplink channel carrying a first HARQ-ACK and a second uplink channel carrying a second HARQ-ACK overlap in the time domain, determining a reference bit number of the second HARQ-ACK according to the bit number of the first HARQ-ACK; and transmitting the second HARQ-ACK and the first HARQ-ACK simultaneously on the same uplink channel according to the reference bit number. The application can ensure that the terminal and the network device have consistent understanding of the bit number of the HARQ-ACK transmitted by the terminal.

The invention discloses a load determination method, the method is applied to a transmitting end node, and the method comprises the following steps: receiving a channel quality parameter value and a first quantization bit number reported by a receiving end node; wherein the first quantization bit number is determined by the receiving end node based on a pre-configured signal-load dictionary set; determining a target signal-load dictionary matched with the signal quality parameter value and the first quantization bit number from the pre-configured signal-load dictionary set; determining a target load corresponding to a to-be-transmitted signal based on the target signal-load dictionary; and loading the target load to a signal transmitting device of the transmitting end node, and exciting to transmit the signal to be transmitted. The invention further discloses a load determination device and system, a storage medium and a computer program product.

A method for calculating the N-bit square root B of a 2N-bit number X comprises: performing a multiplication of the bits b of the square root B. i Iterate starting from the most significant bit of the square root B and working your way down to the least significant bit. For each iteration, the method includes: positioning a 1 at bit b in the CHECK variable. i The bit b is determined based on the comparison of the number X with all previously found bits and a function of the previous comparison results. i shift all previously found bits in the CHECK variable right by 1 position; and i The determined value is added to its square position in the CHECK variable.

A circuit for encoding a C-PHY signal, a decoding circuit and a transmission device, the encoding circuit being characterized by: obtaining a C-PHY line state, forming a line state block, mapping the line state block into a binary number capable of uniquely identifying the line state block, and setting different line state blocks for an HS mode, an LP mode and an ALP mode, and binary coding mapping is carried out according to the corresponding line state block, so that the coding efficiency is improved under different conditions. Furthermore, a flag bit is set, so that the bit number of binary coding is reduced, and the coding efficiency is improved. According to the invention, the complexity of a coding circuit is reduced, the integrity of coding information is kept, and the coding and decoding efficiency and the transmission real-time performance are improved from multiple angles through a series of methods such as flag bits and line state sub-blocks.

The invention discloses a component selection analysis system and an analysis method thereof, and the system comprises a configuration module which is used for configuring component parameter attribute information according to a component library and requirements, and configuring parameter attributes corresponding to components according to different application scenes; and the display module is used for displaying the corresponding component parameter attribute information in the schematic diagram according to the configured component parameter attribute, and positioning the position number of the component and the position of the component in the schematic diagram. According to the component selection analysis system and the component selection analysis method, component parameter attributes needing to be displayed can be configured, and the positions of related components can be automatically positioned and bit numbers can be displayed according to requirements. According to different application scenes, the model selection reports in different formats can be exported through self-configuration, and the applicability is high. Therefore, the model selection time is shortened, and the design efficiency is improved.

The application provides a video decoding method, a video encoding method and a storage medium. The video decoding method comprises: decoding an additional bit number M from a code stream of a video, the additional bit number M indicating a number of additional general constraint information (GCI) bits contained in the code stream of the video, wherein the additional bits comprise flags indicating respective additional coding tools to be constrained for the video, and wherein an expected value of the additional bit number M is 0 or 6; and in response to determining that the value of the additional bit number M is equal to 0, indicating that the flags of the additional coding tools to be constrained for the video do not exist in the code stream of the video, and the value of the flags is inferred to be equal to a specific value.

The application discloses a power control method and device of an uplink control channel, so that when time-frequency resources of a first PUCCH used for carrying a first UCI and time-frequency resources of a second PUCCH used for carrying a second UCI overlap, a terminal transmits the first UCI and the second UCI through a third PUCCH by using a first power, wherein the first power is determined according to a bit number of the first UCI and / or a bit number of the second UCI, so that transmission reliability of the UCI in the scenario can be improved.

A digital power control method, comprising the following steps: (1) determining the power control coefficient bit number as PA according to the quantization level bit number OUT of the digital signal whose power needs to be adjusted; (2) calculating the power control coefficient A p , the calculation formula of the power control coefficient A p is as follows: x dB is the power value needing to be adjusted, the range of A p is (0~(2 PA-1 -1)); (3) quantizing A p into a binary number, the binary number bit number is PA, and multiplying the quantized binary number by the digital signal whose power needs to be adjusted as the last set power control coefficient, so that the power control can be realized. The present application has the characteristics of simple method and high control precision.

The invention discloses a configuration data downloading method and device. The method comprises the following steps: acquiring a current downloading list file, a historical downloading list file and a bit number assignment list file; comparing the current downloading list file with the historical downloading list file to obtain a comparison result; determining a change list file based on the comparison result; generating configuration data based on the current downloading list file, the change list list file and the bit number assignment list file; and downloading the configuration data into the controller according to the mode of the interface file. Configuration data are downloaded into the controller in an interface file mode and can be directly compatible with configuration software, modification or redesign is not needed, and therefore the flexibility and expandability of the system are improved.

The present application relates to a PPDU transmission method and apparatus, and a readable storage medium, the method comprising: an AMP device sending an AMP PPDU, the AMP PPDU comprising a synchronization field, a signaling field, and a payload, the synchronization field being generated based on a synchronization sequence, the synchronization sequence being used to indicate or correspond to at least one data rate, the signaling field being generated based on the synchronization field, and the payload being generated based on the synchronization field; the first information in the signaling field is used to indicate a data rate of the payload in conjunction with the synchronization sequence. By adopting the method and the device, the bit number of the signaling field can be saved, and the detection reliability of the synchronization sequence can be improved. The method and the device can be applied to the AMP field, such as supporting WPT, WLAN or IEEE series protocols. The method is suitable for IEEE (Institute of Electrical and Electronic Engineers) 802.11 protocols related to AMP (Amplification Management Protocol) or other protocols suitable for IEEE 802.11 series, such as 802.11 a / b / g / n / ac / ax / bee / bn protocols and the like.

The invention provides a coding method, a decoding method and a display device, and the coding method comprises the steps: obtaining a first initial data stream, carrying out the operation of the first initial data stream according to a preset logic operation relation, outputting a target coding feature value obtained through the operation, judging whether the target coding feature value meets a first preset condition or not, and if yes, carrying out the decoding. Under the condition that the target coding characteristic value meets a first preset condition, assigning the bit number of the ith bit of the first initial data stream as the bit number of the (i + 1) th bit of a first target data stream to be output, and assigning a first target bit number obtained by carrying out logical NOT operation on the bit number of the first bits of the first initial data stream as the bit number of the first bits of the first target data stream, and outputting the first target data stream, so that the coded first target data stream with nine bits can be obtained through the logical NOT operation, and the coding efficiency of the first target data stream is improved. While the bandwidth utilization rate is improved, the logic operation complexity required by coding is also reduced.

The application discloses a data synchronization method and device, a storage medium and a processor. The method comprises the following steps: obtaining subscription information sent by a client through a preset interface, wherein the preset interface is used for establishing communication between the client and a preset database, and the subscription information is used for indicating subscription of changed data in the preset database; sending the subscription information to the preset database through the preset interface, wherein in the case that the changed data appears in the preset database, bit number change information used for indicating a bit number where the changed data is located is generated; and sending the bit number change information to the client through the preset interface, wherein the client is used for synchronizing the changed data according to the bit number change information. The application solves the technical problem of difficult configuration data and real-time data synchronization.

The application provides a compression parameter analysis calculation method and system of an LZ77 compression algorithm, comprising judging whether an LZ77 code of compressed data stream adopts a flag bit method or an escape code method; for the flag bit method, using obtained flag bit B, bit number D of distance code and bit number L of length code to decompress data stream S to obtain compressed data stream Q, and determining that the bit number of distance code is L; for the escape code method, analyzing distance code with distance K and extension code; in response to K>L, generating special compressible data with distance 1-4 to inject an LZ77 compressor to obtain compressed data, and calculating distance escape code and extension code with distance 1-4. The method calculates LZ77 compression parameters according to enumeration, so as to realize data decompression, solve the problem of decompression of a black box compressor, and has great innovation and practical significance in the application of data analysis.

Systems and methods for building and utilizing a k-dimensional tree that is complete and pointer-free tree are disclosed herein. In an embodiment, the method includes determining a relative magnitude between (i) half of a high-bit number being the largest number that is a power of two less than or equal to the number of data points at respective node, and (ii) the difference between the number of data points and the high-bit number, splitting the respective node with a hyperplane that places a number of points on the left side of the hyperplane equal to (a) the high-bit number or (b) the sum of half of the high-bit number and the difference between the number of data points and the high-bit number, until each branch of the KD-CPF tree terminates at a leaf node.

Provided are a data storage device and a decoding combination selecting method. The data storage device includes a non-volatile memory and a processing circuit. The non-volatile memory includes a plurality of blocks. Each block includes a plurality of pages. A decoding combination selecting method is executed by the processing circuit to include: periodically reading a page in the non-volatile memory to update state parameters of a first block including the page in a block state table; and selecting one of a plurality of decoding combinations based on the state parameters of the first block in the block state table to decode the first block. The state parameters include a charge leakage degree value, a potential offset degree value, a first offset voltage and a second offset voltage, and a first bit number and a second bit number respectively corresponding to the first offset voltage and the second offset voltage.

The application provides a list data storage method and related equipment, belonging to the technical field of data storage. The method comprises the following steps: setting the bit number of the bitmap in each storage area as a preset number; obtaining the digital number of the list data to be stored; determining the target storage area corresponding to the list data in each storage area; when the digital number is less than or equal to the preset number, determining the target bit corresponding to the digital number on the bitmap; and setting the value of the target bit as a preset value. In the application, the digital number of the list data has a corresponding bit in the bitmap, the value of the bit is set as a preset value to represent that the list data is stored, the bit is one-eighth byte, and the storage space occupied by the list data during storage is small. The bit number of the bitmap in the storage area is set as a preset number, and the preset number is less than the maximum number of bits accommodated by the storage area, thereby further reducing the storage resources occupied by the list data during storage.