376 results about "Bit numbering" patented technology

The invention relates to a capacitor mismatch foreground calibration method suitable for an SARADC, and the method comprises the steps: S1, enabling an analog input signal, a random jitter signal and a dynamic element to be matched with each other, and jointly inputting the signals into a capacitive digital-to-analog converter; s2, comparing the output of the capacitive digital-to-analog converter with a reference point through a comparator, and storing to obtain an output digital code; s3, calculating an evaluation value of the corresponding output digital code; s4, obtaining an error between the actual output value and the reference output value estimation value; s5, iterating the capacitance weight and the random signal according to the size of the error by utilizing an LMS (Least Mean Square) algorithm; and S6, continuously changing the capacitance weight and the random signal to enable the error to be within an allowable range, and obtaining more accurate output. According to the invention, no additional analog circuit needs to be added for capacitor mismatch calibration, and parameters such as the significant bit number and the spurious-free dynamic range of the ADC are obviously improved.

The invention discloses a fusion multiply-add operation circuit compatible with multiple floating-point number formats, and the circuit comprises an input device which is used for obtaining three floating-point numbers and control information in a fusion multiply-add operation instruction; the input decoding device is used for analyzing the control information and extracting the symbol, the index and the mantissa of each floating-point number; the multiplication correlation device is used for calculating an initial index, a mantissa product and an initial symbol; the addend aligning and shifting device is used for completing addend mantissa aligning and shifting; the additive operation correlation device is used for calculating an addition result, a symbol, a normalized shift bit number and a direction flag bit according to the mantissa product sum; the original result processing device is used for generating an initial rounding bit, a normalized shift pasting bit and intermediate result data; and the final result output device is used for outputting a final operation result compatible with the IEEE-754 or Point floating-point number according to the rounding information. The circuit area and power consumption are remarkably reduced through hardware integration, and meanwhile the calculation efficiency is improved.

The embodiment of the invention discloses a floating point calculation device and method for a processor, electronic equipment and a storage medium, and the device comprises a mantissa alignment module which is used for carrying out the interception processing of a first mantissa of a first floating point number based on an interception digit to obtain a first addend, and carrying out the first addend based on a shift digit to obtain a second addend; the second mantissa of the second floating-point number is shifted to obtain a second addend, and the first addend and the second addend are two mantissas with aligned indexes; the interception bit number and the shift bit number are determined based on an index difference value between a first index of the first floating-point number and a second index of the second floating-point number; the adder is used for adding the first addend and the second addend to obtain a first mantissa sum; and the post-processing module is used for performing normalization processing and rounding processing on the first mantissa sum to obtain a target mantissa. Therefore, the selector processing process before the mantissa is shifted in the floating point addition calculation process can be reduced, the calculation path is shortened, and the calculation speed is improved.

The invention provides a data processing method, device and system, and relates to the technical field of computers. According to the data processing method, an access logic address of a user in the storage system is converted into a first physical address and a second physical address, an error correction code is read or written according to the first physical address and the second physical address, and the first physical address and the second physical address correspond to different address spaces of different storage particles in a memory. Under the condition that the storage medium fault area has aggregation characteristics and the fault areas of different storage particles are the same or similar, code words of error correction codes are written or read in different address spaces, namely different bit fault rate areas, in different storage particles, so that the code words of the error correction codes are dispersed in the address spaces of the different bit fault rate areas; the maximum error bit number of the code word of the error correction code can be reduced, the error bit number difference of accessing different address spaces is reduced, the waste of error correction code resources is reduced, and the reliability of a memory is improved while the utilization rate of the error correction code resources is improved.

The invention provides a bit number silk screen adding method and device, equipment and a medium, relates to the technical field of PCB design, and is used for solving the problem that in the prior art, bit number silk screen adding efficiency and accuracy are low. The method comprises the steps that Allegro software is started, a design file of the printed circuit board is imported, and all devices of the printed circuit board are displayed; in response to a skill program calling instruction input by a user, displaying an option box; in response to a setting operation of a user in the option box, obtaining a placement parameter; in response to a first click operation of a user on a target device in all the devices through a mouse, attaching the bit number of the target device to the mouse in a silk-screen manner; and in response to a second click operation of the user at a target position through the mouse, placing the bit number silk screen of the target device at the target position according to the placement parameters. The user can add the bit number silk screen of the device only by clicking the mouse, so that the efficiency and the accuracy are improved.

The invention relates to an equipment rotating speed monitoring-based equipment operation data full-amount storage method, which relates to the field of data processing, and comprises the following steps of: constructing a query fault-tolerant condition based on an equipment model of to-be-monitored bit number equipment, a transmission element model list and a transmission element service life list; searching a historical operation sample group meeting a query fault tolerance condition; counting a plurality of control mode starting completion rotation speed characteristic values of the historical operation sample group, setting the minimum value as a rated rotation speed upper limit value, counting a plurality of control mode stopping completion rotation speed characteristic values of the historical operation sample group, and setting the maximum value as a rated rotation speed lower limit value; when the equipment monitoring rotating speed at the first moment falls between the rated rotating speed lower limit value and the rated rotating speed upper limit value, full storage is started, otherwise, interval storage is executed according to a preset period, and the problems that key parameter changes in the equipment starting and stopping process are difficult to accurately capture, data storage efficiency is low, and important information is prone to being missed are solved. And maintenance and analysis are difficult to carry out.

The invention discloses a novel digital hybrid coding method based on a large model. The method comprises the following steps: S1, preprocessing to-be-coded data; s2, performing feature coding on the preprocessed data by adopting a diffusion model driven feature learning method; s3, performing neural network coding on the feature coding data, and dynamically adjusting the coding bit number based on a variable bit rate quantization method; s4, performing adaptive entropy coding on the neural network coding data, and performing probability density transformation based on a normalized flow entropy coding method; s5, discrete transform coding is carried out on entropy coding data, and hierarchical quantization is carried out on different frequency components by adopting a hierarchical sub-block quantization method; and S6, based on the code length distribution and entropy coding parameters of the A3C optimization transformation coding data, extracting a lightweight coding model from the diffusion model by using a knowledge distillation method, and generating final optimization coding data. Through the hybrid coding and dynamic optimization strategy, the data compression efficiency and the coding quality are remarkably improved.

The embodiment of the invention provides a color setting method, a graphic processing unit and a system on chip. The method applied to GPU user mode driving comprises the steps that under the condition that a rendering preparation instruction is received, a first bit field of a sampling descriptor is set as a first identifier, the first identifier is used for pointing to a preset table located in a memory, and the table is used for storing boundary colors with the color format exceeding the bit number of the sampling descriptor; writing a target color carried in the rendering preparation instruction into the preset table; acquiring a second identifier of the target color in the preset table; and writing a second identifier of the target color in the preset table into a second bit field of the sampling descriptor, and sending the sampling descriptor to GPU hardware, so that the GPU hardware realizes texture boundary color setting according to the sampling descriptor. According to the embodiment of the invention, the storage format and precision of the target color can be expanded, so that the setting of the texture boundary color can be improved, and the user experience is improved.

Provided are a wireless communication method, and a communication device. The method comprises: a first device sending first indication information to a second device, wherein the first device is a device for determining a beamforming feedback angle, and the first indication information is used for indicating a first quantization bit number of the beamforming feedback angle. The first quantization bit number may be determined by means of the first device. That is, a device for determining the feedback angle may determine the first quantization bit number. On this basis, a method for determining the first quantization bit number can be more flexible, such that a balance between the quantization precision and quantization overheads is achieved, thereby improving the reliability of a communication system.

The invention discloses a fault injection and detection method based on RTL, and relates to the technical field of aerospace fault-tolerant calculation, the fault injection and detection method is compatible with three single-particle fault types of SEU, SET and SEL, the injection bit number, duration and position can be customized by a user, and based on random number file configuration, the problems of single fault type and parameter solidification of an existing tool are solved; a bypass injection mechanism controlled by a timer is adopted, and a fault data flow is switched in a specified clock period, so that a trunk data flow is not influenced, and the occupation of system resources is reduced; a forward detection module is designed based on (13, 8) extended Hamming codes, a receiving end quickly locates the fault type and position through a syndrome look-up table, original data does not need to be transmitted back, and detection delay is effectively controlled; a streamlined design is adopted, check bit generation, fault injection, syndrome generation and fault information output are executed in parallel, and hardware resource overhead is obviously optimized.

The invention provides a data reading method and a memory controller thereof, which are suitable for a storage device with a rewritable nonvolatile memory module. The method comprises the following steps: executing a reading operation on a target physical page to obtain target data containing multiple pieces of bit page data; when the error bit number of the target bit page data exceeds a preset threshold value, obtaining a target voltage gear table corresponding to the bit page type, and selecting a current gear sequence number according to the sequence of the gear sequence numbers in the table to execute iterative rereading; and if the error bit number after rereading does not exceed the preset threshold value, acquiring original data and updating the target voltage gear table based on the current gear sequence number. According to the method, the sequence of the voltage gear table is maintained, and the voltage gear group with high rereading success rate is preferentially used, so that the trying times of rereading operation can be effectively reduced, and the rereading efficiency of the flash memory is improved.

The invention relates to the technical field of three-dimensional graphic rendering, in particular to a multi-model surface filling method based on template buffering, a terminal and a storage medium, and the method comprises the following steps: obtaining a plurality of to-be-processed models and sectioning planes, and generating corresponding surface filling planes; setting corresponding numbers according to bits for the to-be-processed model and the patch plane; performing double-sided rendering on the to-be-processed model, and performing single-sided rendering on the complement plane; and discarding the slice elements of the patch plane of which the binary bit corresponding to the serial number is not 1 in the template value, and finishing trimming of the patch plane. According to the method, a bitwise corresponding numbering rule, combination of double-sided rendering and bitwise negation and a parallelization mechanism that multiple models share a single template value are utilized, and the problems that a traditional method frequently empties template values, strictly depends on sequential rendering, is insufficient in support for multiple models and the like are solved.

The invention discloses an active-active storage difference data recording method and system based on a difference bitmap, and the method comprises the steps: receiving a write request initiated by a service cluster, and determining a currently used difference bitmap; according to the positions of the difference bitmaps, two difference bitmap spaces are respectively allocated from a physical partition of the dual-active volume disk in advance when the dual-active relation is created; calculating the initial position of the write request in the difference bitmap and the bit number of the write request IO length required to be recorded in the difference bitmap, and setting the bit number at the corresponding position in the currently used difference bitmap as dirty; according to the write request, executing a dual-active master-slave site storage array disk falling operation; and after judging that the use time of the currently used difference bitmap exceeds a preset time or when the ratio of the record dity bit of the currently used difference bitmap exceeds a preset threshold value, switching the currently used difference bitmap to another difference bitmap. According to the invention, the data consistency of the active-active storage sites can be ensured.

The present application relates to the technical field of video decoding. Provided in the embodiments of the present application are a video image decoding method and coding method, an apparatus, and a storage medium, which help to improving the image quality. The method comprises: acquiring channel-level complexity levels from a data stream, the data stream being a coding data stream of a current block; according to at least two channel-level complexity levels, determining the block-level complexity level of the current block, the channel-level complexity levels being used for representing the complexity degree of the channel-level texture of the current block; according to a code control parameter, determining a target bit number of the current block, the code control parameter comprising the block-level complexity level of the current block; on the basis of the target bit number, determining a quantization parameter of the current block; and on the basis of the quantization parameter, decoding the current block.

The invention provides a configuration design method and device and electronic equipment, and relates to the technical field of automatic development. The method comprises the following steps: based on a preset template library, determining a first configuration template matched with a to-be-designed project in the preset template library; matching the first bit number corresponding to the second bit number of each component in the control system corresponding to the project to be designed; replacing the first bit number in the first configuration template with the second bit number matched with the first bit number to obtain a second configuration template comprising the second bit number and second configuration information corresponding to the second bit number; and according to the second configuration template, generating an execution file for a control system corresponding to the to-be-designed project. Based on the preset template library, through bit number matching and bit number replacement, calendar project experience and technical assets are fully utilized, the configuration design efficiency and reliability are improved, and the design cost and difficulty are reduced.

The invention discloses a magnetic flux regulation crosstalk calibration method for quantum bits, and relates to the technical field of quantum, and the method comprises the steps: S1, obtaining an initial calibration parameter of a target quantum system through employing an initial crosstalk matrix; s2, generating a plurality of groups of random magnetic flux configuration signals containing magnetic flux regulation and control values by using the initial crosstalk matrix; s3, constructing a modified crosstalk matrix by using the random magnetic flux configuration signal; and S4, acquiring a correction calibration parameter by using the correction crosstalk matrix, performing error evaluation, if the error evaluation is met, completing correction, and if the error evaluation is not met, returning to the step S2. Compared with the prior art, the method has the advantages that the frequency offset matrix is constructed, the crosstalk matrix is corrected, and the corrected crosstalk matrix is generated by using the quasi-Monte Carlo method and the frequency offset matrix, so that the high sampling complexity in direct proportion to the square of the bit number in two-dimensional spectrum scanning is avoided; the method has the advantages of improving the calibration precision and reducing the complexity of a phase measurement experiment process.

Field programmable gate array (FPGA) based lossless data compression may be used in a test device such as a spectrum analyzer to efficiently reduce the data transfer rate and needed memory. Multi-channel IQ data may be flexibly recorded using multiple lanes of high data rate connections such as JESD204B / C and PCIe between an analog-digital-converter (ADC), the FPGA, and a processor. Bandwidth, sample rate, and / or bit number may determine the IQ data size. When the IQ data size is less than a product of the compression coefficient and the data transfer rate, the lossless compression may be skipped saving logic usage and power consumption in FPGA. Thus, depending on memory and transfer rate perspectives, a decision may be made whether the compression needs to be used or not.

The embodiment of the invention provides a PCB component direction silk-screen adjusting method, electronic equipment and a storage medium, and relates to the field of PCB design, the method comprises the following steps: obtaining packaging names and bit numbers of all components in a PCB, obtaining an information table, aiming at each packaging name in the information table, when the packaging name has a welding direction requirement, adjusting the welding direction of each component in the information table; the method comprises the steps of determining at least one bit number corresponding to a packaging name, determining an indication pin number corresponding to the packaging name, the position of a component in a PCB and the position of a direction indication pin, generating a set query area, and when component direction silk-screen exists in the set query area and an interference risk exists, adjusting the component direction silk-screen. Manual intervention is not needed, and the efficiency of direction screen printing adjustment is improved.

The invention relates to the technical field of automatic generation of sequence control codes, and provides a method and system for automatically generating sequence control codes of a DCS (Distributed Control System), and the method comprises the following steps: S1, formulating a standardized template rule of a sequence control scheme, the standard template rule defines a preset type of sequential control steps, and sets formats of required parameters and selectable parameters including the preset type, the equipment bit number and the bit number description of each step; s2, filling in a sequence control scheme according to the standardized template rule, determining the preset type of each step, the equipment bit number of the associated equipment and the bit number description, and supplementing control logic parameters required by the preset type of the corresponding step; and S3, analyzing the sequence control scheme through a conversion tool, and automatically converting the analyzed step information into a sequence control code which can be imported into the DCS based on a code grammar rule of the DCS. The invention aims to solve the problems of high difficulty in writing sequence control of a DCS (Distributed Control System), high time consumption and high error rate of codes.

The invention provides a hybrid precision quantification method and system based on neural network architecture search. The method comprises the following steps: dividing a whole model structure into a plurality of modules; performing a quantitative sensitivity test on the whole model and each module, and setting an initialization bit number of each module; building a search space based on the number of divided modules, a set weight and an activated quantization structure; based on the initialized bit number, under the constraint that the overall average quantization precision of the model is kept unchanged, the overall verification performance serves as an optimization target, searching is carried out in the search space, weight and activated bit width self-adaptive distribution is carried out, and an optimal quantization scheme of the mixed precision is obtained. According to the method, the model expression ability and the task performance are maximized under the limited bit budget by introducing an adaptive weight and activation bit width allocation mechanism based on NAS (Neural Network Architecture Search).

The invention discloses a storage device and a detection method and device of the storage device. The detection method of the storage device comprises the steps of obtaining a data protection level of the storage device; in response to the condition that the data protection level is lower than a preset level, performing a first test on all the storage blocks to obtain a first error bit number corresponding to any storage area in each storage block; in response to the fact that the first error bit number is larger than a first threshold value and the corresponding storage area is a target storage area, performing a second test on the target storage area to obtain a second error bit number corresponding to the target storage area; wherein the target storage area with the second error bit number smaller than the second threshold value can reduce the error bit number generated in the read-write process through optimization; and determining whether the corresponding storage block is a bad block or not according to the first error bit number and / or the second error bit number. According to the mode, the testing efficiency of testing the storage equipment can be improved, and the product yield of the storage equipment can be improved.

The invention provides an SSB index indication method, a communication device and a computer readable storage medium, and relates to the technical field of communication. In the method, a base station sends an SSB comprising a PBCH and a demodulation reference signal of the PBCH to a terminal device, and the PBCH and the demodulation reference signal indicate an SSB index in a preset mode. And when the bit number of the SSB index is greater than the first preset bit number, jointly indicating the SSB index through M first bits and N second bits in the additional load bits of the PBCH and the demodulation reference signal. According to the invention, on the premise of not increasing extra resource occupation, the indication range of the SSB index is obviously expanded, the channel utilization efficiency is improved, the problem of limited expansibility caused by insufficient indication bit width of the SSB index is effectively relieved, the requirement of a 5GNR network for more SSB index indications in high-frequency-band communication and complex scenes is met, and the service life of the 5GNR network is prolonged. And technical support is provided for efficient operation of a future network.

The invention provides a communication method and a communication device supporting a variable authentication label length, and the method comprises the steps: generating a first key stream and a second key stream according to input data through employing a ZUC algorithm, and carrying out the encryption processing of the input data through employing the first key stream, and obtaining a ciphertext message; a secret key mixing step: performing shift operation on the current secret key and the next secret key in the second secret key stream to obtain secret key mixed data; a first updating step: updating the next secret key as the current secret key, and sequentially repeating the secret key mixing step and the first updating step for at least one time until all secret key mixed data is obtained; calculating a target message authentication code according to the second key stream and all key mixed data; and sending the ciphertext message and the target message authentication code to a communication receiver. The problem that in the prior art, the bit number of integrity verification is too single, and integrity verification of different lengths cannot be adopted for messages of different importance degrees, so that the risk that a secret key is attacked and cracked is increased is solved.

The present application relates to the technical field of video decoding. Provided in the embodiments of the present application are a video image decoding method and coding method, an apparatus, and a storage medium, which help to improving the image quality. The method comprises: acquiring channel-level complexity levels from a data stream, the data stream being a coding data stream of a current block; according to at least two channel-level complexity levels, determining the block-level complexity level of the current block, the channel-level complexity levels being used for representing the complexity degree of the channel-level texture of the current block; according to a code control parameter, determining a target bit number of the current block, the code control parameter comprising the block-level complexity level of the current block; on the basis of the target bit number, determining a quantization parameter of the current block; and on the basis of the quantization parameter, decoding the current block.

The invention belongs to the technical field of engineering energy industry. An engineering energy industry equipment document and drawing bit number automatic extraction system comprises a document drawing uploading module used for uploading a to-be-processed file to the system; the document drawing preprocessing module is used for preprocessing the uploaded file to obtain a target file; the document drawing OCR module is used for carrying out OCR identification on the target file and extracting characters in the file to obtain character information; the bit number information extraction module is used for matching and extracting the character information according to a preset rule to obtain bit number information conforming to the preset rule; the bit number position positioning module is used for positioning the bit number information to the bit number position of the target file to obtain bit number position information; the bit number accuracy matching module is used for performing similarity matching on the bit number information and bit numbers in an existing bit number library to obtain the bit number information with the highest similarity; and the extraction result storage module is used for storing the position information.

The invention relates to a thermal power generating unit operation index data evaluation method and system, and relates to the field of data analysis, and the method comprises the steps: obtaining an element service duration list, operation environment monitoring information and operation instruction time sequence information of a first bit number thermal power generating unit of a target model; when the element service duration list is inconsistent with the element reference service duration list, or the operation environment monitoring information is inconsistent with the reference operation environment, taking the element reference service duration list, the reference operation environment and the operation instruction time sequence information as constraints, and based on a historical sample library, retrieving an operation index record data set meeting the target model; and performing mode analysis on the operation index record data set, obtaining an operation index reference state, correcting an operation index monitoring state, obtaining an operation index updating state, and executing operation index data evaluation. The technical problems that thermal power generating unit assessment index data is not accurate, and evaluation result limitation is caused by only considering operation differences are solved.

The embodiment of the invention discloses a data processing method capable of being applied to a high-speed optical transmission network. The method comprises the following steps: obtaining second bit data according to first bit data of which the number of bits is din, the second bit data comprising the bits in the din first bit data, dCRC check bits and / or dPAD filling bits; scrambling the second bit data to obtain third bit data, wherein the bit number dscr of the third bit data is equal to din + dCP, and dCP is equal to dCRC + dPAD; then probability constellation shaping PCS processing is carried out on a first bit subset in a first bit set with the bit number of m to obtain a second bit subset, and the first bit set is obtained from the third bit data; performing FEC coding and interleaving processing on the second bit subset and a third bit subset except the first bit subset in the first bit set to obtain a second bit set; according to the invention, different values of the din, the m and the dCP are given, the existing 400G network can be compatible, the performance is excellent, and the cost is low.

The application relates to a cement rotary kiln control parameter optimization method, which comprises the following steps: firstly, obtaining each target bit number data type related to the cement f-CaO content under the target cement rotary kiln working state; then, obtaining each to-be-referenced optimal control parameter vector based on a vector composed of each target bit number data type data value at each to-be-analyzed time point; then, obtaining the to-be-referenced optimal control parameter vector with the highest similarity to the current vector in each to-be-referenced optimal control parameter vector based on a current vector composed of the data values of each target bit number data type of the target cement rotary kiln under the current working state, and forming a target optimal control parameter vector; finally, adjusting each target bit number data type corresponding to the current working state of the target cement rotary kiln with the target optimal control parameter vector as the target; in this way, the working condition gradually approaches or reaches the historical best level, so that the output and quality of the clinker are effectively improved.

The invention discloses a quantum computing gate circuit expression and compression method and a medium, and relates to the technical field of quantum computing, and the method comprises the steps: setting a conversion expression character between a user side and a quantum computing cloud platform, or setting the conversion expression character between the quantum computing cloud platform and a terminal quantum computer for unifying quantum languages; the conversion expression character is divided into three segments which are an operation code, a bit code and a parameter code in sequence, the operation code refers to quantum gate operation, the bit code refers to a quantum bit number, and the parameter code refers to a floating-point number related to the operation code; the core of the method is that the file volume is compressed and the quantum language is unified, so that the problem of transmission efficiency of existing codes among different terminals is solved.

The invention discloses a control method of an approximate adder circuit based on a memristor and an approximate adder device, and belongs to the technical field of microelectronic devices. Wherein the approximate adder circuit only comprises 2n + 1 memristors and a resistor, the approximate addition process of two n-bit numbers is divided into initialization and n rounds of approximate addition method sub-processes, and each round of approximate addition method sub-process executes 1-bit approximate addition operation; a first memristor, a second memristor and a third memristor are correspondingly selected in each round of approximate addition method sub-process, 1-bit approximate addition operation can be achieved only by performing state setting on the first memristor and the second memristor and performing pressurization on the memristors and resistors, and the actual operation steps needed by the whole approximate addition are only 2n + 1 steps; compared with an existing n-bit approximate adder, the n-bit approximate adder can achieve approximate addition operation with high calculation precision under the condition that few devices and operation steps are adopted.