313 results about "Bit numbering" patented technology

The invention discloses a fusion multiply-add operation circuit compatible with multiple floating-point number formats, and the circuit comprises an input device which is used for obtaining three floating-point numbers and control information in a fusion multiply-add operation instruction; the input decoding device is used for analyzing the control information and extracting the symbol, the index and the mantissa of each floating-point number; the multiplication correlation device is used for calculating an initial index, a mantissa product and an initial symbol; the addend aligning and shifting device is used for completing addend mantissa aligning and shifting; the additive operation correlation device is used for calculating an addition result, a symbol, a normalized shift bit number and a direction flag bit according to the mantissa product sum; the original result processing device is used for generating an initial rounding bit, a normalized shift pasting bit and intermediate result data; and the final result output device is used for outputting a final operation result compatible with the IEEE-754 or Point floating-point number according to the rounding information. The circuit area and power consumption are remarkably reduced through hardware integration, and meanwhile the calculation efficiency is improved.

The embodiment of the invention discloses a floating point calculation device and method for a processor, electronic equipment and a storage medium, and the device comprises a mantissa alignment module which is used for carrying out the interception processing of a first mantissa of a first floating point number based on an interception digit to obtain a first addend, and carrying out the first addend based on a shift digit to obtain a second addend; the second mantissa of the second floating-point number is shifted to obtain a second addend, and the first addend and the second addend are two mantissas with aligned indexes; the interception bit number and the shift bit number are determined based on an index difference value between a first index of the first floating-point number and a second index of the second floating-point number; the adder is used for adding the first addend and the second addend to obtain a first mantissa sum; and the post-processing module is used for performing normalization processing and rounding processing on the first mantissa sum to obtain a target mantissa. Therefore, the selector processing process before the mantissa is shifted in the floating point addition calculation process can be reduced, the calculation path is shortened, and the calculation speed is improved.

The invention provides a data processing method, device and system, and relates to the technical field of computers. According to the data processing method, an access logic address of a user in the storage system is converted into a first physical address and a second physical address, an error correction code is read or written according to the first physical address and the second physical address, and the first physical address and the second physical address correspond to different address spaces of different storage particles in a memory. Under the condition that the storage medium fault area has aggregation characteristics and the fault areas of different storage particles are the same or similar, code words of error correction codes are written or read in different address spaces, namely different bit fault rate areas, in different storage particles, so that the code words of the error correction codes are dispersed in the address spaces of the different bit fault rate areas; the maximum error bit number of the code word of the error correction code can be reduced, the error bit number difference of accessing different address spaces is reduced, the waste of error correction code resources is reduced, and the reliability of a memory is improved while the utilization rate of the error correction code resources is improved.

The invention relates to an equipment rotating speed monitoring-based equipment operation data full-amount storage method, which relates to the field of data processing, and comprises the following steps of: constructing a query fault-tolerant condition based on an equipment model of to-be-monitored bit number equipment, a transmission element model list and a transmission element service life list; searching a historical operation sample group meeting a query fault tolerance condition; counting a plurality of control mode starting completion rotation speed characteristic values of the historical operation sample group, setting the minimum value as a rated rotation speed upper limit value, counting a plurality of control mode stopping completion rotation speed characteristic values of the historical operation sample group, and setting the maximum value as a rated rotation speed lower limit value; when the equipment monitoring rotating speed at the first moment falls between the rated rotating speed lower limit value and the rated rotating speed upper limit value, full storage is started, otherwise, interval storage is executed according to a preset period, and the problems that key parameter changes in the equipment starting and stopping process are difficult to accurately capture, data storage efficiency is low, and important information is prone to being missed are solved. And maintenance and analysis are difficult to carry out.

The invention discloses a novel digital hybrid coding method based on a large model. The method comprises the following steps: S1, preprocessing to-be-coded data; s2, performing feature coding on the preprocessed data by adopting a diffusion model driven feature learning method; s3, performing neural network coding on the feature coding data, and dynamically adjusting the coding bit number based on a variable bit rate quantization method; s4, performing adaptive entropy coding on the neural network coding data, and performing probability density transformation based on a normalized flow entropy coding method; s5, discrete transform coding is carried out on entropy coding data, and hierarchical quantization is carried out on different frequency components by adopting a hierarchical sub-block quantization method; and S6, based on the code length distribution and entropy coding parameters of the A3C optimization transformation coding data, extracting a lightweight coding model from the diffusion model by using a knowledge distillation method, and generating final optimization coding data. Through the hybrid coding and dynamic optimization strategy, the data compression efficiency and the coding quality are remarkably improved.

The embodiment of the invention provides a color setting method, a graphic processing unit and a system on chip. The method applied to GPU user mode driving comprises the steps that under the condition that a rendering preparation instruction is received, a first bit field of a sampling descriptor is set as a first identifier, the first identifier is used for pointing to a preset table located in a memory, and the table is used for storing boundary colors with the color format exceeding the bit number of the sampling descriptor; writing a target color carried in the rendering preparation instruction into the preset table; acquiring a second identifier of the target color in the preset table; and writing a second identifier of the target color in the preset table into a second bit field of the sampling descriptor, and sending the sampling descriptor to GPU hardware, so that the GPU hardware realizes texture boundary color setting according to the sampling descriptor. According to the embodiment of the invention, the storage format and precision of the target color can be expanded, so that the setting of the texture boundary color can be improved, and the user experience is improved.

The invention discloses a fault injection and detection method based on RTL, and relates to the technical field of aerospace fault-tolerant calculation, the fault injection and detection method is compatible with three single-particle fault types of SEU, SET and SEL, the injection bit number, duration and position can be customized by a user, and based on random number file configuration, the problems of single fault type and parameter solidification of an existing tool are solved; a bypass injection mechanism controlled by a timer is adopted, and a fault data flow is switched in a specified clock period, so that a trunk data flow is not influenced, and the occupation of system resources is reduced; a forward detection module is designed based on (13, 8) extended Hamming codes, a receiving end quickly locates the fault type and position through a syndrome look-up table, original data does not need to be transmitted back, and detection delay is effectively controlled; a streamlined design is adopted, check bit generation, fault injection, syndrome generation and fault information output are executed in parallel, and hardware resource overhead is obviously optimized.

The invention provides a data reading method and a memory controller thereof, which are suitable for a storage device with a rewritable nonvolatile memory module. The method comprises the following steps: executing a reading operation on a target physical page to obtain target data containing multiple pieces of bit page data; when the error bit number of the target bit page data exceeds a preset threshold value, obtaining a target voltage gear table corresponding to the bit page type, and selecting a current gear sequence number according to the sequence of the gear sequence numbers in the table to execute iterative rereading; and if the error bit number after rereading does not exceed the preset threshold value, acquiring original data and updating the target voltage gear table based on the current gear sequence number. According to the method, the sequence of the voltage gear table is maintained, and the voltage gear group with high rereading success rate is preferentially used, so that the trying times of rereading operation can be effectively reduced, and the rereading efficiency of the flash memory is improved.

The invention relates to the technical field of three-dimensional graphic rendering, in particular to a multi-model surface filling method based on template buffering, a terminal and a storage medium, and the method comprises the following steps: obtaining a plurality of to-be-processed models and sectioning planes, and generating corresponding surface filling planes; setting corresponding numbers according to bits for the to-be-processed model and the patch plane; performing double-sided rendering on the to-be-processed model, and performing single-sided rendering on the complement plane; and discarding the slice elements of the patch plane of which the binary bit corresponding to the serial number is not 1 in the template value, and finishing trimming of the patch plane. According to the method, a bitwise corresponding numbering rule, combination of double-sided rendering and bitwise negation and a parallelization mechanism that multiple models share a single template value are utilized, and the problems that a traditional method frequently empties template values, strictly depends on sequential rendering, is insufficient in support for multiple models and the like are solved.

The invention discloses an active-active storage difference data recording method and system based on a difference bitmap, and the method comprises the steps: receiving a write request initiated by a service cluster, and determining a currently used difference bitmap; according to the positions of the difference bitmaps, two difference bitmap spaces are respectively allocated from a physical partition of the dual-active volume disk in advance when the dual-active relation is created; calculating the initial position of the write request in the difference bitmap and the bit number of the write request IO length required to be recorded in the difference bitmap, and setting the bit number at the corresponding position in the currently used difference bitmap as dirty; according to the write request, executing a dual-active master-slave site storage array disk falling operation; and after judging that the use time of the currently used difference bitmap exceeds a preset time or when the ratio of the record dity bit of the currently used difference bitmap exceeds a preset threshold value, switching the currently used difference bitmap to another difference bitmap. According to the invention, the data consistency of the active-active storage sites can be ensured.

The present application relates to the technical field of video decoding. Provided in the embodiments of the present application are a video image decoding method and coding method, an apparatus, and a storage medium, which help to improving the image quality. The method comprises: acquiring channel-level complexity levels from a data stream, the data stream being a coding data stream of a current block; according to at least two channel-level complexity levels, determining the block-level complexity level of the current block, the channel-level complexity levels being used for representing the complexity degree of the channel-level texture of the current block; according to a code control parameter, determining a target bit number of the current block, the code control parameter comprising the block-level complexity level of the current block; on the basis of the target bit number, determining a quantization parameter of the current block; and on the basis of the quantization parameter, decoding the current block.

The invention discloses a magnetic flux regulation crosstalk calibration method for quantum bits, and relates to the technical field of quantum, and the method comprises the steps: S1, obtaining an initial calibration parameter of a target quantum system through employing an initial crosstalk matrix; s2, generating a plurality of groups of random magnetic flux configuration signals containing magnetic flux regulation and control values by using the initial crosstalk matrix; s3, constructing a modified crosstalk matrix by using the random magnetic flux configuration signal; and S4, acquiring a correction calibration parameter by using the correction crosstalk matrix, performing error evaluation, if the error evaluation is met, completing correction, and if the error evaluation is not met, returning to the step S2. Compared with the prior art, the method has the advantages that the frequency offset matrix is constructed, the crosstalk matrix is corrected, and the corrected crosstalk matrix is generated by using the quasi-Monte Carlo method and the frequency offset matrix, so that the high sampling complexity in direct proportion to the square of the bit number in two-dimensional spectrum scanning is avoided; the method has the advantages of improving the calibration precision and reducing the complexity of a phase measurement experiment process.

The invention relates to the technical field of automatic generation of sequence control codes, and provides a method and system for automatically generating sequence control codes of a DCS (Distributed Control System), and the method comprises the following steps: S1, formulating a standardized template rule of a sequence control scheme, the standard template rule defines a preset type of sequential control steps, and sets formats of required parameters and selectable parameters including the preset type, the equipment bit number and the bit number description of each step; s2, filling in a sequence control scheme according to the standardized template rule, determining the preset type of each step, the equipment bit number of the associated equipment and the bit number description, and supplementing control logic parameters required by the preset type of the corresponding step; and S3, analyzing the sequence control scheme through a conversion tool, and automatically converting the analyzed step information into a sequence control code which can be imported into the DCS based on a code grammar rule of the DCS. The invention aims to solve the problems of high difficulty in writing sequence control of a DCS (Distributed Control System), high time consumption and high error rate of codes.

The invention provides a hybrid precision quantification method and system based on neural network architecture search. The method comprises the following steps: dividing a whole model structure into a plurality of modules; performing a quantitative sensitivity test on the whole model and each module, and setting an initialization bit number of each module; building a search space based on the number of divided modules, a set weight and an activated quantization structure; based on the initialized bit number, under the constraint that the overall average quantization precision of the model is kept unchanged, the overall verification performance serves as an optimization target, searching is carried out in the search space, weight and activated bit width self-adaptive distribution is carried out, and an optimal quantization scheme of the mixed precision is obtained. According to the method, the model expression ability and the task performance are maximized under the limited bit budget by introducing an adaptive weight and activation bit width allocation mechanism based on NAS (Neural Network Architecture Search).

The invention discloses a storage device and a detection method and device of the storage device. The detection method of the storage device comprises the steps of obtaining a data protection level of the storage device; in response to the condition that the data protection level is lower than a preset level, performing a first test on all the storage blocks to obtain a first error bit number corresponding to any storage area in each storage block; in response to the fact that the first error bit number is larger than a first threshold value and the corresponding storage area is a target storage area, performing a second test on the target storage area to obtain a second error bit number corresponding to the target storage area; wherein the target storage area with the second error bit number smaller than the second threshold value can reduce the error bit number generated in the read-write process through optimization; and determining whether the corresponding storage block is a bad block or not according to the first error bit number and / or the second error bit number. According to the mode, the testing efficiency of testing the storage equipment can be improved, and the product yield of the storage equipment can be improved.

The invention provides a communication method and a communication device supporting a variable authentication label length, and the method comprises the steps: generating a first key stream and a second key stream according to input data through employing a ZUC algorithm, and carrying out the encryption processing of the input data through employing the first key stream, and obtaining a ciphertext message; a secret key mixing step: performing shift operation on the current secret key and the next secret key in the second secret key stream to obtain secret key mixed data; a first updating step: updating the next secret key as the current secret key, and sequentially repeating the secret key mixing step and the first updating step for at least one time until all secret key mixed data is obtained; calculating a target message authentication code according to the second key stream and all key mixed data; and sending the ciphertext message and the target message authentication code to a communication receiver. The problem that in the prior art, the bit number of integrity verification is too single, and integrity verification of different lengths cannot be adopted for messages of different importance degrees, so that the risk that a secret key is attacked and cracked is increased is solved.

The present application relates to the technical field of video decoding. Provided in the embodiments of the present application are a video image decoding method and coding method, an apparatus, and a storage medium, which help to improving the image quality. The method comprises: acquiring channel-level complexity levels from a data stream, the data stream being a coding data stream of a current block; according to at least two channel-level complexity levels, determining the block-level complexity level of the current block, the channel-level complexity levels being used for representing the complexity degree of the channel-level texture of the current block; according to a code control parameter, determining a target bit number of the current block, the code control parameter comprising the block-level complexity level of the current block; on the basis of the target bit number, determining a quantization parameter of the current block; and on the basis of the quantization parameter, decoding the current block.

The invention relates to a thermal power generating unit operation index data evaluation method and system, and relates to the field of data analysis, and the method comprises the steps: obtaining an element service duration list, operation environment monitoring information and operation instruction time sequence information of a first bit number thermal power generating unit of a target model; when the element service duration list is inconsistent with the element reference service duration list, or the operation environment monitoring information is inconsistent with the reference operation environment, taking the element reference service duration list, the reference operation environment and the operation instruction time sequence information as constraints, and based on a historical sample library, retrieving an operation index record data set meeting the target model; and performing mode analysis on the operation index record data set, obtaining an operation index reference state, correcting an operation index monitoring state, obtaining an operation index updating state, and executing operation index data evaluation. The technical problems that thermal power generating unit assessment index data is not accurate, and evaluation result limitation is caused by only considering operation differences are solved.

The embodiment of the invention discloses a data processing method capable of being applied to a high-speed optical transmission network. The method comprises the following steps: obtaining second bit data according to first bit data of which the number of bits is din, the second bit data comprising the bits in the din first bit data, dCRC check bits and / or dPAD filling bits; scrambling the second bit data to obtain third bit data, wherein the bit number dscr of the third bit data is equal to din + dCP, and dCP is equal to dCRC + dPAD; then probability constellation shaping PCS processing is carried out on a first bit subset in a first bit set with the bit number of m to obtain a second bit subset, and the first bit set is obtained from the third bit data; performing FEC coding and interleaving processing on the second bit subset and a third bit subset except the first bit subset in the first bit set to obtain a second bit set; according to the invention, different values of the din, the m and the dCP are given, the existing 400G network can be compatible, the performance is excellent, and the cost is low.

The application relates to a cement rotary kiln control parameter optimization method, which comprises the following steps: firstly, obtaining each target bit number data type related to the cement f-CaO content under the target cement rotary kiln working state; then, obtaining each to-be-referenced optimal control parameter vector based on a vector composed of each target bit number data type data value at each to-be-analyzed time point; then, obtaining the to-be-referenced optimal control parameter vector with the highest similarity to the current vector in each to-be-referenced optimal control parameter vector based on a current vector composed of the data values of each target bit number data type of the target cement rotary kiln under the current working state, and forming a target optimal control parameter vector; finally, adjusting each target bit number data type corresponding to the current working state of the target cement rotary kiln with the target optimal control parameter vector as the target; in this way, the working condition gradually approaches or reaches the historical best level, so that the output and quality of the clinker are effectively improved.

The invention discloses a quantum computing gate circuit expression and compression method and a medium, and relates to the technical field of quantum computing, and the method comprises the steps: setting a conversion expression character between a user side and a quantum computing cloud platform, or setting the conversion expression character between the quantum computing cloud platform and a terminal quantum computer for unifying quantum languages; the conversion expression character is divided into three segments which are an operation code, a bit code and a parameter code in sequence, the operation code refers to quantum gate operation, the bit code refers to a quantum bit number, and the parameter code refers to a floating-point number related to the operation code; the core of the method is that the file volume is compressed and the quantum language is unified, so that the problem of transmission efficiency of existing codes among different terminals is solved.

The invention discloses an HPLC (High Performance Liquid Chromatography) signal processing method based on bit loading, and belongs to the technical field of power line carrier communication. The HPLC signal processing method based on bit loading comprises the following steps: reading bit data from a channel interleaving module, and sequentially writing the bit data into a first bit buffer queue according to a preset read bit number of the channel interleaving module; in the bit loading mode, aiming at the modulation mode corresponding to each subcarrier, determining a target bit number required to be filled by each subcarrier; different modulation modes correspond to different target bit numbers; and sequentially reading the bit data of the target bit number from the first bit buffer queue according to the write-in sequence, and mapping the bit data read as required to the corresponding subcarrier for modulation and transmission. According to the invention, rate efficient matching of data processing in a bit loading mode and data transmission without subcarrier cross-physical blocks are realized.

The invention discloses a dual-mode communication chip, and belongs to the technical field of communication. The dual-mode communication chip comprises an HPLC (High Performance Liquid Chromatography) signal transmitting end and an HPLC signal receiving end; the HPLC signal transmitting end is configured as a coding module and is used for coding the load data to obtain coded load data; the first storage module is used for storing the coded load data; the channel interleaving module is used for carrying out interleaving processing on the bit data read out from the first storage module; the first bit buffer queue is used for sequentially writing the bit data from the channel interleaving module according to a first bit number and sequentially reading the bit data according to a writing sequence according to a second bit number; and the bit mapping module is used for mapping the bit data from the first bit buffer queue to each subcarrier with a second bit number. According to the invention, rate efficient matching of data processing in a high-order modulation mode and data transmission without subcarrier cross-physical blocks are realized.

The application relates to a calculation method for realizing a Tanh excitation function based on FPGA, which comprises the following steps: obtaining the quantization bit number during FPGA realization, determining the decimal bit quantization bit number, determining the accuracy of input and output values of the Tanh excitation function and the range of the output values based on the decimal bit quantization bit number, processing the values greater than 0 based on four linear fittings, one quadratic fitting and two table storage respectively, and mapping and processing the values less than 0 based on the odd symmetry of the Tanh function. The application can realize the Tanh function with high accuracy under the condition that the FPGA resource is limited.

The embodiment of the application discloses a data format conversion device and method, electronic equipment and computer storage medium, the data format conversion device comprises: a first shift module, which is used for first extended shift of a normalized format number to be converted integer, and obtains a shift integer; the bit number of the shift integer is n times of the bit number of the integer to be converted; n is a positive integer; a second shift module is used for second extended shift of a normalized format number to be converted decimal, and obtains a shift decimal; an addition module is used for adding the shift integer and the shift decimal, and obtains a shift number; a floating point conversion module is used for floating point format conversion of the shift number, and obtains a floating point format number of the shift number; the floating point format number of the shift decimal is a target floating point number.

The application provides an uplink control information transmission method, a receiving method, a terminal and a network device, and the method comprises the following steps: in the case that a first uplink channel carrying a first HARQ-ACK and a second uplink channel carrying a second HARQ-ACK overlap in the time domain, determining a reference bit number of the second HARQ-ACK according to the bit number of the first HARQ-ACK; and transmitting the second HARQ-ACK and the first HARQ-ACK simultaneously on the same uplink channel according to the reference bit number. The application can ensure that the terminal and the network device have consistent understanding of the bit number of the HARQ-ACK transmitted by the terminal.

The invention discloses a load determination method, the method is applied to a transmitting end node, and the method comprises the following steps: receiving a channel quality parameter value and a first quantization bit number reported by a receiving end node; wherein the first quantization bit number is determined by the receiving end node based on a pre-configured signal-load dictionary set; determining a target signal-load dictionary matched with the signal quality parameter value and the first quantization bit number from the pre-configured signal-load dictionary set; determining a target load corresponding to a to-be-transmitted signal based on the target signal-load dictionary; and loading the target load to a signal transmitting device of the transmitting end node, and exciting to transmit the signal to be transmitted. The invention further discloses a load determination device and system, a storage medium and a computer program product.

A method for calculating the N-bit square root B of a 2N-bit number X comprises: performing a multiplication of the bits b of the square root B. i Iterate starting from the most significant bit of the square root B and working your way down to the least significant bit. For each iteration, the method includes: positioning a 1 at bit b in the CHECK variable. i The bit b is determined based on the comparison of the number X with all previously found bits and a function of the previous comparison results. i shift all previously found bits in the CHECK variable right by 1 position; and i The determined value is added to its square position in the CHECK variable.

A circuit for encoding a C-PHY signal, a decoding circuit and a transmission device, the encoding circuit being characterized by: obtaining a C-PHY line state, forming a line state block, mapping the line state block into a binary number capable of uniquely identifying the line state block, and setting different line state blocks for an HS mode, an LP mode and an ALP mode, and binary coding mapping is carried out according to the corresponding line state block, so that the coding efficiency is improved under different conditions. Furthermore, a flag bit is set, so that the bit number of binary coding is reduced, and the coding efficiency is improved. According to the invention, the complexity of a coding circuit is reduced, the integrity of coding information is kept, and the coding and decoding efficiency and the transmission real-time performance are improved from multiple angles through a series of methods such as flag bits and line state sub-blocks.

The invention discloses a component selection analysis system and an analysis method thereof, and the system comprises a configuration module which is used for configuring component parameter attribute information according to a component library and requirements, and configuring parameter attributes corresponding to components according to different application scenes; and the display module is used for displaying the corresponding component parameter attribute information in the schematic diagram according to the configured component parameter attribute, and positioning the position number of the component and the position of the component in the schematic diagram. According to the component selection analysis system and the component selection analysis method, component parameter attributes needing to be displayed can be configured, and the positions of related components can be automatically positioned and bit numbers can be displayed according to requirements. According to different application scenes, the model selection reports in different formats can be exported through self-configuration, and the applicability is high. Therefore, the model selection time is shortened, and the design efficiency is improved.