57434results about "Complex mathematical operations" patented technology

Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor architectures. The technique includes converting data from a multidimensional array stored in a conventional row-major order into SIMD format. Converted data in SIMD format consists of a sequence of blocks, where each block interleaves s rows such that SIMD vector processors may operate on s rows simultaneously. As a result, the converted data in SIMD format enables smaller-sized 1D FFTs to be optimized in SIMD multi-core processor architectures.

Method and system for preventing accidents between first and second vehicles includes a positioning system arranged in each vehicle for determining the absolute position thereof, a memory unit arranged in the first vehicle for storing data about travel lanes, a communication system for transmitting the position of the second vehicle to the first vehicle, a receiver system arranged in the first vehicle for receiving position information from the second vehicle, a processor coupled to the positioning system, the receiver system and the memory unit in the first vehicle for predicting a collision between the vehicles based on the position of the vehicles and travel lane data, and a reactive component arranged in the first vehicle and coupled to the processor. The reactive component is arranged to initiate an action or change its operation when a collision is predicted by the processor, e.g., sound or indicate an alarm.

A navigation and control system including one or more position sensors configured to generate position signals indicative of the location and heading of a vehicle. The system includes one or more operation control mechanisms having inputs and producing outputs which control an operation of the vehicle and includes a self-contained autonomous controller disposed remote from the operation control mechanisms. The autonomous controller includes a processor configured to receive the position signals from the position sensors and to generate operation control signals defining an updated travel path for the vehicle, and a programmable interface providing communication among the position sensors, the operation control mechanisms, and the processor. The programmable interface is configured to normalize inputs to the processor from the position sensors and to generate compatible operation control signals applied as the inputs to the operation control mechanisms, whereby the self-contained autonomous controller is configurable for operation with a variety of different sensors and different operation control mechanisms.

A vehicle information recording system 100 includes a picture acquiring unit 101a placed in a vehicle that takes a picture of surroundings and generates picture data showing the picture, a vehicle data receiving unit 107 placed in the vehicle that receives other vehicle data concerning another vehicle shown in the picture acquired by the picture acquiring unit 101a, an acquired information sending unit 103 placed in the vehicle that sends data including the picture data and the other vehicle data outside of the vehicle, a receiving unit 104 placed outside of the vehicle that receives the data sent by the acquired information sending unit 103, an encoding unit 105 placed outside of the vehicle that encodes the other vehicle data among the data received by the receiving unit 104 and adds the encoded data to the picture data as related data, and a recording unit 106 placed outside of the vehicle that records the picture data to which the other vehicle data is added by the encoding unit 105.

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.