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57053results about "Complex mathematical operations" patented technology

System and method for automated placement or configuration of equipment for obtaining desired network performance objectives and for security, RF tags, and bandwidth provisioning

A method is presented for determining optimal or preferred configuration settings for wireless or wired network equipment in order to obtain a desirable level of network performance. A site-specific network model is used with adaptive processing to perform efficient design and on-going management of network performance. The invention iteratively determines overall network performance and cost, and further iterates equipment settings, locations and orientations. Real time control is between a site-specific Computer Aided Design (CAD) software application and the physical components of the network allows the invention to display, store, and iteratively adapt any network to constantly varying traffic and interference conditions. Alarms provide rapid adaptation of network parameters, and alerts and preprogrammed network shutdown actions may be taken autonomously. A wireless post-it note device and network allows massive data such as book contents or hard drive memory to be accessed within a room by a wide bandwidth reader device, and this can further be interconnected to the internet or Ethernet backbone in order to provide worldwide access and remote retrieval to wireless post-it devices.
Owner:EXTREME NETWORKS INC

Data hierarchy layout correction and verification method and apparatus

A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout. As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.
Owner:SYNOPSYS INC

Internet navigation using soft hyperlinks

A system for internet navigation using soft hyperlinks is disclosed, in connection with an illustrative information retrieval system with which it may be used. The navigation tool provides freedom to move through a collection of electronic documents independent of any hyperlink which has been inserted within an HTML page. A user can click on any term in a document page, not only those that are hyperlinked. For example, when a user clicks on an initial word within the document, the disclosed system employs a search engine in the background to retrieve a list of related terms. In an illustrative embodiment, a compass-like display appears with pointers indicating the first four terms returned by the search engine. These returned terms have the highest degree of correlation with the initial search term in a lexical knowledge base that the search engine constructs automatically. The disclosed system allows the user to move from the current document to one of a number of document lists which cover different associations between the initial word clicked on by the user and other terms extracted from within the retrieved list of related terms. The disclosed system may further allow the user to move to a document that is considered most related to the initial word clicked on by the user, or to a list of documents that are relevant to a phrase or paragraph selection indicated by the user within the current page.
Owner:FIVER LLC

Simulation gridding method and apparatus including a structured areal gridder adapted for use by a reservoir simulator

A Flogrid Simulation Gridding Program includes a Flogrid structured gridder. The structured gridder includes a structured areal gridder and a block gridder. The structured areal gridder will build an areal grid on an uppermost horizon of an earth formation by performing the following steps: (1) building a boundary enclosing one or more fault intersection lines on the horizon, and building a triangulation that absorbs the boundary and the faults; (2) building a vector field on the triangulation; (3) building a web of control lines and additional lines inside the boundary which have a direction that corresponds to the direction of the vector field on the triangulation, thereby producing an areal grid; and (4) post-processing the areal grid so that the control lines and additional lines are equi-spaced or smoothly distributed. The block gridder of the structured gridder will drop coordinate lines down from the nodes of the areal grid to complete the construction of a three dimensional structured grid. A reservoir simulator will receive the structured grid and generate a set of simulation results which are displayed on a 3D Viewer for observation by a workstation operator.
Owner:SCHLUMBERGER TECH CORP

Novel massively parallel supercomputer

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input / Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.
Owner:INT BUSINESS MASCH CORP
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