281results about "Single instruction multiple data multiprocessors" patented technology

Aspects of the disclosure provide for an accelerator capable of accelerating data dependent, irregular, and / or memory-bound operations. An accelerator as described herein includes a programmable engine for efficiently executing computations on-chip that are dynamic, irregular, and / or memory-bound, in conjunction with a co-processor configured to accelerate operations that are predictable in computational load and behavior on the co-processor during design and fabrication.

Apparatuses, systems, and techniques to cause a descriptive representation of graph code to be generated. In at least one embodiment, a descriptive representation of graph code is caused to be generated based on, for example, CUDA or other parallel computing platform code.

This disclosure describes supporting distributed graphics and compute engines in a multi-dielet processor, such as, for example, a multi-dielet graphics processing unit (GPU), architectures and synchronization in such architectures. Each multi-dielet processor includes a hardware-implemented remapping capability and / or a hardware-implemented memory barrier capability.

An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.

The invention discloses a dynamic reconstruction method of a two-dimensional memory access controller, which belongs to the technical field of memory access controllers, and specifically comprises the following steps of: extracting the parallelism degree and the operation characteristic of a matrix algorithm, determining the partitioning mode of a storage module according to the parallelism degree and the operation characteristic, and storing matrix source data in a partitioning manner; based on the degree of parallelism, the number of enabled source data channels is determined, and efficient transmission of data from storage to calculation is achieved; according to the degree of parallelism and the operation characteristics, matrix source data are moved from the storage module to the calculation module through the source data channel, and matrix operation is executed; after the operation is finished, determining the number of enabled result data channels according to the degree of parallelism and a result, and transmitting the result back to the storage module; the configuration of each module is dynamically adjusted according to an algorithm and operation requirements, and the flexibility and efficiency of matrix operation are improved.

The embodiment of the invention provides a processor core, a processor and a method for the processor. The processor core includes a processing pipeline configured to rename and execute a first instruction including at least one of a first architectural register and a second architectural register, and includes: a first type of physical register configured to be mapped by the first architectural register and configured to store a first type of data; the first type of physical register is configured to be mapped by the first architecture register and configured to store data of a first type, the second type of physical register is configured to be mapped by the second architecture register and configured to store data of a second type, the first architecture register comprises a vector architecture register, the data of the first type stored by the first type of physical register comprises vector data, and the second architecture register comprises a mask architecture register; the second type of data stored in the second type of physical register comprises mask data. The processor core may mitigate processing pipeline stagnation and increase less area.

A data processing method is provided. The implementation is: for each of a plurality of data blocks included in data to be processed, dividing the data block into a plurality of first sub-blocks corresponding to a plurality of computing unit groups respectively; for each first sub-block of the plurality of first sub-blocks, dividing the first sub-block, based on a target computing unit group corresponding to the first sub-block, into a plurality of second sub-blocks corresponding to the plurality of computing units in the target computing unit group, respectively; determining, by processing each second sub-block utilizing the corresponding computing unit of the second sub-block, a plurality of first processing results output by the plurality of computing units respectively; and determining a processing result of the first sub-block by performing a data reduction operation on the plurality of first processing results utilizing the target computing unit group.

Embodiments of the invention provide a data processing method and apparatus, an electronic device and a storage medium. The method comprises the steps of obtaining a unit vector operation width supported by hardware; obtaining a source address to be aligned and the number of object data to be operated; in response to the fact that the width of the object data is larger than or equal to a first threshold value, the remainder obtained after the to-be-aligned source address is aligned with the unit vector operation width is calculated so as to obtain the data width of which the addresses are not aligned in the object data, and the width of the object data is equal to the product of the unit data width of the object data and the number of the object data; the width of the address misalignment data is equal to the difference value between the unit vector operation width and the remainder; determining the number of the address misalignment data according to the unit data width of the object data and the width of the address misalignment data, and determining first mask information based on the number of the address misalignment data and the unit vector operation width; and according to the first mask information, loading and processing the data of which the addresses are not aligned, and the method improves the data processing performance.

Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

The invention relates to a data processing system. When rendering is performed in a tile-based graphics processor including a plurality of rendering processors, different regions of rendering output are allocated to different ones of the rendering processors for processing. The processing of the rendered output is tracked to determine when a portion of the rendered output that is still to be allocated to the rendering processor for processing falls below a threshold, and when it is determined that the portion of the rendered output that is still to be allocated to the rendering processor for processing falls below the threshold, the rendered output is output to the rendering processor. A smaller cell of the rendered output is then allocated to the rendering processor for processing.

The present disclosure provides a data processing method, apparatus, device and storage medium. The data processing method includes: determining at least one first vector register storing a first matrix and at least one second vector register storing a second matrix, in which the first matrix includes a plurality of pieces of first operational data, the second matrix includes a plurality of pieces of second operational data; obtaining first data selection information and second data selection information; selecting at least one piece of first operational data from the plurality of pieces of first operational data based on the first data selection information to obtain at least one piece of first target operational data and selecting at least one piece of second operational data from the plurality of pieces of second operational data based on the second data selection information to obtain at least one piece of second target operational data.

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

A system includes a component configured to send data in a first data format. The system includes a direct memory access (DMA) engine configured to receive the data in the first data format and convert the first data format to a second data format, wherein the second data format is associated with a data format of a machine learning (ML) hardware, wherein the second data format is different from the first data format. The ML hardware is configured to receive the data in the second format and perform at least one ML operation on the received data in the second format. The received data in the second data format is stored on an on-chip memory (OCM) of the ML hardware.

Examples include techniques for contention-free routing for number-theoretic-transform (NTT) or inverse-NTT (iNTT) computations routed through a parallel processing device. Examples include a tile array that includes a plurality of tiles arranged in a 2-dimensional mesh interconnect-based architecture. Each tile includes a plurality of compute elements configured to execute NTT or iNTT computations associated with a fully homomorphic encryption workload. Contention-free routing to include use of selective stalls and destination ports indicated in routing tables maintained at tiles of the tile array can facilitate NTT / iNTT computation throughput through the parallel processing device.

A data processing apparatus comprises operand routing circuitry configured to prepare operands for processing, and a plurality of processing elements. Each processing element comprises receiving circuitry, processing circuitry, and transmitting circuitry. A group of coupled processing elements comprises a first processing element configured to receive operands from the operand routing circuitry and one or more further processing elements for which the receiving circuitry is coupled to the transmitting circuitry of another processing element in the group. The apparatus also comprises timing circuitry, configured to selectively delay transmission of operands within the group of coupled processing elements to cause operations performed by the group of coupled processing elements to be staggered.

The invention discloses a sensing, storing and computing integrated macro-cell circuit, a sensing, storing and computing integrated macro-cell system and a digital-to-analog conversion method. The digital-to-analog conversion method comprises the following steps: setting a weight coefficient; writing weight signals into the analog storage and calculation unit through an iSC bus according to the weight coefficient, wherein each bit of the digital signal corresponds to one weight signal; the tag module reads the digital signal from the iSC bus and sequentially obtains each bit of the digital signal; carrying out digital-to-analog conversion calculation according to a formula of DREGn * weight signals; and after all bits of the digital signal are converted and calculated, the conversion result corresponding to each bit of digital signal is accumulated to obtain an analog signal, so that the analog domain signal and the digital domain signal are efficiently and parallelly converted.

To provide methods, systems and other embodiments for incorporating a balanced binary tree into multiplication modules of a tensor processor so as to execute sequences of instructions more efficiently for stream-reducing operations; where this abstract and the independent claims are concise signifiers of embodiments of the claimed inventions, and the abstract does not limit the scope of the claimed inventions.SOLUTION: In one or more ECINs disclosed herein, balanced binary tree structures are disclosed that enable a compiler to locally optimize an aggregation operation for the timing / area as needed without having an impact on the overall architecture.SELECTED DRAWING: Figure 1

The invention discloses a sensing, storing and computing integrated macro-cell circuit, a sensing, storing and computing integrated macro-cell system and an analog-to-digital conversion method. The method comprises the following steps: a tag module reads an analog signal from an iSC bus; the label module carries out traversal comparison on the read analog signal and a plurality of reference analog signals; obtaining a corresponding digital signal according to a comparison result; the plurality of reference analog signals are data which are gradually increased or decreased along with the function relationship. According to the method, a special ADC (Analog to Digital Converter) circuit is not needed, and the conversion function is realized by utilizing the existing PE circuit.

Systems and methods for faster BVH building that requires repeated sorting and partitioning of are described. Specific hardware circuitries are programmed to sort partitioned data and make reductions for each partition. The hardware units perform the initial sorting along a split axis and calculation of bounding box extents. The solutions presented herein improve performance of BVH builds, especially for cases where the geometry is comprised of many small BVH treelets. The most expensive processing steps in BVH construction are delegated to hardware thereby minimizing memory access latencies and increasing overall system efficiencies.

To provide an instruction execution device configured to implement high computational throughput and energy efficiency, a method, electronic equipment, and a storage medium.SOLUTION: An instruction execution device 100 includes: a dispatching unit configured to respond to determining that at least one source register used for an instruction to be executed corresponds to at least one uniform register in a plurality of uniform registers, the instruction to be executed serving as a uniform instruction including a plurality of uniform computing operations to be dispatched to a first computing unit; and the first computing unit configured to execute uniform calculation operation to obtain a uniform calculation result, the uniform calculation result being written into at least one available uniform register in the plurality of uniform registers.SELECTED DRAWING: Figure 1

An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

Apparatus, systems, and techniques for causing one or more software modules to be executed by a processor simultaneously. In at least one embodiment, the one or more processors execute one or more software drivers to cause two or more graphics kernels to be executed simultaneously. In at least one embodiment, causing the two or more graphics kernels to be executed simultaneously includes performing operations to prepare the two or more graphics kernels to be launched on one or more graphics processing cores. In at least one embodiment, the one or more software drivers are to receive instructions from an application programming interface (API) to prepare the two or more graphics kernels to be executed simultaneously.

A technique is disclosed for operand propagation and accumulation within a processing array of an integrated circuit using overlapping patch regions. The system includes an interconnecting processing patch defined over a rectilinear subset of processing elements, with an origin processing element broadcasting operand data to the remaining elements in a directionally constrained, time-staggered wavefront pattern. A logical processing patch is separately defined over a second rectilinear subset of processing elements. The interconnecting processing patch and the logical processing patch partially overlap to form an interconnecting patch mesh comprising a common set of processing elements. Operand data is propagated from the origin of the interconnecting patch to the common processing elements within the patch mesh, enabling operand handoff or accumulation across patch boundaries. The architecture supports fine-grained, localized data movement and patch-level execution coordination across a mesh of processing elements to optimize compute reuse, operand locality, and execution throughput.

The present application discloses a sense-in-memory macrocell circuit, system, and analog-to-digital conversion method, including the steps: a tag module reads an analog signal from the iSC bus; the tag module traverses and compares the read analog signal with a plurality of reference analog signals; according to the comparison result, a corresponding digital signal is obtained; the plurality of reference analog signals are data that gradually increase or decrease according to a functional relationship. This method does not require a dedicated ADC circuit and utilizes the existing circuits of the PE to implement the conversion function.

The embodiment of the invention provides an integrated circuit and an operation method thereof. An integrated circuit may include a plurality of in-memory computing (CIM) circuits physically formed on a substrate. Each of the plurality of CIM circuits may include: an input circuit configured to receive a plurality of first data elements; a memory array coupled to the input circuit and configured to store the plurality of first data elements; a data multiplexer configured to output the plurality of first data elements through a first data path or through a second data path; and a plurality of arithmetic units coupled to the data multiplexer and configured to perform a multiply-accumulate (MAC) operation on the plurality of first data elements and the plurality of second data elements.

An in-memory computing (IMC) accelerator using a high-density operation circuit and a low-power sense amplifier as a peripheral circuit includes a plurality of dynamic random-access memory (DRAM) banks each including a pair of cell arrays, a data supply logic, a memory, and a controller for IMC, a global SRAM, and a top-level controller, wherein the cell array includes a plurality of subarrays, each of the subarrays includes a DRAM array including a big array and a little array, and an arithmetic circuit configured to perform an operation, and the arithmetic circuit includes a sense amplifier configured to amplify a bit line voltage difference, and a compact multiply-accumulate (MAC)-single instruction multiple data (SIMD) unit (CMSU) for an MAC operation and an SIMD operation, so that functionality of an in-memory operation is diversified.

Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a lookup table (LUT) according to a fused single instruction stream, multiple data stream (SIMD) instruction. The LUT may include segment entries corresponding to a result of evaluating a function using corresponding index values ​​representing an independent variable of the function. The index values ​​are used to map data sample values ​​in a data array configured to be interpolated to the segment entries.By using an iterative process of mapping data samples to valid segment entries contained in each LUT section, the architecture advantageously facilitates scaling to support larger LUTs and can thus be extended to enable linear interpolation on multiple dimensions.

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes: parsing sequential FHE logic gate code; transforming the FHE logic gate code into a set of code modules, each code module in the set of code modules having an input and an output that is a function of the input and not passing control to other functions; creating node wrappers around each code module; configuring at least one of the main processing cores to implement an equivalent logic element of each element in a streaming mode of operation, wherein a data stream flowing out of a corresponding arithmetic logic unit flows into main memory and into other arithmetic logic units among a plurality of arithmetic logic units.

An apparatus comprising: at least one processing element configured to process a data flow in at least one direction of a plurality of directions; a configuration register comprising at least one setting that determines the processing of the data flow with the at least one processing element; and a shift register configured to select data of the at least one processing element from the at least one direction, and to provide at least one shifted data sample to a plurality of slices configured to perform at least one arithmetic operation with the data flow; wherein at least one slice of the plurality of slices is configured with the at least one setting of the configuration register.