Parallel Array Architecture for a Graphics Processor

a graphics processor and parallel array technology, applied in the field of parallel array architecture for graphics processors, can solve the problems of increasing the load on the vertex shader core, reducing the memory locality, and reducing the efficiency of the graphics processing
US20070159488A1Inactive Publication Date: 2007-07-12NVIDIA CORP
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
NVIDIA CORP
Publication Date
2007-07-12
Estimated Expiration
Not applicable · inactive patent

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Abstract

A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. The pixel distribution logic selects one of the processing clusters to which the coverage data for a first pixel is delivered based at least in part on a location of the first pixel within an image area. The processing clusters can be mapped directly to the frame buffers partitions without a crossbar so that pixel data is delivered directly from the processing cluster to the appropriate frame buffer partitions. Alternatively, a crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions. The crossbar is configured such that pixel data generated by any one of the processing clusters is deliverable to any one of the frame buffer partitions.
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Description

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] The present application claims the benefit of U.S. Provisional Application No. 60 / 752,265, filed Dec. 19, 2005, which is incorporated herein by reference in its entirety for all purposes.

[0002] The present application is related to the following commonly-assigned co-pending U.S. patent applications: application Ser. No. 11 / 290,303, filed Nov. 29, 2005; application Ser. No. 11 / 289,828, filed Nov. 29, 2005; and application Ser. No. 11 / 311,993, filed Dec. 19, 2005, which are incorporated in their entirety, herein, by reference for all purposes.BACKGROUND OF THE INVENTION

[0003] The present invention relates in general to graphics processors, and in particular to a parallel array architecture for a graphics processor.

[0004] Parallel processing techniques enhance throughput of a processor or multiprocessor system when multiple independent computations need to be performed. A computation can be divided into tasks that are defined by progra...

Claims

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