473 results about "Processing core" patented technology

Systems and methods for distribution and management of certificates in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller includes firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device includes firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node of a plurality of nodes of a firmware framework; and where the orchestrator is configured to: store certificates in a local storage of the controller; and distribute one or more other certificates to one or more of the plurality of nodes within the firmware framework, without any involvement by any Operating System (OS) of the IHS.

An apparatus to facilitate hardware acceleration of resource barriers in a graphics environment is disclosed. The apparatus includes resource barrier hardware circuitry for processing cores and a graphics pipeline to: receive a resource barrier instruction to transition a resource utilized by the graphics pipeline from a first usage to a second usage; responsive to the resource barrier instruction, cause a draw group marker having a current draw group count to be sent to an end of the graphics pipeline to track completion of each stage of the graphics pipeline; increment the current draw group count to a new draw group count for each new draw group of the graphics pipeline; and determine that a current signal stage of the graphics pipeline is complete for a current draw group responsive to a done count for the current signal stage being less than or equal to the current draw group count.

The invention provides an instruction synchronization method and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips, and the method comprises the steps: after a processing core sends a calculation instruction, sending a barrier instruction with the same memory address, enabling the calculation instruction and the barrier instruction to enter a cache in an order-preserving manner, and guaranteeing that the cache receives the calculation instruction and achieves calculation; therefore, a large amount of memory fence operation is reduced, and the processing time delay of the memory access instruction is reduced. And for the plurality of processing cores bound with the same target barrier identifier, recording the number of synchronized instructions of the plurality of processing cores in real time. When the number of the synchronized instructions is equal to the expected synchronization number, returning a synchronization success message to the plurality of processing cores so as to realize instruction synchronization of the plurality of processing cores; in the process, each processing core does not need to circularly read the atomic accumulation result, so that the occupation of bandwidth resources such as bus bandwidth and direct interconnection bandwidth is greatly reduced, the instruction synchronization overhead is reduced, and the efficiency of the whole system is improved.

The invention discloses a traffic incident detector system based on a domestic intelligent DSP and a detection method. The system comprises a video acquisition unit, a data exchange and storage unit, an intelligent processing core and a communication interaction unit. The intelligent processing core adopts a heterogeneous SoC chip integrating a multi-core DSP, an NPU and an FFT hardware acceleration module, the FFT module is responsible for video frame frequency domain enhancement, the NPU runs a deep learning model to carry out target detection, and the multi-core DSP executes multi-target parallel tracking and event judgment. And the data exchange and storage unit supports direct carrying of data among the modules through a unified physical address space and a DMA mechanism. The method comprises the following steps: carrying out NPU target detection on a video subjected to environment self-adaptive preprocessing; a multi-core DSP is used for tracking a target in parallel and judging an event; and finally, alarm information is generated and reported. Through heterogeneous hardware division and software and hardware cooperation, high-real-time and high-precision edge analysis is realized, and the detection reliability is improved.

The invention provides a process reset processing method, a processor, a storage medium and a program product, and relates to the technical field of chip design, the method is applied to the processor comprising at least one processing core, and the processing core comprises a gateway module and a process management module. The method comprises the following steps: under the condition that a gateway module receives a first task request from a process management module, based on a process identifier carried by the first task request, determining a latest count value of a counter associated with the process management module, the counter is used for recording the accumulated number of times that the process borne by the process management module is triggered to reset; and in response to determining that the first count value carried by the first task request is inconsistent with the newest count value of the counter, executing an operation related to process reset on the first task request. The method can ensure that a single process can be effectively terminated, and process-level resetting is realized.

Techniques for optimizing distillation tile layouts for distillation tiles in a magic state factory of a quantum computer and a scheduling of distilled magic state production (e.g., using temporally encoded lattice surgery based (TELS-based) magic state distillation) using said distillation tiles are disclosed. Customized designs for distillation tile layouts that reduce space-time costs when executing a given quantum algorithm are presented, wherein the designs may be customized based, at least in part, on a selected classical error-correcting code and distillation circuit, on a decision whether to perform parallelized TELS-based magic state distillation, etc. Production of distilled magic states may then be configured using a round robin scheduling design in order to minimize potential time in which a processing core of the quantum computer is waiting for another newly distilled magic state from the magic state factory to use for logical computation related to the given quantum algorithm being executed.

The invention relates to the technical field of multi-core CPU task scheduling, and discloses a multi-core CPU task scheduling optimization method based on load balancing. The method comprises the following steps: continuously monitoring an output value of a load balancing indicator in a multi-core CPU task scheduler, and setting a current task distribution mode as reference task distribution when a system is balanced; collecting an instant load measurement value of each processing core, constructing a load distribution sequence, calculating a load deviation parameter distributed with a reference task, and determining a load imbalance degree and a skew core identifier; based on the state updating indicator output value, generating a task redistribution instruction to adjust the task distribution direction; and during task execution, task operation data associated with the unique identifier is collected in real time, and performance is evaluated and stored after segmentation processing according to categories. According to the method, accurate sensing and dynamic adjustment of the load state are realized, the task allocation logic is optimized, and the scheduling rationality and operation efficiency of the multi-core CPU are improved.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

The invention discloses a multi-head attention calculation task allocation method and related products, and the method is executed by a single processing core of an artificial intelligence processor, and is used for loading multi-head attention sequence interval calculation tasks allocated to the processing core. The sequence interval calculation task is obtained by dynamically splitting according to a comparison result of an actual calculation amount of a current processing core and a target calculation amount of each processing core, and the actual calculation amount of the current processing core is obtained by pre-estimating according to an input sequence of the multi-head attention calculation task and an action range of a causal mask; the target calculation amount refers to the average calculation amount of each processing core participating in the multi-head attention calculation task; and executing the sequence interval calculation task. According to the method, the calculation task is dynamically split according to the comparison result of the actual calculation amount of the current processing core and the target calculation amount of each processing core, so that overload of the processing cores is effectively prevented, and the problem that excessive tasks are allocated to any processing core to become a system bottleneck is avoided.

The invention discloses an electrical control device for high-pressure protection in a hydraulic control system, which relates to the technical field of hydraulic control and comprises a high-pressure detection module for monitoring pressure data of the hydraulic system in real time and transmitting the pressure data to a control processing core through an analog quantity input module. Two-channel independent control logic is adopted through the redundancy protection unit, even if a single loop breaks down, the other loop can still independently execute a safety instruction, the risk of single-point failure is eradicated, meanwhile, the intelligent control unit achieves advanced and accurate pressure adjustment and trend suppression through a high-frequency-response electro-hydraulic servo valve and a proportional valve and depending on bus communication, and the safety performance of the system is improved. The high-voltage risk is eliminated in the bud, the leap from passive response to active protection is achieved, high system integration and intelligent management are achieved through the intelligent valve terminal, remote monitoring and diagnosis are supported while wiring is simplified, and maintainability is enhanced.

The invention provides a synchronization signal processing method and an artificial intelligence chip. The synchronization signal processing method comprises the following steps: receiving a synchronization signal reading request with a prompt sign sent by a first processing core; confirming that the synchronization signal reading request is a synchronization operation according to the prompt sign; determining that storage addresses in an effective state exist, and determining whether a target storage address matched with the target program segment identifier and the target synchronous address identifier exists in the storage addresses in the effective state; if the target storage address exists, when the synchronization value in the target storage address is the same as the target synchronization value, returning a synchronization success message to the first processing core, and adjusting readable times in the target storage address; the time spent on reading the synchronizing signal is greatly shortened, the time is saved, the delay is reduced, and the processing efficiency of the processing core is improved; moreover, the bandwidth can be saved, the bandwidth waste is avoided, and the working efficiency of the whole system is improved.

The invention relates to an Imaging sensor device in a stacked arrangement comprising:a pixel array tier comprising a plurality of pixel segments each having a plurality of pixels for photon detection each providing a digital pixel output;a processing tier comprising a number of processing cores each associated with one of the plurality of pixel segments to receive the pixel outputs of the pixels of the respective pixel segment, wherein the processing cores are each in bidirectional communication with one or more neighboring processing cores,wherein the processing cores are each configured to receive pixel outputs of the pixels of the associated pixel segments and to distribute processing of pixel outputs between the processing core and the at least one of the neighboring processing cores as neighboring processing cores.

According to one example of the present disclosure, a system may be provided. The system may comprise at least one processing core configured to process computations of the at least one neural network model comprising at least one tensor, at least one memory circuit configured to store the at least one tensor, a bus circuit, electrically coupled to the at least one processing core and the at least one memory circuit, configured to transmit the at least one tensor based on a memory access operation instruction, and a controller configured to control a priority of a memory access operation for each tensor of the at least one processing core.

A system for managing cache coherency comprises memory areas, processing cores, cache nodes each associated with at least one of the processing cores, and a hardware processor configured to: for each of the memory areas: cluster the processing cores into clusters according to memory access metrics in relation to the memory area; and for each of the clusters, associate the memory area with a caching scheme; and configure the processing cores to: receive from a first core a memory access command comprising a memory address associated with a memory area, where the first core is a member of a first cluster for the memory area; compute a determination of a target cache node according to the memory access command, where the target cache node is associated with a second core; and access the memory area according to the caching scheme associated with the memory area for the first cluster.

A data input sub-system of a parallelized database system includes processing core resources operable to obtain divisions of data slabs of a dataset and compress the divisions of data slabs using a null elimination compression scheme to produce divisions of compressed data slabs, A first data slab of a first division of data slabs of the divisions of data slabs is compressed using the null elimination compression scheme to produce a first compressed data slab. The first compressed data slab includes first compressed data and first compression information. The processing core resources are further operable to store a respective division of compressed data slabs of the divisions of compressed data slabs.

The embodiment of the invention relates to an image processing method and device and a medium. The method proposed herein includes: generating, by a graphics processing unit, a first reference frame, a second reference frame, and motion vector information corresponding to the first reference frame; transmitting the motion vector information to a digital signal processor by a graphic processing unit; the digital signal processor divides the motion vector information into a plurality of groups; processing the plurality of groups in parallel by using a plurality of processing cores of the digital signal processor, each processing core being configured to: write a group of motion vectors indicated by a corresponding group to a group of projection positions of the group of motion vectors in the interpolated frame by using a scatter instruction; respectively reading source pixel information from the first reference frame and the second reference frame based on the written group of motion vectors by utilizing a collection instruction; the source pixel information is fused by a digital signal processor to generate an interpolated frame. In this way, according to the embodiment of the invention, the generation efficiency of the interpolation frame can be effectively improved.

An integrated circuit (IC) is disclosed. In one embodiment, the IC comprises a memory and at least one processing core coupled to the memory. In one embodiment, the operations the at least one processing core operatively coupled to the memory perform comprise storing final hashes of each block chain authentication (BCA) section of an in-system test (IST) image in a write-protected portion of the memory; receiving at least one Public Key Authentication (PKA) signature; authenticating the at least one PKA signature using public key cryptography (PKC) algorithm; once the PKA signature is authenticated, using the final hash for each BCA section to authenticate a portion of the IST image associated with each BCA section using a hash engine of the at least one processing core skipping any PKA signature checks for any of the final hashes; and testing portions of the IC with the authenticated IST image portion.

A system for real-time prediction of heart disease and to support clinical decisions; the system includes: a patient data acquisition module configured to receive multimodal inputs, including physiological signals selected from electrocardiographic waveforms, blood pressure readings, heart rate readings, and oxygen saturation readings, as well as demographic and lifestyle information, including age, gender, cholesterol levels, smoking habits, and family medical history; a preprocessing engine configured to perform data cleansing, imputation of missing values, categorical coding, and feature scaling, so that the input data is normalized and converted into a format suitable for machine learning; a processing core comprising a multi-core CPU / GPU system-on-chip operationally coupled with a secure storage unit, wherein the processing core is configured to execute a variety of pre-trained machine learning models, including Naive Bayes, Random Forest, Logistic Regression and Decision Tree classifiers; a model evaluation unit configured to calculate validation metrics such as precision, recall, F1 score and area under the curve for each of the models and dynamically select the model with optimal performance to generate real-time predictions for the risk of heart disease; a display interface configured to present predictive results in the form of risk probability values, confidence indices, and actionable recommendations that are mapped to clinical treatment guidelines; and a communication interface configured to transmit emergency alerts based on high-risk predictions to remote caregivers, hospitals, and emergency response systems via wireless communication protocols such as WLAN, Bluetooth, and 4G / 5G cellular connections.

This application is directed to resource management in a storage system that includes a non-volatile memory and a collection of resources having one or more processing cores. The storage system allocates a first subset of resources to process queues of I / O access operations requested by a host device. The first subset of resources includes a storage controller corresponding to a subset of processing cores. The storage system obtains a first request for adjusting resource allocation of the storage device, and the first request includes a target performance requirement for processing the queues of I / O access operations. The storage system determines that the target performance requirement can be satisfied by allocation of at least a target subset of resources. In response to the first request and based on the target subset of resources, a second subset of resources is allocated for processing the one or more queues of I / O access operations.

Datacenter workloads demand flexible memory architectures spanning from rack-level to pod-scale deployments. Embodiments herein disclose systems enabling CXL memory semantics over physical layers based on IEEE 802.3 PMA, facilitating memory disaggregation across datacenter fabric infrastructures. The embodiments comprise processing cores with coherent interconnects, MMUs for address translation, and memory channels supporting substantial memory capacities. Resource Provisioning Units (RPUs) translate between CXL data, optionally encapsulated, transmitted via physical layers based on IEEE 802.3 PMA, and CXL requests, enabling external entities to access memory across different physical address spaces. This architecture provides memory pooling using datacenter network infrastructure, supporting intra-rack memory sharing, inter-pod memory access, distributed AI training across datacenter resources, and elastic memory provisioning for cloud-native applications, overcoming physical layer limitations of traditional CXL implementations while maintaining protocol coherency suitable for GenAL, LLM inference, and HPC workloads.

The invention discloses a semantic understanding method and engine based on multi-model collaborative reasoning and self-supervised learning, and belongs to the technical field of natural language processing and artificial intelligence. The method comprises the following steps: preprocessing input data to extract semantic features; at least two models are intelligently scheduled from a large language model, a task type model and a rule engine for collaborative reasoning through a dynamic routing module based on a multi-level strategy and a meta-learning network; performing hierarchical fusion and conflict resolution on the reasoning result by using a multi-model fusion module, and outputting a final semantic understanding result; and continuous optimization of the system is realized through feedback learning. Universal semantic representation is learned by using unlabeled data through a self-supervised pre-training task, so that the generalization ability of the model is enhanced. The engine comprises an input processing core module, a dynamic routing core module, a multi-model fusion core module, a feedback learning core module, a model warehouse core module, a monitoring security core module and the like so as to collaboratively realize the method. According to the method, high-precision and high-efficiency semantic understanding with self-adaptive capability is realized.

The application relates to a high-speed encryption and decryption engine and an encryption and decryption implementation method, wherein a plurality of physical channels are provided to provide a plurality of service processing modules with cryptographic services, the problem that a cryptographic card can only provide a single service channel is solved, secondary keys are imported into an FPGA chip for buffering, a session key is managed in a life cycle by the FPGA chip, the time cost of key updating required by cryptographic operation can be reduced, and the processing delay of the cryptographic service can be obviously reduced; the FPGA chip is used as a cryptographic operation processing core unit, multi-stage parallel pipeline processing is realized, and the processing performance is effectively improved.

The invention relates to an intelligent control method and system based on multi-protocol task scheduling and a medium. The intelligent control method comprises the steps that original instruction data input by a user is received and subjected to semantic analysis, instruction keywords are extracted, and a structured instruction data packet is generated; converting the structured instruction data packet into a multi-protocol connection service calling parameter, and sending the multi-protocol connection service calling parameter to a multi-protocol connection service processing core through an internal communication interface; the multi-protocol connection service processing core schedules a corresponding execution unit to execute the operation instruction set according to the target system identifier, and generates operation result data corresponding to the task type identifier; performing state analysis on the operation result data to generate decision instruction data containing a decision type identifier; and executing task refinement processing, abnormal alternative scheme generation or task completion feedback processing based on the decision type identifier, and converting a processing result into natural language feedback output. According to the invention, unified coordination and autonomous operation of the heterogeneous intelligent system in the home environment are realized.

A communication system couples a plurality of processing cores together, each having an associated register storing a virtual machine ID, which is inserted into requests sent by the respective processing core. A master circuit has associated a master interface circuit, wherein the master interface circuit has associated register for storing a second virtual machine ID, which is inserted into requests sent by the master circuit. A slave circuit has associated a slave interface circuit configured to selectively forward read or write requests addressed to an address sub-range. The slave interface circuit has associated a third register storing a third virtual machine ID associated with the address sub-range and is configured to receive a request addressed to the address sub-range, extract from the request a virtual machine ID, determine whether the extracted virtual machine ID corresponds to the third virtual machine ID, and then either forwards or rejects the request.

The invention relates to the technical field of artificial intelligence and medical health, in particular to an intelligent medical auxiliary system based on multi-model driving and multi-knowledge-base collaboration, and the system comprises an input layer which is used for receiving a query request submitted by a user in the forms of texts, voices and images; the data storage layer comprises a structured knowledge base, and the data storage layer is used for storing disease knowledge data; the processing core layer is used for receiving a query request, selecting a processing flow according to the query request, and generating a response text and interaction feedback in combination with the data stored in the data storage layer; and the output layer is used for outputting a query result which comprises a response text, an original text source of a retrieval basis and interactive feedback of a training link. The system has the capability of integrating texts, voices and images, creatively adopts a multi-knowledge-base RAG architecture oriented to special injury treatment and daily diseases, can provide professional medical auxiliary services in an off-network environment, and meets high-safety scene requirements.

The invention relates to the technical field of vehicle part strength simulation analysis verification, and discloses a strength load processing method and system based on a virtual test field, and the system comprises a model construction module, a data configuration module, a simulation execution module, a load processing core module, and a finite element interface module. The method comprises the following steps: constructing a virtual test field pavement model and a multi-body dynamic model; calling a programming tool to process the file; further converting the sub-working-condition load into a standardized load header file required by finite element strength analysis, and finally driving a finite element solver to execute batch working condition calculation and output stress-strain summarized data of the parts. According to the method, intelligent normalization processing of load data, dynamic coverage of critical working conditions and multi-system seamless integration are achieved, the efficiency and precision of component strength verification are improved, the development period is shortened, and a unified comparability reference is provided for fatigue life evaluation.

A processing system including processing cores, a shared memory, a shift table that stores a maximum number of reservations to locations in the memory, and an exclusive monitor that uses the shift table and an eviction policy to enforce core synchronization. The eviction policy is based on priority, age of valid reservations, shift table fullness state, and reservation memory conflict. The shift table may include a memory address and a size value indicative of a flexible amount of reserved memory at the memory address. The exclusive monitor evicts an oldest reservation in the shift table having a same or lower priority level as the new reservation. The exclusive monitor rejects the new reservation when the shift table is full of higher priority reservations. Reservations are shifted to maintain age status. Stale reservations may be invalidated or have their priority lowered. Conflicting reservations may be made with the same priority level.

The invention relates to the technical field of laser intelligent manufacturing, and discloses a laser cladding and cutting combined machining system based on machine learning, which comprises three core units, namely a multi-mode sensing core unit, a central processing core unit and a laser machining execution core unit. The multi-mode sensing unit integrates a scanning galvanometer type thermal infrared imager and a non-contact ultrasonic transducer array, and synchronously collects a surface temperature field and internal acoustic impedance. An acoustic-thermal correlation health model is arranged in the central processing unit, and internal hidden defects are identified on line by comparing health acoustic characteristics predicted by real-time temperature with a measured value. Therefore, the feed-forward parameter planning module fuses the physical state field and the defect identification result, dynamically plans and outputs an optimal process parameter sequence, and drives a laser processing execution unit to complete adaptive processing. According to the method, closed-loop self-adaptive regulation and control are realized through acoustic-thermal multi-mode information fusion and feedforward control, formation of internal defects can be effectively predicted and inhibited, and the quality, consistency and reliability of processed finished products are remarkably improved.

This invention provides a VBA-based method for calculating the helix parameters of a cylindrical battery, comprising: establishing a VBA data processing module; and performing calculations according to the following steps: S1: running and initializing the VBA tool; S2: building an interface module to create an interface for solving the helix parameters of the cylindrical battery; S3: inputting and reading data through a data input and preliminary data processing module; S4: performing calculations based on the data input in step S3; S5: storing and outputting the arc length and theta data calculated by the core calculation module in step S4 through a drawing and data generation module; S6: exporting the data stored in step S5 to a new worksheet through a data export module. This method can greatly simplify the engineer's workflow, reduce experimental costs, shorten the R&D cycle, quickly evaluate cell design schemes, assist engineers in effectively evaluating cell designs, and improve efficiency in the cylindrical battery manufacturing process.

A computing device and a method for encoding video at a computing device is provided. The computing device comprises memory, an image signal processor in communication with the memory and an encoder. The image signal processor is configured to convert data of images of a video stream as part of image sensor processing pipeline; and for an image of the video stream, pre-analyze, as part of the image sensor processing pipeline, converted data of one or more images of the video stream prior to encoding the frame. The encoder is configured to encode images of the video stream using information resulting from the pre-encoding analysis of the converted data. The encoded images are decoded and displayed.