716 results about "Processing core" patented technology

The invention provides a cross-platform education data privacy protection analysis system, and relates to the technical field of data privacy protection. The cross-platform education data privacy protection analysis system comprises a multi-modal data acquisition unit, a dynamic privacy analysis engine, a federal learning processing core module, a block chain enhanced access control system, a privacy watermark traceability module and a compliance autonomy unit. Dynamic coupling of scene sensitivity and data protection intensity is realized through a dynamic privacy risk scoring equation and an adaptive differential privacy noise equation; the problems of privacy disclosure, compliance verification and traceability and responsibility investigation in cross-platform education data sharing are solved by combining federal learning, block chain evidence storage and privacy watermarking technologies. According to the method, the privacy risk assessment precision is remarkably improved, the model precision loss is reduced, full-life-cycle data security management and control are supported, and the method is suitable for multiple scenes such as K12 education and college educational administration.

The invention relates to a brain inspired data service system and a brain inspired data service method, which are characterized in that a layered architecture is constructed, the layered architecture comprises a data node cluster deployed in a mixed manner, the data node cluster specifically comprises a core node, an acquisition node and a gateway node, and the core node, the acquisition node and the gateway node are respectively used for processing core service data, real-time edge data and cross-domain connection; the small-world connection layer realizes same-domain efficient communication through high-clustering local connection, and breaks a data island through dynamic long-range cross-domain connection; the intelligent control layer integrates a DMN control center, a collaborative state monitoring engine, a prediction analysis module and a reinforcement learning driven resource scheduler. The system initializes a topological structure through a small-world network manager, and when the communication frequency of a cross-domain node exceeds a threshold value, long-range connection is dynamically inserted to ensure that the hop count of a cross-domain path is stably not higher than a preset value. The DMN control center realizes dual-mode switching based on a system load threshold; in an idle period, data pre-cleaning, knowledge graph construction, predictive pre-fetching and resource pre-allocation are executed; and optimizing routing in combination with a graph traversal algorithm in a task period.

The invention provides a priority resetting method of a cache line and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips, the method comprises the following steps: detecting that a cache group contains a cache line of a first priority state (namely, the priority is greater than a preset level), and in addition, detecting that the cache group contains the cache line of the first priority state (namely, the priority is greater than the preset level); detecting a request state between the processing core and the cache when the target duration (namely the interval duration from the previous access of the data request carrying the priority prompt to the cache group) is greater than the preset duration; when the request state is that the data request sent by the processing core is not detected, spontaneously initiating a priority resetting process, and adjusting the priority of the cache line in the first priority state in the cache group to a preset level; in this way, hardware can automatically reset the priority of the cache line, the situation that the cache line with the high priority occupies the cache space for a long time is avoided, the cache space reserved for non-important data access is improved, the overall performance of the cache is improved, and meanwhile processing of a data request (normal access) of a processing core is not affected.

Systems and methods for capabilities and interfaces in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node, and where each node is configured to communicate, to the orchestrator, one or more exposed capabilities and one or more exposed interfaces usable to access the one or more exposed capabilities without any involvement by any Operating System (OS) of the IHS.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

The invention discloses an engineering design document compliance inspection method, electronic equipment and a storage medium, and the method is based on an OCR and a large language model, and comprises the following steps: standardizing the character recognition and extraction of a document; standardizing character error check and manual correction of the text; performing structured processing on the corrected standard text; vectorization processing of core text content and construction of a standard query system; presetting a specification set range corresponding to each chapter of the design document; carrying out vectorization and similarity query on characters selected by a user in the text editor; corresponding standard content is provided for the user; the method can improve the efficiency and accuracy of specification reference in the document, facilitates the dynamic update management of specification contents, and facilitates the guarantee of the correctness of reference specifications.

Systems and methods for runtime selection and distribution of modules in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where the orchestrator is configured to distribute a firmware module to a given node in response to a determination that the given node requires the firmware module to provide a capability, without any involvement by any Operating System (OS) of the IHS.

Systems and methods for discovery in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node, and where the nodes are configured to communicate with the orchestrator within a firmware framework without any involvement by any Operating System (OS).

The invention provides a rendering task allocation method and device, electronic equipment and a storage medium, the method is applied to a processing core of graphic processing equipment, the processing core comprises a plurality of computing unit clusters, and the method comprises the following steps: establishing a first rendering task of a first block according to primitive set information of the first block to be rendered in a rendering object; respectively determining task load values and task load levels of the plurality of computing unit clusters according to a set task distribution mode; determining a target computing unit cluster from the plurality of computing unit clusters according to the task load levels of the plurality of computing unit clusters; and sending the first rendering task to a task queue of the target computing unit cluster, so that the target computing unit cluster executes the first rendering task. According to the embodiment of the invention, the load balance of computing resources can be improved, and the utilization rate of the computing resources is improved.

The invention provides a task allocation method and device, electronic equipment and a storage medium, the method is applied to a processing core of graphic processing equipment, the processing core comprises a plurality of computing unit clusters, and the method comprises the following steps: under the condition that primitive set information of a to-be-rendered first block in a rendering object is obtained, the to-be-rendered first block in the rendering object is obtained; establishing a first rendering task of the first image block; according to a set task allocation mode, acquiring allocated task information of the plurality of computing unit clusters corresponding to the task allocation mode; determining a target computing unit cluster from the plurality of computing unit clusters according to the allocated task information; and sending the first rendering task to a task queue of the target computing unit cluster, so that the target computing unit cluster executes the first rendering task. According to the embodiment of the invention, the load balance of computing resources can be improved, and the utilization rate of the computing resources is improved.

The invention relates to a processor and a kernel synchronization method for the processor. Based on the method and the device, the query request initiated by the plurality of processing cores in the processor for the same specified data can be selectively forwarded by the route, so that the occupation of the query request on the on-chip bandwidth of the processor can be reduced, and the query response occupying the on-chip bandwidth of the processor can be indirectly reduced. Or, the data cache unit where the specified data is located can reduce the generation of the query response for promoting the processing kernel to continue to initiate the query request, so that not only can the occupation of the query response to the on-chip bandwidth of the processor be reduced, but also the query request occupying the on-chip bandwidth of the processor can be indirectly reduced. Therefore, the occupation of the query request and the query response for realizing kernel synchronization on the on-chip bandwidth of the processor can be inhibited from the routing forwarding source of the query request or the generation source of the query response, so that the on-chip bandwidth occupied by the kernel synchronization in the processor can be reduced.

Systems and methods for servicing nodes participating in inter-node communications in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where the orchestrator is configured to service a first node in communication with a second node without any involvement by any Operating System (OS) of the IHS.

Systems and methods for distribution and management of certificates in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller includes firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device includes firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node of a plurality of nodes of a firmware framework; and where the orchestrator is configured to: store certificates in a local storage of the controller; and distribute one or more other certificates to one or more of the plurality of nodes within the firmware framework, without any involvement by any Operating System (OS) of the IHS.

Systems and methods for secure communications in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, wherein the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where a given node is configured to communicate with the orchestrator, at least in part, using a security service of the firmware framework without any involvement by any Operating System (OS) of the IHS.

An apparatus to facilitate hardware acceleration of resource barriers in a graphics environment is disclosed. The apparatus includes resource barrier hardware circuitry for processing cores and a graphics pipeline to: receive a resource barrier instruction to transition a resource utilized by the graphics pipeline from a first usage to a second usage; responsive to the resource barrier instruction, cause a draw group marker having a current draw group count to be sent to an end of the graphics pipeline to track completion of each stage of the graphics pipeline; increment the current draw group count to a new draw group count for each new draw group of the graphics pipeline; and determine that a current signal stage of the graphics pipeline is complete for a current draw group responsive to a done count for the current signal stage being less than or equal to the current draw group count.

Systems and methods for diagnostics in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where the orchestrator is configured to trigger a diagnostics operation by a selected node to be performed independently of any Operating System (OS) of the IHS.

The invention provides a network card drive optimization method and device, equipment and a storage medium, and the method comprises the steps: resetting a throttling counter in a drive interrupt path according to an interrupt merging factor and a throttling parameter of a hardware interrupt response determined by an interrupt behavior state model, and generating a merging control strategy; polling and reading the use state of the buffer area according to the combination control strategy, and updating an interrupt response state table; and determining an optimal interrupt processing core set according to the interrupt response state table and the original operation data, generating an interrupt affinity mapping strategy, grouping the to-be-processed data packets of the receiving queue, and performing batch scheduling on the soft interrupt threads of the corresponding groups based on different soft interrupt priority levels of each group. According to the scheme, the interrupt processing core is selected by constructing the dynamic interrupt affinity mapping strategy, adaptive allocation of interrupt scheduling is achieved, resource idling and core migration expenses are reduced, and the interrupt processing efficiency and the resource utilization rate of the multi-core processor are effectively improved.

The invention provides an instruction synchronization method and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips, and the method comprises the steps: after a processing core sends a calculation instruction, sending a barrier instruction with the same memory address, enabling the calculation instruction and the barrier instruction to enter a cache in an order-preserving manner, and guaranteeing that the cache receives the calculation instruction and achieves calculation; therefore, a large amount of memory fence operation is reduced, and the processing time delay of the memory access instruction is reduced. And for the plurality of processing cores bound with the same target barrier identifier, recording the number of synchronized instructions of the plurality of processing cores in real time. When the number of the synchronized instructions is equal to the expected synchronization number, returning a synchronization success message to the plurality of processing cores so as to realize instruction synchronization of the plurality of processing cores; in the process, each processing core does not need to circularly read the atomic accumulation result, so that the occupation of bandwidth resources such as bus bandwidth and direct interconnection bandwidth is greatly reduced, the instruction synchronization overhead is reduced, and the efficiency of the whole system is improved.

The invention discloses a traffic incident detector system based on a domestic intelligent DSP and a detection method. The system comprises a video acquisition unit, a data exchange and storage unit, an intelligent processing core and a communication interaction unit. The intelligent processing core adopts a heterogeneous SoC chip integrating a multi-core DSP, an NPU and an FFT hardware acceleration module, the FFT module is responsible for video frame frequency domain enhancement, the NPU runs a deep learning model to carry out target detection, and the multi-core DSP executes multi-target parallel tracking and event judgment. And the data exchange and storage unit supports direct carrying of data among the modules through a unified physical address space and a DMA mechanism. The method comprises the following steps: carrying out NPU target detection on a video subjected to environment self-adaptive preprocessing; a multi-core DSP is used for tracking a target in parallel and judging an event; and finally, alarm information is generated and reported. Through heterogeneous hardware division and software and hardware cooperation, high-real-time and high-precision edge analysis is realized, and the detection reliability is improved.

Systems and methods for telemetry in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where at least a given node is configured to communicate, to the orchestrator, telemetry data without any involvement by any Operating System (OS) of the IHS.

Systems and methods for Operating System (OS) discovery of, and interaction with, firmware framework devices. In some embodiments, an Information Handling System (IHS) may include one or more processors; a memory coupled to the one or more processors, where the memory includes program instructions that, upon execution by the one or more processors, cause the one or more processors to instantiate an OS; a controller, where the controller includes firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device includes firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node, where the nodes are configured to communicate with the orchestrator within a firmware framework without any involvement by the OS, and where the nodes and orchestrator are further configured to communicate with the OS.

The invention provides a process reset processing method, a processor, a storage medium and a program product, and relates to the technical field of chip design, the method is applied to the processor comprising at least one processing core, and the processing core comprises a gateway module and a process management module. The method comprises the following steps: under the condition that a gateway module receives a first task request from a process management module, based on a process identifier carried by the first task request, determining a latest count value of a counter associated with the process management module, the counter is used for recording the accumulated number of times that the process borne by the process management module is triggered to reset; and in response to determining that the first count value carried by the first task request is inconsistent with the newest count value of the counter, executing an operation related to process reset on the first task request. The method can ensure that a single process can be effectively terminated, and process-level resetting is realized.

Systems and methods for Best Known Configuration (BKC) of nodes in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator, and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where the orchestrator is configured to apply a BKC to the plurality of nodes.

Techniques for optimizing distillation tile layouts for distillation tiles in a magic state factory of a quantum computer and a scheduling of distilled magic state production (e.g., using temporally encoded lattice surgery based (TELS-based) magic state distillation) using said distillation tiles are disclosed. Customized designs for distillation tile layouts that reduce space-time costs when executing a given quantum algorithm are presented, wherein the designs may be customized based, at least in part, on a selected classical error-correcting code and distillation circuit, on a decision whether to perform parallelized TELS-based magic state distillation, etc. Production of distilled magic states may then be configured using a round robin scheduling design in order to minimize potential time in which a processing core of the quantum computer is waiting for another newly distilled magic state from the magic state factory to use for logical computation related to the given quantum algorithm being executed.

The invention relates to the technical field of multi-core CPU task scheduling, and discloses a multi-core CPU task scheduling optimization method based on load balancing. The method comprises the following steps: continuously monitoring an output value of a load balancing indicator in a multi-core CPU task scheduler, and setting a current task distribution mode as reference task distribution when a system is balanced; collecting an instant load measurement value of each processing core, constructing a load distribution sequence, calculating a load deviation parameter distributed with a reference task, and determining a load imbalance degree and a skew core identifier; based on the state updating indicator output value, generating a task redistribution instruction to adjust the task distribution direction; and during task execution, task operation data associated with the unique identifier is collected in real time, and performance is evaluated and stored after segmentation processing according to categories. According to the method, accurate sensing and dynamic adjustment of the load state are realized, the task allocation logic is optimized, and the scheduling rationality and operation efficiency of the multi-core CPU are improved.

Systems and methods for license distribution and management in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller includes firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device includes firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node of a plurality of nodes, and where the orchestrator is configured to obtain and distribute licenses to one or more of the plurality of nodes within a firmware framework, without any involvement by any Operating System (OS) of the IHS.

Systems and methods for distribution and management of certificates in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller includes firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device includes firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node of a plurality of nodes of a firmware framework; and where the orchestrator is configured to: store certificates in a local storage of the controller; and distribute one or more other certificates to one or more of the plurality of nodes within the firmware framework, without any involvement by any Operating System (OS) of the IHS.

The invention provides a cache-based asynchronous direct writing method and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips, the method comprises the following steps: detecting respective status bits of a plurality of cache groups in a cache; when the status bit of the cache group indicates that a cache line meeting a preset condition exists in the cache group, the link state between the cache and the main memory is detected, and the preset condition is that refreshing prompt information is contained and the state is marked as a dirty state; and when the link state is an idle state and the data request of the processing core is not received, the cache lines meeting a preset condition in the cache group are evicted to the main memory. When the link between the cache and the main memory is idle, the cache line which contains the refresh prompt information and is marked as a dirty state is timely evicted into the main memory, so that the interconnection bus bandwidth between the cache and the main memory is in a dynamic balance state, the interconnection bus bandwidth between the cache and the main memory is fully utilized, and the interconnection bus bandwidth between the cache and the main memory is not influenced. And meanwhile, the excessive pressure of the interconnection bus bandwidth between the cache and the main memory is avoided.

The invention discloses a data loading device and electronic equipment. The data loading device comprises a crossbar switch circuit and N storage units in a storage part, wherein N is a positive integer greater than 1; the storage component is configured to store data; the crossbar switch circuit is configured to load the data in the storage component to the corresponding processing core for calculation or processing; the crossbar switch circuit comprises N demultiplexers and N multiplexers; wherein the N storage units are configured to send request data to the multiplexers coupled with the N storage units in sequence according to the same preset return sequence; each demultiplexer is also provided with N first-in first-out cache modules in one-to-one correspondence with the N processing cores, and each first-in first-out cache module is configured to cache data information of each data packet sent by a storage unit coupled with the demultiplexer according to a receiving sequence. The data loading device can effectively relieve the arbitration conflict that a plurality of storage units return to the same processing core at the same moment, and the data transmission performance is effectively improved.

The invention discloses a multi-head attention calculation task allocation method and related products, and the method is executed by a single processing core of an artificial intelligence processor, and is used for loading multi-head attention sequence interval calculation tasks allocated to the processing core. The sequence interval calculation task is obtained by dynamically splitting according to a comparison result of an actual calculation amount of a current processing core and a target calculation amount of each processing core, and the actual calculation amount of the current processing core is obtained by pre-estimating according to an input sequence of the multi-head attention calculation task and an action range of a causal mask; the target calculation amount refers to the average calculation amount of each processing core participating in the multi-head attention calculation task; and executing the sequence interval calculation task. According to the method, the calculation task is dynamically split according to the comparison result of the actual calculation amount of the current processing core and the target calculation amount of each processing core, so that overload of the processing cores is effectively prevented, and the problem that excessive tasks are allocated to any processing core to become a system bottleneck is avoided.