1081 results about "Processing core" patented technology

A new system architecture for servers used in supercomputers uses an on-chip switch fabric with backpressure to improve performance. A server-on-a-chip includes one or more of the on-chip switch fabrics coupling one or more processing cores enabled to respond to the backpressure. Optionally, one or more ports of the on-chip switch fabrics are used to provide (external) ports of the server-on-a-chip to enable seamless communication with other server-on-a-chip instances. Various instances of the server-on-a-chip use the seamless communication to communicate with each other over a single printed circuit board and / or with each other across a plurality of printed circuit boards. Optional smart memory and / or multi-homed memory techniques improve memory efficiency by posting all writes, hiding DRAM maintenance operations (e.g., refresh, scrubbing, error correction and / or error logging), and / or reducing attack vectors, such as via secure booting of encrypted boot images.

The invention provides a cross-platform education data privacy protection analysis system, and relates to the technical field of data privacy protection. The cross-platform education data privacy protection analysis system comprises a multi-modal data acquisition unit, a dynamic privacy analysis engine, a federal learning processing core module, a block chain enhanced access control system, a privacy watermark traceability module and a compliance autonomy unit. Dynamic coupling of scene sensitivity and data protection intensity is realized through a dynamic privacy risk scoring equation and an adaptive differential privacy noise equation; the problems of privacy disclosure, compliance verification and traceability and responsibility investigation in cross-platform education data sharing are solved by combining federal learning, block chain evidence storage and privacy watermarking technologies. According to the method, the privacy risk assessment precision is remarkably improved, the model precision loss is reduced, full-life-cycle data security management and control are supported, and the method is suitable for multiple scenes such as K12 education and college educational administration.

The invention relates to a brain inspired data service system and a brain inspired data service method, which are characterized in that a layered architecture is constructed, the layered architecture comprises a data node cluster deployed in a mixed manner, the data node cluster specifically comprises a core node, an acquisition node and a gateway node, and the core node, the acquisition node and the gateway node are respectively used for processing core service data, real-time edge data and cross-domain connection; the small-world connection layer realizes same-domain efficient communication through high-clustering local connection, and breaks a data island through dynamic long-range cross-domain connection; the intelligent control layer integrates a DMN control center, a collaborative state monitoring engine, a prediction analysis module and a reinforcement learning driven resource scheduler. The system initializes a topological structure through a small-world network manager, and when the communication frequency of a cross-domain node exceeds a threshold value, long-range connection is dynamically inserted to ensure that the hop count of a cross-domain path is stably not higher than a preset value. The DMN control center realizes dual-mode switching based on a system load threshold; in an idle period, data pre-cleaning, knowledge graph construction, predictive pre-fetching and resource pre-allocation are executed; and optimizing routing in combination with a graph traversal algorithm in a task period.

The invention provides a priority resetting method of a cache line and an artificial intelligence chip, and relates to the technical field of artificial intelligence chips, the method comprises the following steps: detecting that a cache group contains a cache line of a first priority state (namely, the priority is greater than a preset level), and in addition, detecting that the cache group contains the cache line of the first priority state (namely, the priority is greater than the preset level); detecting a request state between the processing core and the cache when the target duration (namely the interval duration from the previous access of the data request carrying the priority prompt to the cache group) is greater than the preset duration; when the request state is that the data request sent by the processing core is not detected, spontaneously initiating a priority resetting process, and adjusting the priority of the cache line in the first priority state in the cache group to a preset level; in this way, hardware can automatically reset the priority of the cache line, the situation that the cache line with the high priority occupies the cache space for a long time is avoided, the cache space reserved for non-important data access is improved, the overall performance of the cache is improved, and meanwhile processing of a data request (normal access) of a processing core is not affected.

The invention discloses a real-time simulation performance evaluation method based on an ARMv8 architecture multi-core processor, and particularly relates to the technical field of multi-core performance evaluation. Comprising the following steps that a concurrent monitoring module is arranged, and an access instruction sequence and memory barrier instruction information of a processing core are collected; analyzing an address cross relation and time sequence dependence between the access instructions, and generating an instruction rearrangement risk access group; concurrency consistency analysis is carried out on the risk access group, race conditions are identified, and a synchronization mode and memory barrier instruction distribution are recorded; high-intensity concurrent operation is injected into the simulation environment, read-write operation of the shared variables is continuously tracked, and an instruction execution sequence is analyzed; the matching degree under different simulation load conditions is counted, a real-time simulation performance evaluation index for the weak memory model is generated, and the potential consistency problem caused by instruction rearrangement can be accurately recognized.

Systems and methods for capabilities and interfaces in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node, and where each node is configured to communicate, to the orchestrator, one or more exposed capabilities and one or more exposed interfaces usable to access the one or more exposed capabilities without any involvement by any Operating System (OS) of the IHS.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

The embodiment of the invention provides a multi-core network-on-chip transaction processing system, method, device, medium and product, the multi-core network-on-chip transaction processing system comprises a plurality of clusters, each cluster comprises four processing cores, a slave node and a master node, each processing core is provided with a cache, each slave node is provided with a slave node, and each slave node is provided with a slave node; the slave node is provided with a private cache, and the slave node comprises a four-stage pipeline architecture; the slave node is used for processing a request transaction through the four-stage pipeline architecture and generating a target response message or target response message data under the condition that the request transaction is received, and the four-stage pipeline architecture is constructed based on different clock periods and is used for periodically processing the request transaction.

The invention discloses an engineering design document compliance inspection method, electronic equipment and a storage medium, and the method is based on an OCR and a large language model, and comprises the following steps: standardizing the character recognition and extraction of a document; standardizing character error check and manual correction of the text; performing structured processing on the corrected standard text; vectorization processing of core text content and construction of a standard query system; presetting a specification set range corresponding to each chapter of the design document; carrying out vectorization and similarity query on characters selected by a user in the text editor; corresponding standard content is provided for the user; the method can improve the efficiency and accuracy of specification reference in the document, facilitates the dynamic update management of specification contents, and facilitates the guarantee of the correctness of reference specifications.

Systems and methods for runtime selection and distribution of modules in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where the orchestrator is configured to distribute a firmware module to a given node in response to a determination that the given node requires the firmware module to provide a capability, without any involvement by any Operating System (OS) of the IHS.

Apparatuses, systems, and techniques to perform neural networks. In at least one embodiment, a processor is to cause information to be distributed to processing cores. In at least one embodiment, a processor is to cause inferencing of two or more contiguous portions of information to be distributed between two or more respective processing cores based, at least in part, on locations of the two or more contiguous portions within the information relative to one or more terminating portions of the information.

Systems and methods for discovery in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node, and where the nodes are configured to communicate with the orchestrator within a firmware framework without any involvement by any Operating System (OS).

The invention provides a rendering task allocation method and device, electronic equipment and a storage medium, the method is applied to a processing core of graphic processing equipment, the processing core comprises a plurality of computing unit clusters, and the method comprises the following steps: establishing a first rendering task of a first block according to primitive set information of the first block to be rendered in a rendering object; respectively determining task load values and task load levels of the plurality of computing unit clusters according to a set task distribution mode; determining a target computing unit cluster from the plurality of computing unit clusters according to the task load levels of the plurality of computing unit clusters; and sending the first rendering task to a task queue of the target computing unit cluster, so that the target computing unit cluster executes the first rendering task. According to the embodiment of the invention, the load balance of computing resources can be improved, and the utilization rate of the computing resources is improved.

The invention provides a core photograph processing method based on perspective transformation and a graphical user interface. The core photograph processing method comprises the following steps: S1, collecting a high-definition core photograph; s2, establishing a graphical user interface; s3, defining and designing a user-defined function for selecting the core photos, and acquiring file paths of all the core photos to be processed in batches by using the function; s4, defining and designing a user-defined function to obtain four angular points of the core picture selected in the S3, performing perspective transformation, and storing the four angular points; s5, creating a'batch selection photo 'button and an'interactive perspective transformation' button, and binding the buttons with the custom functions in S3 and S4; and S6, performing packaging on the steps S2 to S5 by using Anacoda, and creating an exe executable file. According to the method, on the premise that the core box does not need to be preprocessed, a method for rapidly and accurately correcting deformation and cutting a large number of core photos is provided for geologists based on the graphical user interface.

The invention provides a task allocation method and device, electronic equipment and a storage medium, the method is applied to a processing core of graphic processing equipment, the processing core comprises a plurality of computing unit clusters, and the method comprises the following steps: under the condition that primitive set information of a to-be-rendered first block in a rendering object is obtained, the to-be-rendered first block in the rendering object is obtained; establishing a first rendering task of the first image block; according to a set task allocation mode, acquiring allocated task information of the plurality of computing unit clusters corresponding to the task allocation mode; determining a target computing unit cluster from the plurality of computing unit clusters according to the allocated task information; and sending the first rendering task to a task queue of the target computing unit cluster, so that the target computing unit cluster executes the first rendering task. According to the embodiment of the invention, the load balance of computing resources can be improved, and the utilization rate of the computing resources is improved.

The invention discloses a system cache processing method and device, electronic equipment and a storage medium, and relates to the technical field of data storage. When a storage volume receives a system cache task needing to be processed, the task scheduling condition of a processing core bound with the system cache task is determined firstly; under the condition that the processing core is not too busy, the processing core currently bound with the storage volume is directly adopted to execute the system cache task; when the processing core is relatively busy, a processing core which is relatively not busy can be re-determined to complete the system cache task. When a system cache task is received each time, a processing core which is not too busy is searched for to execute the task, so that the conditions that the processing speed is reduced, the system cache performance is reduced and the like due to task accumulation are avoided, the system cache performance is effectively improved, meanwhile, the utilization rate of the processing core in a computer is improved, and the processing efficiency is improved. Therefore, the performance of the whole computer is greatly improved.

A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

For example, an apparatus may include a motherboard including a functional processing core configured to perform a functionality having a Functional Safety (FuSa) level; a FuSa transceiver configured to communicate with an external safety-island processor, which is external to the motherboard; and a FuSa controller configured to establish a FuSa connection with the external safety-island processor according to the FuSa level, to send FuSa information corresponding to the functionality of the functional processing core to the external safety-island processor via the FuSa transceiver, and to control one or more FuSa operations of the functional processing core based on one or more control messages received from the external safety-island processor via the FuSa transceiver.

The invention relates to a processor and a kernel synchronization method for the processor. Based on the method and the device, the query request initiated by the plurality of processing cores in the processor for the same specified data can be selectively forwarded by the route, so that the occupation of the query request on the on-chip bandwidth of the processor can be reduced, and the query response occupying the on-chip bandwidth of the processor can be indirectly reduced. Or, the data cache unit where the specified data is located can reduce the generation of the query response for promoting the processing kernel to continue to initiate the query request, so that not only can the occupation of the query response to the on-chip bandwidth of the processor be reduced, but also the query request occupying the on-chip bandwidth of the processor can be indirectly reduced. Therefore, the occupation of the query request and the query response for realizing kernel synchronization on the on-chip bandwidth of the processor can be inhibited from the routing forwarding source of the query request or the generation source of the query response, so that the on-chip bandwidth occupied by the kernel synchronization in the processor can be reduced.

Systems and methods for servicing nodes participating in inter-node communications in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where the orchestrator is configured to service a first node in communication with a second node without any involvement by any Operating System (OS) of the IHS.

Systems and methods for distribution and management of certificates in a firmware framework. In some embodiments, an Information Handling System (IHS) may include a controller, where the controller includes firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device includes firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node of a plurality of nodes of a firmware framework; and where the orchestrator is configured to: store certificates in a local storage of the controller; and distribute one or more other certificates to one or more of the plurality of nodes within the firmware framework, without any involvement by any Operating System (OS) of the IHS.

Systems and methods for secure communications in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, wherein the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where a given node is configured to communicate with the orchestrator, at least in part, using a security service of the firmware framework without any involvement by any Operating System (OS) of the IHS.

An apparatus to facilitate hardware acceleration of resource barriers in a graphics environment is disclosed. The apparatus includes resource barrier hardware circuitry for processing cores and a graphics pipeline to: receive a resource barrier instruction to transition a resource utilized by the graphics pipeline from a first usage to a second usage; responsive to the resource barrier instruction, cause a draw group marker having a current draw group count to be sent to an end of the graphics pipeline to track completion of each stage of the graphics pipeline; increment the current draw group count to a new draw group count for each new draw group of the graphics pipeline; and determine that a current signal stage of the graphics pipeline is complete for a current draw group responsive to a done count for the current signal stage being less than or equal to the current draw group count.

Systems and methods for diagnostics in a firmware framework. In some embodiments, an Information Handling System (IHS) may include: a controller, where the controller comprises firmware that, upon execution by a processing core, causes the processing core to instantiate an orchestrator; and a plurality of devices coupled to the controller, where each device comprises firmware that, upon execution by a corresponding processing core, causes the corresponding processing core to instantiate a node as part of a firmware framework, and where the orchestrator is configured to trigger a diagnostics operation by a selected node to be performed independently of any Operating System (OS) of the IHS.

A system to output a response to a query via processing a large language model is disclosed. The system includes an array of processing cores arranged in a grid allowing each processing core to communicate directly to a neighboring processing core. An interconnection network is coupled to each of the processing cores allowing communication between the processing cores. A first processing core of the array of processing cores is configured to receive an encrypted query. A second processing core of the array of processing cores is configured to input the encrypted query to a large language model; execute the large language model having general weights in plaintext; and provide an encrypted output of the large language model.

The invention discloses a fault detection method and device, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that enhanced error report register data and machine inspection architecture register data from a server are received, the enhanced error report register data and the machine inspection architecture register data are sent when the server detects that the graphics processing unit has uncorrectable errors and the number of times of correctable errors reaches a preset threshold value; under the condition that the enhanced error report register data and the machine check architecture register data are valid, determining whether the graphics processing unit is in a healthy state according to the machine check architecture register data; if not, the fault type and the fault position of the graphic processing unit are determined according to at least one of the processing core information and the memory information included in the enhanced error report register data, so that specific internal equipment with faults of the graphic processing unit can be accurately positioned.

A hardware apparatus for isolated virtual environments includes graphics processing unit comprising a first dedicated memory and a first plurality of processing cores, a central processing unit comprising a second dedicated memory and a second plurality of processing cores, a field programmable gate array comprising a third dedicated memory, a control and data bus assembly connecting the field programmable gate array, the central processing unit, and the graphics processing unit, and a hypervisor located on a non-volatile memory of the hardware apparatus, the hypervisor configured to create one or more virtual machines by isolating the graphics processing unit, the central processing unit and the field programmable gate array.

The invention provides a multi-core consistency test method and device, electronic equipment and a storage medium, and relates to the technical field of communication. Comprising the following steps: determining a plurality of test parameters and a value range of each test parameter according to a test requirement of tested equipment; generating a plurality of groups of test parameter combinations according to the value range of each test parameter; according to the multiple groups of test parameter combinations, creating a test program corresponding to each processing core in a plurality of processing cores participating in the test in the tested equipment, and deploying the test program corresponding to each processing core to each processing core; running the test program on each processing core, and controlling the corresponding processing core to perform consistency test verification by the test program according to each group of test parameter combination to obtain a test result corresponding to each group of test parameter combination; and according to the test result corresponding to each group of test parameter combination, analyzing to obtain a consistency test result between the processing cores. According to the method, the test parameter combination capable of comprehensively covering more test scenes can be generated, and the test comprehensiveness and accuracy are improved.

The invention discloses a method, a system and a device for realizing high-repetition-frequency wide-width imaging, and relates to the technical field of high-repetition-frequency wide-width imaging, and the method comprises the steps: carrying out the pulse compression of large-size imaging echo data; setting the number of accumulation frame periods and the number of imaging areas; a first cache, a second cache, a first processing core and a second processing core are arranged, high repetition frequency imaging accumulation is conducted on pulse pressure data of multiple accumulation frame periods through the first cache, the second cache, the first processing core and the second processing core, and high repetition frequency imaging accumulation results corresponding to multiple imaging areas are spliced. Based on this, the dual-core model separates the control flow and the imaging accumulation process, and the two cores perform parallel processing, so that the processing speed can be improved; an imaging accumulation process is divided into pulse pressure cache and imaging hardcore accumulation by a double-cache technology, and the repetition frequency is improved by optimizing time efficiency through a memory; and the imaging data is divided into a plurality of areas for respective imaging, so that the problem of imaging sheet limitation can be solved.

The invention provides a network card drive optimization method and device, equipment and a storage medium, and the method comprises the steps: resetting a throttling counter in a drive interrupt path according to an interrupt merging factor and a throttling parameter of a hardware interrupt response determined by an interrupt behavior state model, and generating a merging control strategy; polling and reading the use state of the buffer area according to the combination control strategy, and updating an interrupt response state table; and determining an optimal interrupt processing core set according to the interrupt response state table and the original operation data, generating an interrupt affinity mapping strategy, grouping the to-be-processed data packets of the receiving queue, and performing batch scheduling on the soft interrupt threads of the corresponding groups based on different soft interrupt priority levels of each group. According to the scheme, the interrupt processing core is selected by constructing the dynamic interrupt affinity mapping strategy, adaptive allocation of interrupt scheduling is achieved, resource idling and core migration expenses are reduced, and the interrupt processing efficiency and the resource utilization rate of the multi-core processor are effectively improved.