354 results about "System on a chip" patented technology

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

The invention provides a request merging method, a request merging system, a chip, a request merging device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: determining the unit data volume of write data processed in each beat based on the maximum value of the connection line width of the write data between an upstream module and a memory merging module and the cache line size; based on the request length and the unit data volume of the original requests, determining the request number of the original requests merged in each beat; wherein the total data amount of the original request combined in each beat is smaller than or equal to the unit data amount; and merging the plurality of original requests according to the request quantity to obtain at least one merged request, and mapping data of each original request corresponding to the merged request based on the unit data volume to obtain merged data of the merged request.

Aspects of the disclosure are directed to dynamic workload partitioning. In accordance with one aspect, the disclosure includes a first system on a chip (SOC) configured to commence a use case execution using a baseline workload partition; and a controller coupled to the first SOC, the controller configured to determine if the baseline workload partition should be reallocated using a machine learning (ML) monitoring of system on a chip (SOC) temperatures.

The invention provides a calibration method and device of an energy storage system, the energy storage system, a chip and a program product. The energy storage system comprises a plurality of battery clusters. Acquiring required power and a first priority sequence of the plurality of battery clusters; according to the demand power and the first priority sequence, the charging and discharging power of a plurality of battery clusters is determined, and when the charging and discharging power of a first battery cluster in the plurality of battery clusters is lower than a power threshold value, the first battery cluster is controlled to carry out SOC calibration, and the method comprises the following steps: obtaining SOC difference values among a plurality of battery monomers of the first battery cluster; when the first SOC value is greater than a first threshold value and the SOC difference value is greater than a second threshold value, controlling the first battery cluster to perform SOC low-end standing calibration; and if the first SOC value is greater than the first threshold value and the SOC difference value is less than or equal to the second threshold value, controlling the first battery cluster to perform SOC low-end standing calibration or SOC full-charge calibration so as to improve the safety and reliability of the energy storage system.

The invention provides a half-bridge system, a chip and a preparation method of the half-bridge system, and relates to the technical field of power. The half-bridge system comprises an upper tube and a lower tube which are connected in sequence; the source electrode of the upper tube is connected with the drain electrode of the lower tube; hybrid bonding is arranged between the source electrode of the upper tube and the drain electrode of the lower tube, the source electrode of the upper tube and the drain electrode of the lower tube form interconnection through the hybrid bonding, and the source electrode of the upper tube and the lower tube form an inverted structure through the hybrid bonding. Direct and short-distance interconnection of the source electrode of the upper tube and the drain electrode of the lower tube can be achieved through mixed bonding, and compared with traditional bonding wires and long PCB routing, the current transmission path is greatly shortened, and parasitic inductance can be remarkably reduced. In addition, the inverted structure further optimizes the spatial layout and the connection mode between the devices, reduces additional leads and other parasitic sources, and weakens the source of parasitic inductance generation from the structural level.

The invention belongs to the technical field of welding, and discloses a welding robot system, a chip welding method, a chip welding device and a computer storage medium, the welding robot system comprises a calibration module used for bearing a calibration plate, and the calibration plate calibrates a bonding pad to obtain a three-dimensional coordinate of the bonding pad; the mechanical arm is arranged adjacent to the calibration module; the detection module is arranged adjacent to the mechanical arm and the calibration module and is used for collecting sensor data so as to determine a height sequence of welding spots, a temperature field distribution diagram of a welding area and defect characteristics of the to-be-welded chip in combination with the three-dimensional coordinates; and the main control unit is electrically connected with the detection module and / or is in signal connection with the detection module, and is used for carrying out feature fusion and determining welding laser power and a welding speed adjusting instruction according to the obtained multi-sensor fusion features to obtain a preset welding track so as to control the mechanical arm to execute the preset welding track. According to the method, submicron heterogeneous material calibration, thermal interface cooperative control, cross-material process rapid adaptation and multi-modal interface reliability evaluation can be realized.

The invention relates to the technical field of data encryption, and discloses a data encryption device, a memory encryption and decryption system and a chip. A password root output end; the key generation circuit is used for generating an n-bit first key and an n-bit second key; the data encryption logic circuit comprises a four-round encryption module, a four-round encryption unit in the four-round encryption module comprises an n-bit interleaver, four columns of 64-bit round function components correspondingly arranged on the two sides of the interleaver and two sub-circuits for encrypting residual data and residual keys, and the four-round encryption unit is connected with an address input end, a password root output end and a key generation circuit. And the four-round encryption module is used for performing alignment processing on the memory access address, performing interleaving encryption processing based on the four-round encryption module according to the n-bit alignment address obtained by the alignment processing, the first key and the second key, and generating an n-bit password root, so that the encryption device encrypts the write data according to the password root, and the decryption device decrypts the read data according to the password root.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

Eyewear including a frame having a first side and a second side, a first temple extending from the first side of the frame, a second temple extending from the second side of the frame, electronic components, a first system on a chip (SoC) adjacent the first side of the frame coupled to a first set of the electronic components, and a second system on a chip adjacent the second side, the second SoC coupled to the first SoC and to a second set of the plurality of electronic components. Processing workloads are balanced between the first SoC and the second SoC by performing a first set of operations with the first SoC and performing a second set of operations with the second SoC.

The invention discloses a manufacturing method of a three-dimensional system chip based on an aluminum nitride bonding structure and the three-dimensional system chip, and belongs to the field of advanced packaging of semiconductors. The manufacturing method comprises the following steps: providing a mother wafer, wherein the surface of the mother wafer is provided with a mother core metal electrode array; providing at least one sub-core particle, wherein the surface of the sub-core particle is provided with a sub-core metal electrode array; forming an aluminum nitride bonding layer in a non-electrode interconnection area on the surface of the mother wafer and / or the surfaces of the sub core particles; and stacking and aligning the sub-core particles and the mother wafer, and bonding through the aluminum nitride bonding layer, so that the mother core metal electrode array and the sub-core metal electrode array are vertically interconnected. According to the invention, aluminum nitride is used as a bonding and filling medium, and has the characteristics of high insulativity and high thermal conductivity, so that high-density and high-reliability electrical interconnection is realized, an efficient heat dissipation channel is provided for the high-power-consumption core particles, and the technical problem that heat dissipation and insulation in traditional three-dimensional integration are difficult to collaboratively optimize is solved.

The utility model discloses a high-definition multi-path image processing structure, which comprises a shell, at least one network interface arranged on the shell, a processor arranged in the shell, a video decoder arranged in the shell and connected with the network interface and the processor, and a processor arranged in the shell and connected with the network interface and the processor. And the video receiver is arranged in the shell and is connected with the video decoder and the processor. Therefore, the system chip (system-on-chip, SoC) and the field programmable gate array (field programmable gate array, FPGA) are separately arranged, so that the required FPGA and SoC can be flexibly selected for development, the cost can be effectively reduced, the processing efficiency can be improved, the overall speed can be improved, the system load of a personal computer (PC) is reduced, and the development cost of the system chip (system-on-chip, SoC) and the development cost of the system chip (system-on-chip, SoC) can be reduced. Therefore, the structure of the utility model can carry out multi-path high-quality image processing.

The invention discloses a manufacturing method of a three-dimensional system chip, and the method comprises the steps: providing a first wafer which comprises first core particles; providing a second core particle; manufacturing an interconnection patch cord, wherein the interconnection patch cord is used for interconnecting the electrodes in the same first core particle and / or the electrodes among different first core particles; a bonding layer is formed on the first wafer and the second core particle, and the bonding layer exposes a partial region of the electrode or the patch cord to serve as an I / O interconnection electrode; bonding the first wafer and the second chip particle by using a bonding layer, wherein the I / O interconnection electrodes of the first wafer and the second chip particle are opposite to each other; and depositing metal on the I / O interconnection electrodes of the first wafer and the second wafer until interconnection is formed. And three-dimensional system physical integration of a plurality of heterogeneous and heterogeneous core particles is realized so as to complete electrical interconnection among all the core particles required by a system chip.

The present disclosure relates to accelerating table lookups using decoupled lookup table accelerators in a system on a chip. In various examples, a VPU and associated components can be optimized to improve VPU performance and throughput. For example, the VPU can include a min / max collector, an auto store prediction function, a SIMD data path organization that allows inter-lane sharing, a transpose load / store with stride parameter function, a load with permute and zero insertion function, a hardware, logic, and memory layout function to allow two-point and two-point by one lookups, and a per memory bank load cache function. Further, a decoupled accelerator can be used to offload VPU processing tasks to improve throughput and performance, and a hardware sequencer can be included in a DMA system to reduce programming complexity of the VPU and DMA system. The DMA and VPU can perform a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Provided is a system-on-chip including a host central processing unit (CPU) and a secure element, wherein the secure element includes a primary device configured to transmit encrypted data, an internal bus configured to transmit the encrypted data, a plurality of secondary devices configured to receive the encrypted data, and a secure CPU configured to manage access keys indicating authorization of the primary device for accessing the plurality of secondary devices, and the internal bus sets a secondary device to which the encrypted data is to be transmitted from among the plurality of secondary devices, based on the access key and transmits the encrypted data to a set secondary device by using an error detection tag.

A computer-implemented method causes a data processing hardware to perform operations when executed by the data processing hardware. The operations include providing a common encryption key and a unique encryption key at a system on a chip (SoC) of a radar module, providing a unique key pair at the SoC, the unique key pair including a unique public key and a unique private key, and encrypting software with the common encryption key. The operations further include generating a secure boot certificate for the encrypted software, signing the secure boot certificate using the unique private key, and writing the encrypted software to an external flash memory. The operations further include updating the software at the SoC, verifying the software update via a regional public key, and signing the secure boot certificate with a device unique private key via a hardware security module (HSM) of the SoC.

An displaying device includes a backlight module, a display panel located on one side of the backlight module, at least two first driving-chip groups, at least two first circuit boards and a system chip, each of the first driving-chip groups includes at least two first driving chips, and all of the first driving chips are electrically connected to the display panel. Each of the first circuit boards is electrically connected to one first driving-chip group, the first circuit boards are cascaded, and at least some of the signals transmitted in the first circuit boards are synchronous. The first circuit boards are electrically connected to the backlight module. The system chip is electrically connected to the first circuit boards, and configured for providing at least two channels of the same video signal to the at least two first circuit boards, and receiving a touch-controlling signal from the display panel.

The utility model belongs to the field of Internet of Things, and relates to a core board conforming to Jetson Orin Nano, which comprises an Internet of Things chip, a Jetson Orin Nano chip and a Jetson Orin Nano chip, the PCIE bridging controller chip, the power supply management chip, the power supply management system chip, the USB Hub controller, the Ethernet physical layer chip, the direct current power supply input circuit, the PMIC clock circuit, the analog power supply electromagnetic interference protection circuit, the LPDDR4 power supply circuit, the automatic power-on circuit, the PCIE switching circuit, the PCIE expansion chip power supply circuit and the PMIC interface circuit are electrically connected with the Internet of Things chip; the USB Hub controller is further connected with the switch chip, and the Internet of Things chip is used for collecting, processing, transmitting and controlling data of Internet of Things equipment. Due to the fact that the data processing capacity is high, the expansibility is high, power management and data transmission are stable, and powerful technical support is provided for application of the Internet of Things.

The application relates to a unique optoelectronic module configured to operate simultaneously at high-speed bit rate and low speed bit rate, thanks to a reconfigurable system on a chip, i.e. a programmable unit on a chip. This reconfigurable system embeds the electronic circuitry of the low-speed channel(s), i.e. at least the driver when the link is a transmission channel, or at least the amplifier when the link is a receiver channel.

Methods and systems for managing cooling of a data processing system. In particular, methods and system for providing system temperature control using an embedded controller installed in a data processing system having an advanced reduced instruction set computer machines (ARM) based architecture system on a chip (SoC) are provided. The embedded controller may be bridged to the ARM based architecture SoC using a bridging agent that bridges enhanced serial peripheral interface (eSPI) format communication to system power management interface (SPMI) format communication.

The invention provides a chip component interconnection link calibration method and device, a multi-chip component interconnection system, a chip component, electronic equipment and a storage medium, and relates to the technical field of integrated circuits. The method comprises the steps that telemetry data of all chip assemblies in the operation process are collected, and all the chip assemblies are communicated through interconnection links; predicting a starting moment when the signal quality of the interconnection link is degraded based on the telemetry data; and adjusting signal related parameters of the interconnection link to calibrate the signal quality of the interconnection link before the starting moment and under the condition that the interconnection link is confirmed to meet an active calibration condition based on the telemetry data. According to the scheme, active calibration can be carried out before the initial moment when the signal quality of the interconnection link is degraded, so that the energy efficiency and the stability of the interconnection link can be improved.

Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.

Provided in the present disclosure are an information transmission method and apparatus, and a device, a system, a chip and a storage medium. The method comprises: receiving first system information, wherein a terminal is located at a first beam position of a cell covered by a network device, and the first system information is different from system information of at least one beam position in the cell. Therefore, terminals at different beam positions or beam position groups can receive different types of system information, thereby improving the flexibility of system information configuration.

Provided in the embodiments of the present application is a data transmission method, which is applied to any intermediate node in a networking system and comprises: receiving a target packet, wherein a destination node of the target packet is different from the intermediate node, and the target packet is a packet used for time synchronization; and after a first duration from the start of receiving the target packet, sending the target packet to a downstream node of the intermediate node. Because the intermediate node sends the target packet to the downstream node of the intermediate node after the first duration from the start of receiving the target packet, a processing delay of the intermediate node for the target packet is fixed, making receiving and sending processing delays of the intermediate node symmetrical. Thus, when target packets used for time synchronization are exchanged between a master clock node and a slave clock node via an intermediate node, it can be ensured that uplink and downlink transmissions between the master clock node and the slave clock node are symmetrical, thereby simplifying a time synchronization process and achieving accurate time synchronization.

The invention provides a firmware loading method, a processing system, a chip and electronic equipment, and the method applied to a slave chip system comprises the steps: receiving basic firmware from a master chip system through a first transmission path after the slave chip system is powered on; the slave chip system loads basic firmware to initialize a second transmission path for output transmission with the master chip system; wherein the data transmission rate of the first transmission path is smaller than that of the second transmission path; and the slave chip system receives and loads the complete firmware from the master chip system through a second transmission path so as to initialize the slave chip system. According to the technical scheme, the problem that hardware cost and PCB space occupation are increased due to the fact that firmware is independently loaded from a chip system in the related technology is solved, and the hardware design complexity is reduced while the cost is reduced.

The invention discloses a single-particle fault automatic detection and processing method and system, a chip and electronic equipment, and relates to the field of chip detection. And before or when the task instruction is sent to the business unit, configuring the temperature threshold value of each heat source and the power supply information of each power supply domain in the business unit. Respectively comparing the acquired real-time temperature and the real-time parameter of each power domain with a temperature threshold and power information, and determining whether a single-particle fault exists or not; if the single-particle fault exists, fault processing is carried out according to a preset processing method; and if the single-particle fault does not exist, a self-checking instruction is sent to the service unit, so that the service unit performs self-checking. According to the method and the device, two main influences of the single event effect, namely single event upset and single event locking, are solved, the reliability of single event fault checking and processing is high, and a related system built by a common device has relatively good space environment adaptability.

Provided in the embodiments of the present disclosure are a tensor data transformation method, a tensor processing unit, a processor, a system on a chip, and a computing device. The tensor processing unit comprises: a register array unit, which comprises at least a source address register, a destination address register, and a source tensor parameter register; an instruction decoding unit, which parses an acquired transformation operation instruction, so as to obtain a transformation operation type indicated by an operation type field and obtain respective register serial numbers of the source address register, the destination address register, and the source tensor parameter register; and an instruction execution unit, which accesses the source address register, the destination address register, and the source tensor parameter register on the basis of their respective register serial numbers, reads a source memory address field, a destination memory address field, and a source tensor parameter, reads a source tensor on the basis of the source memory address field, performs, on the source tensor, a transformation operation indicated by the transformation operation type, and writes, on the basis of the source tensor parameter, a destination tensor obtained after the transformation operation into the destination memory address field.

An information handling system includes a system on a chip (SoC) and an embedded controller. The system receives a firmware update bundle, which includes benchmark update configurations and firmware updates for the information handling system. The SoC performs a firmware update process based on the firmware update bundle. In response to the firmware update process being successful, the information handling system restarts. Upon the restart of the information handling system, the SoC performs boot operations with the firmware updates and previous user configurations. During the firmware update process, the system stores the benchmark update configurations. The embedded controller monitors the boot operations of the SoC. In response to a failure of the boot operations, the system replaces the previous user configurations with the benchmark update configurations.

Provided are a power consumption control system for a system on chip, the system on chip and a computing device. The power consumption control system comprises: a plurality of process sensors; a power consumption controller comprising: a chain controller configured to collect at least one count value from each of the plurality of process sensors, and to perform a weighted calculation on the count values of the plurality of process sensors to determine a process deviation of the system on chip under a first working condition; a voltage and frequency calculation unit configured to determine a target frequency and / or a target voltage to which the system on chip is to be adjusted according to the process deviation; a voltage adjustment signal generation unit configured to generate a voltage adjustment signal for adjusting a supply voltage of the system on chip according to the target voltage; and a frequency control unit configured to generate a frequency adjustment signal for adjusting a clock frequency of the system on chip according to the target frequency. The process deviation thus determined is more accurate, and the target frequency and the target voltage calculated based on the process deviation are also more suitable for the current working condition.

In various examples, systems and methods are disclosed that relate to processing data using accelerators in a system on a chip. For example, a plurality of processing elements (PEs) can interconnect to form a processing engine, and a control system can control operation of the PEs based at least on the connections between the PEs. In some examples, the PEs can receive sub-inputs and transfer the sub-inputs to one or more other PEs to enable performance of the instructed operations. In examples, once the PEs complete the instructed operations, the sub-inputs can be transferred out of the processing engine.