533 results about "System on a chip" patented technology

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

The invention relates to a communication computing power transmitting and receiving system chip based on core particle stacking packaging. The communication computing power transmitting and receiving system chip comprises an organic packaging substrate, programmable radio frequency transceiver core particles, computing power device core particles, programmable logic core particles and a ceramic substrate. The computing power device core particles and the programmable logic core particles are horizontally and adjacently arranged on the device mounting surface of the organic packaging substrate; a pre-buried semi-groove is dug in the second surface of the ceramic substrate, and the programmable radio frequency transceiver core particles are arranged in the pre-buried semi-groove; the ceramic substrate is buckled on the organic packaging substrate, the device mounting surface of the organic packaging substrate is opposite to the second surface of the ceramic substrate, and the ceramic substrate completely covers the arranged programmable logic core particles and the arranged computing power device core particles; a conductive layer is arranged between the ceramic substrate and the organic packaging substrate. The communication computing power transceiving system chip can solve the problems of large occupied space, high signal transmission delay and low heat dissipation efficiency in a traditional packaging scheme, can reduce the size of a fuselage of an unmanned aerial vehicle, and enhances the performance of the unmanned aerial vehicle.

The invention provides a request merging method, a request merging system, a chip, a request merging device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: determining the unit data volume of write data processed in each beat based on the maximum value of the connection line width of the write data between an upstream module and a memory merging module and the cache line size; based on the request length and the unit data volume of the original requests, determining the request number of the original requests merged in each beat; wherein the total data amount of the original request combined in each beat is smaller than or equal to the unit data amount; and merging the plurality of original requests according to the request quantity to obtain at least one merged request, and mapping data of each original request corresponding to the merged request based on the unit data volume to obtain merged data of the merged request.

The invention provides a data transmission method and system, a chip, electronic equipment and a storage medium, the method is applied to a processing module of the data transmission system, and the method comprises the following steps: under the condition that an interrupt request is received, obtaining a data transmission instruction, and performing data analysis on the data transmission instruction to obtain an interrupt request; obtaining a data operation type, an interface type and a data transmission parameter; acquiring register configuration data corresponding to the interface type, and performing configuration corresponding to the register configuration data and the data transmission parameters on the configuration register through the internal bus; under the condition that configuration of the configuration register is completed, data to be transmitted are obtained through a transmission interface corresponding to the register configuration data, and data transmission corresponding to the data operation type and the data transmission parameter is conducted on the data to be transmitted based on the control register and the encryption and decryption unit. The transmission interface is one of a bus master interface, a bus slave interface and a private interface.

This disclosure provides systems, methods, and devices for enhancing data communication and computation efficiency in Systems on a Chip (SoC). In one aspect, a system is provided that uses a network on a chip (NOC) to route communications between chip components using a plurality of network interfaces linked by shared data connections. The system may be configured to route communications via multiple virtual channels along the shared connections, with credit restrictions for the channels. Additionally, the system may support mechanisms for maintaining both private and shared credit balances for these virtual channels. Additional aspects are also discussed.

The invention discloses a magnetic aggregation induced emission particle fluorescence-electrochemical nucleic acid dual detection chip and system.The chip comprises a chip body and an upper cover, and a plurality of electrochemical reaction detection cavities and fluorescence reaction detection cavities are formed in the left side and the right side of the chip body in the front-back direction respectively; the electrochemical reaction detection cavities and the fluorescence reaction detection cavities are arranged in a one-to-one correspondence manner; each electrochemical reaction detection cavity and each fluorescence reaction detection cavity are provided with a flow channel, and one end of each flow channel is communicated with the electrochemical reaction detection cavity or the fluorescence reaction detection cavity; the other end of the sampling tube is communicated with an MAIE electrochemical detection auxiliary liquid sample adding hole and an MAIE fluorescence detection auxiliary liquid sample adding hole which are formed in the chip main body; a plurality of MAIE electrochemical detection sample adding holes and MAIE fluorescence detection sample adding holes are formed in the upper cover, and corresponding openings are formed in the positions, corresponding to the MAIE electrochemical detection auxiliary liquid adding holes and the MAIE fluorescence detection auxiliary liquid adding holes, of the upper cover.

The invention discloses a chip sorting method and a chip sorting system.The chip sorting method comprises the steps that a plurality of wafers are provided, and each wafer comprises a plurality of chips; testing the photoelectric performance of the chip, and recording and storing the serial number of the wafer and the photoelectric performance parameter; carrying out primary sorting according to the photoelectric performance parameters, dividing the chips into first-level sub BIN 1 to first-level sub BIN n, respectively counting the number of the chips and summing, and recording the sum as S1-Sn; setting a first preset value A, comparing Sn with A, and determining a first-level sub-BIN to which the chip belongs according to a comparison result; if Sn is greater than A, the chip in the first-level sub BIN n belongs to the original first-level sub BIN n; if Sn is smaller than or equal to A, the chips in the first-level sub BIN n belong to the sub BIN in the first-level set; for the chips in the primary sub BIN n, selecting the chips to the corresponding blue films according to the BIN, and arranging the chips; and for the chips in the sub BIN in the primary set, the chips are selected to the same blue film for arrangement according to the serial numbers of the wafers to which the chips belong, and secondary sorting is executed. According to the invention, the chip sorting efficiency is improved while the yield of good chips is improved.

Aspects of the disclosure are directed to dynamic workload partitioning. In accordance with one aspect, the disclosure includes a first system on a chip (SOC) configured to commence a use case execution using a baseline workload partition; and a controller coupled to the first SOC, the controller configured to determine if the baseline workload partition should be reallocated using a machine learning (ML) monitoring of system on a chip (SOC) temperatures.

The invention provides a calibration method and device of an energy storage system, the energy storage system, a chip and a program product. The energy storage system comprises a plurality of battery clusters. Acquiring required power and a first priority sequence of the plurality of battery clusters; according to the demand power and the first priority sequence, the charging and discharging power of a plurality of battery clusters is determined, and when the charging and discharging power of a first battery cluster in the plurality of battery clusters is lower than a power threshold value, the first battery cluster is controlled to carry out SOC calibration, and the method comprises the following steps: obtaining SOC difference values among a plurality of battery monomers of the first battery cluster; when the first SOC value is greater than a first threshold value and the SOC difference value is greater than a second threshold value, controlling the first battery cluster to perform SOC low-end standing calibration; and if the first SOC value is greater than the first threshold value and the SOC difference value is less than or equal to the second threshold value, controlling the first battery cluster to perform SOC low-end standing calibration or SOC full-charge calibration so as to improve the safety and reliability of the energy storage system.

The invention provides a half-bridge system, a chip and a preparation method of the half-bridge system, and relates to the technical field of power. The half-bridge system comprises an upper tube and a lower tube which are connected in sequence; the source electrode of the upper tube is connected with the drain electrode of the lower tube; hybrid bonding is arranged between the source electrode of the upper tube and the drain electrode of the lower tube, the source electrode of the upper tube and the drain electrode of the lower tube form interconnection through the hybrid bonding, and the source electrode of the upper tube and the lower tube form an inverted structure through the hybrid bonding. Direct and short-distance interconnection of the source electrode of the upper tube and the drain electrode of the lower tube can be achieved through mixed bonding, and compared with traditional bonding wires and long PCB routing, the current transmission path is greatly shortened, and parasitic inductance can be remarkably reduced. In addition, the inverted structure further optimizes the spatial layout and the connection mode between the devices, reduces additional leads and other parasitic sources, and weakens the source of parasitic inductance generation from the structural level.

The invention belongs to the technical field of welding, and discloses a welding robot system, a chip welding method, a chip welding device and a computer storage medium, the welding robot system comprises a calibration module used for bearing a calibration plate, and the calibration plate calibrates a bonding pad to obtain a three-dimensional coordinate of the bonding pad; the mechanical arm is arranged adjacent to the calibration module; the detection module is arranged adjacent to the mechanical arm and the calibration module and is used for collecting sensor data so as to determine a height sequence of welding spots, a temperature field distribution diagram of a welding area and defect characteristics of the to-be-welded chip in combination with the three-dimensional coordinates; and the main control unit is electrically connected with the detection module and / or is in signal connection with the detection module, and is used for carrying out feature fusion and determining welding laser power and a welding speed adjusting instruction according to the obtained multi-sensor fusion features to obtain a preset welding track so as to control the mechanical arm to execute the preset welding track. According to the method, submicron heterogeneous material calibration, thermal interface cooperative control, cross-material process rapid adaptation and multi-modal interface reliability evaluation can be realized.

A system on a chip for enabling communication between a building management system (BMS) device and a BMS network. The system on a chip includes a device interface, a network interface, and a processing circuit. The device interface is configured to connect the system on a chip to the BMS device via a serial communication link. The network interface configured to connect the system on a chip to the BMS network. The processing circuit is configured to identify and update an attribute of an equipment object associated with the BMS device that corresponds to a command received from the BMS network via the network interface and transmit a message to the BMS device via the device interface using the updated attribute of the equipment object.

Eyewear devices that include two SoCs that share processing workload. Instead of using a single SoC located either on the left or right side of the eyewear devices, the two SoCs have different assigned responsibilities to operate different devices and perform different processes to balance workload. In one example, the eyewear device utilizes a first SoC to operate the OS, a first color camera, a second color camera, a first display, and a second display. A second SoC is configured to run computer vision (CV) algorithms, visual odometry (VIO), tracking hand gestures of the user, and providing depth from stereo. This configuration provides organized logistics to efficiently operate various features, and balanced power consumption.

The invention relates to the technical field of data encryption, and discloses a data encryption device, a memory encryption and decryption system and a chip. A password root output end; the key generation circuit is used for generating an n-bit first key and an n-bit second key; the data encryption logic circuit comprises a four-round encryption module, a four-round encryption unit in the four-round encryption module comprises an n-bit interleaver, four columns of 64-bit round function components correspondingly arranged on the two sides of the interleaver and two sub-circuits for encrypting residual data and residual keys, and the four-round encryption unit is connected with an address input end, a password root output end and a key generation circuit. And the four-round encryption module is used for performing alignment processing on the memory access address, performing interleaving encryption processing based on the four-round encryption module according to the n-bit alignment address obtained by the alignment processing, the first key and the second key, and generating an n-bit password root, so that the encryption device encrypts the write data according to the password root, and the decryption device decrypts the read data according to the password root.

The invention discloses a data acquisition method, device and system, a chip and electronic equipment, and relates to the technical field of wireless communication, node data acquisition of a communication baseband chip can be realized through hardware, the method comprises the following steps: receiving first frame data and second frame data, the first frame data and the second frame data being continuous data frames; storing the first frame data in a first storage space; and in response to reading at least part of the first frame data, storing the second frame data in a second storage space which is not overlapped with the first storage space. In this way, software participation can be reduced, system overhead can be reduced, and power consumption of system operation can be saved. And for two continuous frames of data, the storage spaces are not overlapped, so that the risk of data coverage caused by software reset is avoided, the error risk caused by excessive intervention of software is released, and the real-time performance of the system is remarkably improved.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.

The invention provides a computing device, system and method, a chip, equipment and a medium. The computing device comprises a reading circuit, a computing circuit, a storage circuit, a control circuit and a plurality of first registers. The at least one first register is configured with task configuration information of the tasks, and the control circuit reads register information corresponding to the tasks one by one according to a preset mode; enabling a first register identified by a currently read register information to output first configuration information to a reading circuit, output second configuration information to a computing circuit, output third configuration information to a storage circuit, and controlling the reading circuit to perform time-sharing data reading according to the first configuration information of each task, and controlling the calculation circuit to perform data operation in a time-sharing manner according to the second configuration information of each task, and controlling the storage circuit to perform data storage in a time-sharing manner according to the third configuration information of each task, so that the resource utilization rate and the calculation efficiency of the calculation device can be improved.

The embodiment of the invention provides a battery management circuit, method, system, chip and electronic equipment, the battery management circuit is used for controlling a plurality of battery units, and the battery management circuit comprises an electrochemical impedance measurement module which is used for measuring the electrochemical impedance of the plurality of battery units in a preset frequency range; and the battery equalization module is used for carrying out electric quantity equalization on the plurality of battery units according to the electrochemical impedance of the plurality of battery units in the preset frequency range. According to the invention, aiming at different aging conditions of the battery, attenuation control can be effectively carried out, and the health degree of the battery is ensured.

Aspects of the disclosure are directed to processor access to compressed multimedia data. In accordance with one aspect, the disclosure includes converting a cache line address into a two-dimensional address based on a stride width; transforming the two-dimensional address into a pixel address; and computing a tile address using the pixel address and a main memory configuration.

The present application provides a method for sending a command, a storage medium, and a device. The method is applied to an electronic device, wherein the electronic device includes a system on a chip (SoC) and an input / output module. The method includes: in response to a first operation of a user, the SoC generates a first command and a preamble of a timing parameter adjustment command, wherein the first command is used to perform the first operation; the SoC sends the first command and the preamble of the timing parameter adjustment command to the input / output module; in response to a second operation of the user, the SoC generates a main body of the timing parameter adjustment command; and the SoC sends the main body of the timing parameter adjustment command to the input / output module. The SoC sends the first command and the preamble of the timing parameter adjustment command to the input / output module together. When the timing parameters need to be adjusted, the SoC sends the main body of the timing parameter adjustment command, shortening the length of the timing parameter adjustment command so that the timing parameter adjustment command is successfully sent to the input / output module within one clock cycle.

Eyewear including a frame having a first side and a second side, a first temple extending from the first side of the frame, a second temple extending from the second side of the frame, electronic components, a first system on a chip (SoC) adjacent the first side of the frame coupled to a first set of the electronic components, and a second system on a chip adjacent the second side, the second SoC coupled to the first SoC and to a second set of the plurality of electronic components. Processing workloads are balanced between the first SoC and the second SoC by performing a first set of operations with the first SoC and performing a second set of operations with the second SoC.

The invention discloses a vehicle information display method, a system-on-chip, electronic equipment, a storage medium and a program product, and is applied to the system-on-chip, the system-on-chip comprises a CPU, a GPU and a memory unit which are mutually connected through a system bus; the method comprises the steps that a CPU transmits vehicle information obtained from the outside to a memory unit through a system bus, so that a GPU reads the vehicle information, performs 3D rendering processing and outputs and displays the vehicle information; when the GPU breaks down, the CPU generates two-dimensional display information at least according to the vehicle information and outputs and displays the two-dimensional display information. According to the embodiment of the invention, when the GPU breaks down, the CPU takes over the display processing of the vehicle information, and carries out the two-dimensional display processing and output display of the vehicle information in a simplified drawing mode, so that the output display function of the vehicle information is completed, and the user experience is improved. And negative effects caused by excessive occupation of CPU resources when 3D rendering processing is carried out on the vehicle information are also avoided.

The invention discloses a manufacturing method of a three-dimensional system chip based on an aluminum nitride bonding structure and the three-dimensional system chip, and belongs to the field of advanced packaging of semiconductors. The manufacturing method comprises the following steps: providing a mother wafer, wherein the surface of the mother wafer is provided with a mother core metal electrode array; providing at least one sub-core particle, wherein the surface of the sub-core particle is provided with a sub-core metal electrode array; forming an aluminum nitride bonding layer in a non-electrode interconnection area on the surface of the mother wafer and / or the surfaces of the sub core particles; and stacking and aligning the sub-core particles and the mother wafer, and bonding through the aluminum nitride bonding layer, so that the mother core metal electrode array and the sub-core metal electrode array are vertically interconnected. According to the invention, aluminum nitride is used as a bonding and filling medium, and has the characteristics of high insulativity and high thermal conductivity, so that high-density and high-reliability electrical interconnection is realized, an efficient heat dissipation channel is provided for the high-power-consumption core particles, and the technical problem that heat dissipation and insulation in traditional three-dimensional integration are difficult to collaboratively optimize is solved.

The utility model discloses a high-definition multi-path image processing structure, which comprises a shell, at least one network interface arranged on the shell, a processor arranged in the shell, a video decoder arranged in the shell and connected with the network interface and the processor, and a processor arranged in the shell and connected with the network interface and the processor. And the video receiver is arranged in the shell and is connected with the video decoder and the processor. Therefore, the system chip (system-on-chip, SoC) and the field programmable gate array (field programmable gate array, FPGA) are separately arranged, so that the required FPGA and SoC can be flexibly selected for development, the cost can be effectively reduced, the processing efficiency can be improved, the overall speed can be improved, the system load of a personal computer (PC) is reduced, and the development cost of the system chip (system-on-chip, SoC) and the development cost of the system chip (system-on-chip, SoC) can be reduced. Therefore, the structure of the utility model can carry out multi-path high-quality image processing.

The invention discloses a reset signal generation method, a reset signal generation module and a system-on-chip chip reset architecture, and the method comprises the following steps: receiving input signals such as a reset source signal, synchronizing the reset source signal to a system clock domain, determining state transition, and generating a system-level reset signal and a module-level reset signal, the system-level reset signal is used for carrying out reset operation on the whole system, and the module-level reset signal is used for carrying out reset operation on each functional module in the system to ensure that each module can enter an initial state at a proper time. The invention provides an rstgen circuit scheme based on a multi-stage reset control architecture driven by a finite-state machine (FSM) and a modular clock synchronization mechanism, and through configurable state transition logic, multi-source reset signal priority management and simulation-actual dual-mode adaptation, control of a reset signal time sequence and comprehensive improvement of system compatibility are achieved.

The invention discloses a manufacturing method of a three-dimensional system chip, and the method comprises the steps: providing a first wafer which comprises first core particles; providing a second core particle; manufacturing an interconnection patch cord, wherein the interconnection patch cord is used for interconnecting the electrodes in the same first core particle and / or the electrodes among different first core particles; a bonding layer is formed on the first wafer and the second core particle, and the bonding layer exposes a partial region of the electrode or the patch cord to serve as an I / O interconnection electrode; bonding the first wafer and the second chip particle by using a bonding layer, wherein the I / O interconnection electrodes of the first wafer and the second chip particle are opposite to each other; and depositing metal on the I / O interconnection electrodes of the first wafer and the second wafer until interconnection is formed. And three-dimensional system physical integration of a plurality of heterogeneous and heterogeneous core particles is realized so as to complete electrical interconnection among all the core particles required by a system chip.

The present disclosure relates to accelerating table lookups using decoupled lookup table accelerators in a system on a chip. In various examples, a VPU and associated components can be optimized to improve VPU performance and throughput. For example, the VPU can include a min / max collector, an auto store prediction function, a SIMD data path organization that allows inter-lane sharing, a transpose load / store with stride parameter function, a load with permute and zero insertion function, a hardware, logic, and memory layout function to allow two-point and two-point by one lookups, and a per memory bank load cache function. Further, a decoupled accelerator can be used to offload VPU processing tasks to improve throughput and performance, and a hardware sequencer can be included in a DMA system to reduce programming complexity of the VPU and DMA system. The DMA and VPU can perform a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Provided is a system-on-chip including a host central processing unit (CPU) and a secure element, wherein the secure element includes a primary device configured to transmit encrypted data, an internal bus configured to transmit the encrypted data, a plurality of secondary devices configured to receive the encrypted data, and a secure CPU configured to manage access keys indicating authorization of the primary device for accessing the plurality of secondary devices, and the internal bus sets a secondary device to which the encrypted data is to be transmitted from among the plurality of secondary devices, based on the access key and transmits the encrypted data to a set secondary device by using an error detection tag.