684 results about "System on a chip" patented technology

The invention relates to the technical field of image analysis, in particular to a QFP chip image pyramid positioning system which comprises a pyramid construction module, a pin initial positioning module, a pin accurate positioning module and an interference area elimination module. According to the method, an original chip image is processed through step-by-step down-sampling and Gaussian filtering, the image processing speed is effectively improved when a multi-layer image pyramid is constructed, a pin connected domain is clearly identified by applying binarization processing and a pin neighbor connection strategy, the pin area identification capability of the system is enhanced, and the identification accuracy of the system is improved. Region recalibration is carried out by using an up-sampling image of an original image data size, accurate pin positioning can be executed while high resolution is maintained, the probability of wrong positioning is remarkably reduced by accurately extracting pin contour information and effectively eliminating non-target connected domains, the chip assembling quality is improved, the chip assembling speed is increased, and the chip assembling efficiency is improved. And remarkable benefits are brought to a high-speed electronic assembly line.

This disclosure describes systems on a chip (SOCs) that prevent trim attempts. The SOCs include one-time programmable (OTP) memory and an engine configured to determine if the one-time programmable (OTP) memory has been trimmed; and if the one-time programmable (OTP) memory has been trimmed, to prevent trimming of the OTP memory.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

The invention discloses a link auto-negotiation implementation method based on an Ethernet protocol, and relates to the technical field of link negotiation, and the method comprises the steps: according to an identifier of a SerDes IP protocol configuration register, judging and instantiating an auto-negotiation subsystem; configuring and sending an auto-negotiation frame through page data of the static random access memory; executing auto-negotiation state machine management, and negotiating to determine an optimal link parameter based on a page exchange and signal analysis result with opposite terminal equipment; monitoring link quality indexes of a plurality of channels in real time through a microcontroller; and according to a negotiation result, parameters of a sending end and a receiving end of the SerDes are reconfigured, and an external system chip is informed of final link parameters through an interrupt controller, so that link auto-negotiation and system initialization are completed. The problems of low link negotiation efficiency and poor link performance and stability in the prior art are solved.

The invention relates to a communication computing power transmitting and receiving system chip based on core particle stacking packaging. The communication computing power transmitting and receiving system chip comprises an organic packaging substrate, programmable radio frequency transceiver core particles, computing power device core particles, programmable logic core particles and a ceramic substrate. The computing power device core particles and the programmable logic core particles are horizontally and adjacently arranged on the device mounting surface of the organic packaging substrate; a pre-buried semi-groove is dug in the second surface of the ceramic substrate, and the programmable radio frequency transceiver core particles are arranged in the pre-buried semi-groove; the ceramic substrate is buckled on the organic packaging substrate, the device mounting surface of the organic packaging substrate is opposite to the second surface of the ceramic substrate, and the ceramic substrate completely covers the arranged programmable logic core particles and the arranged computing power device core particles; a conductive layer is arranged between the ceramic substrate and the organic packaging substrate. The communication computing power transceiving system chip can solve the problems of large occupied space, high signal transmission delay and low heat dissipation efficiency in a traditional packaging scheme, can reduce the size of a fuselage of an unmanned aerial vehicle, and enhances the performance of the unmanned aerial vehicle.

The invention provides a request merging method, a request merging system, a chip, a request merging device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: determining the unit data volume of write data processed in each beat based on the maximum value of the connection line width of the write data between an upstream module and a memory merging module and the cache line size; based on the request length and the unit data volume of the original requests, determining the request number of the original requests merged in each beat; wherein the total data amount of the original request combined in each beat is smaller than or equal to the unit data amount; and merging the plurality of original requests according to the request quantity to obtain at least one merged request, and mapping data of each original request corresponding to the merged request based on the unit data volume to obtain merged data of the merged request.

The invention relates to a low-power-consumption maintenance-free BLE (Bluetooth Low Energy) camera method based on edge collaboration, which is characterized in that a wireless camera and host equipment are mutually matched, the wireless camera is provided with an image sensor and a BLE function and is responsible for capturing, encoding and transmitting image data, and the host equipment is used as a receiving end and a control center of a system and is used for transmitting the image data. The system is characterized in that a wireless camera is used for processing image data from the wireless camera, the wireless camera is used for receiving guidance information from host equipment, carrying out adaptive image coding and dynamically adjusting connection parameters before transmission, and hardware implementation of the system mainly comprises three parts, namely Bluetooth low energy (BLE), a system chip (SoC), an image sensor and power management. According to the solution provided by the invention, the energy consumption can be effectively reduced, and continuous and stable monitoring is realized.

The invention provides a data transmission method and system, a chip, electronic equipment and a storage medium, the method is applied to a processing module of the data transmission system, and the method comprises the following steps: under the condition that an interrupt request is received, obtaining a data transmission instruction, and performing data analysis on the data transmission instruction to obtain an interrupt request; obtaining a data operation type, an interface type and a data transmission parameter; acquiring register configuration data corresponding to the interface type, and performing configuration corresponding to the register configuration data and the data transmission parameters on the configuration register through the internal bus; under the condition that configuration of the configuration register is completed, data to be transmitted are obtained through a transmission interface corresponding to the register configuration data, and data transmission corresponding to the data operation type and the data transmission parameter is conducted on the data to be transmitted based on the control register and the encryption and decryption unit. The transmission interface is one of a bus master interface, a bus slave interface and a private interface.

A vehicle control method, a vehicle control system, a chip, a controller, a vehicle, and a computer-readable storage medium. The vehicle control method comprises: acquiring an intended travel route of a vehicle, wherein the intended travel route is divided into k road segments, k being an integer greater than 1 (101); determining target SOCs for the k road segments, wherein a target SOC for an ith road segment is related to road condition information of road segments before and / or after the ith road segment, and i=2, 3, 4,…, k-1 (102); and when the vehicle travels on the intended travel route, controlling at least one of an engine and an electric motor of the vehicle on the basis of an actual SOC of a power battery of the vehicle and a target SOC for the road segment where the vehicle is located (103).

The embodiment of the invention provides a signal processing method based on a radio frequency system-on-chip chip and a related device, and the method comprises the steps: receiving a target linear frequency modulation signal; determining a complex number array on a frequency domain; determining an energy value of each frequency component according to the amplitude and the phase of each element to obtain a plurality of energy values; performing sliding window summation operation on the plurality of energy values in a time domain to obtain a plurality of total energy values; determining a maximum total energy value in the plurality of total energy values; and determining a target symbol value of a lead code of the target linear frequency modulation signal according to the maximum total energy value. After the target linear frequency modulation signal is received, the complex array is determined according to the preset frequency reduction linear frequency modulation signal and the target linear frequency modulation signal, and the target symbol value of the lead code of the target linear frequency modulation signal is determined according to the maximum energy value algorithm, so that the accuracy of positioning the initial position of the signal data is improved.

This disclosure provides systems, methods, and devices for enhancing data communication and computation efficiency in Systems on a Chip (SoC). In one aspect, a system is provided that uses a network on a chip (NOC) to route communications between chip components using a plurality of network interfaces linked by shared data connections. The system may be configured to route communications via multiple virtual channels along the shared connections, with credit restrictions for the channels. Additionally, the system may support mechanisms for maintaining both private and shared credit balances for these virtual channels. Additional aspects are also discussed.

The invention discloses a communication method, device and system, a chip, a storage medium and a program product. In the embodiment of the invention, the network equipment indicates the power adjustment amount, so that the terminal equipment can obtain the new sending power according to the initial sending power and the power adjustment amount, and performs uplink communication with the new sending power, thereby flexibly adjusting the sending power of the terminal equipment.

The present application relates to the field of integrated circuit technology, and discloses an on-chip power management system integrated in a wireless communication system chip; the system includes a first power switch, which connects a power supply and a universal input-output circuit in the system chip, and is used to control the power supply state of the universal input-output circuit; when the system chip is in a sleep state, the first power switch is controlled to power off the universal input-output circuit. The system powers off the universal input-output circuit by controlling the disconnection of the first power switch. In this way, leakage power consumption of the universal input-output circuit is avoided, and the energy consumption of the system chip is reduced. The present application also discloses a power-on control method for a wireless communication system chip.

The invention discloses a magnetic aggregation induced emission particle fluorescence-electrochemical nucleic acid dual detection chip and system.The chip comprises a chip body and an upper cover, and a plurality of electrochemical reaction detection cavities and fluorescence reaction detection cavities are formed in the left side and the right side of the chip body in the front-back direction respectively; the electrochemical reaction detection cavities and the fluorescence reaction detection cavities are arranged in a one-to-one correspondence manner; each electrochemical reaction detection cavity and each fluorescence reaction detection cavity are provided with a flow channel, and one end of each flow channel is communicated with the electrochemical reaction detection cavity or the fluorescence reaction detection cavity; the other end of the sampling tube is communicated with an MAIE electrochemical detection auxiliary liquid sample adding hole and an MAIE fluorescence detection auxiliary liquid sample adding hole which are formed in the chip main body; a plurality of MAIE electrochemical detection sample adding holes and MAIE fluorescence detection sample adding holes are formed in the upper cover, and corresponding openings are formed in the positions, corresponding to the MAIE electrochemical detection auxiliary liquid adding holes and the MAIE fluorescence detection auxiliary liquid adding holes, of the upper cover.

The invention provides a rendering system, a chip, equipment and a rendering method applied to the rendering system, and relates to the technical field of image rendering. The rendering system comprises a rendering pipeline manager, a middle buffer area, M geometric processing pipelines and N pixel processing pipelines, wherein a plurality of data segments divided from an input data stream of the rendering system are allocated to M geometric processing pipelines for processing, and primitive data obtained by processing each data segment is stored in a middle buffer area; the rendering pipeline manager is used for acquiring serial numbers and memory information of the data segments processed by the geometric processing pipeline; the rendering pipeline manager is further used for sending rendering instructions to the N pixel processing pipelines respectively, the rendering instructions comprise the serial numbers and the memory information of the k data segments, k is an integer larger than or equal to 1, and the serial numbers of the k data segments are continuous under the condition that k is larger than 1. According to the method, the image rendering efficiency is improved.

The invention discloses a chip sorting method and a chip sorting system.The chip sorting method comprises the steps that a plurality of wafers are provided, and each wafer comprises a plurality of chips; testing the photoelectric performance of the chip, and recording and storing the serial number of the wafer and the photoelectric performance parameter; carrying out primary sorting according to the photoelectric performance parameters, dividing the chips into first-level sub BIN 1 to first-level sub BIN n, respectively counting the number of the chips and summing, and recording the sum as S1-Sn; setting a first preset value A, comparing Sn with A, and determining a first-level sub-BIN to which the chip belongs according to a comparison result; if Sn is greater than A, the chip in the first-level sub BIN n belongs to the original first-level sub BIN n; if Sn is smaller than or equal to A, the chips in the first-level sub BIN n belong to the sub BIN in the first-level set; for the chips in the primary sub BIN n, selecting the chips to the corresponding blue films according to the BIN, and arranging the chips; and for the chips in the sub BIN in the primary set, the chips are selected to the same blue film for arrangement according to the serial numbers of the wafers to which the chips belong, and secondary sorting is executed. According to the invention, the chip sorting efficiency is improved while the yield of good chips is improved.

Aspects of the disclosure are directed to dynamic workload partitioning. In accordance with one aspect, the disclosure includes a first system on a chip (SOC) configured to commence a use case execution using a baseline workload partition; and a controller coupled to the first SOC, the controller configured to determine if the baseline workload partition should be reallocated using a machine learning (ML) monitoring of system on a chip (SOC) temperatures.

The invention provides a calibration method and device of an energy storage system, the energy storage system, a chip and a program product. The energy storage system comprises a plurality of battery clusters. Acquiring required power and a first priority sequence of the plurality of battery clusters; according to the demand power and the first priority sequence, the charging and discharging power of a plurality of battery clusters is determined, and when the charging and discharging power of a first battery cluster in the plurality of battery clusters is lower than a power threshold value, the first battery cluster is controlled to carry out SOC calibration, and the method comprises the following steps: obtaining SOC difference values among a plurality of battery monomers of the first battery cluster; when the first SOC value is greater than a first threshold value and the SOC difference value is greater than a second threshold value, controlling the first battery cluster to perform SOC low-end standing calibration; and if the first SOC value is greater than the first threshold value and the SOC difference value is less than or equal to the second threshold value, controlling the first battery cluster to perform SOC low-end standing calibration or SOC full-charge calibration so as to improve the safety and reliability of the energy storage system.

The invention provides a half-bridge system, a chip and a preparation method of the half-bridge system, and relates to the technical field of power. The half-bridge system comprises an upper tube and a lower tube which are connected in sequence; the source electrode of the upper tube is connected with the drain electrode of the lower tube; hybrid bonding is arranged between the source electrode of the upper tube and the drain electrode of the lower tube, the source electrode of the upper tube and the drain electrode of the lower tube form interconnection through the hybrid bonding, and the source electrode of the upper tube and the lower tube form an inverted structure through the hybrid bonding. Direct and short-distance interconnection of the source electrode of the upper tube and the drain electrode of the lower tube can be achieved through mixed bonding, and compared with traditional bonding wires and long PCB routing, the current transmission path is greatly shortened, and parasitic inductance can be remarkably reduced. In addition, the inverted structure further optimizes the spatial layout and the connection mode between the devices, reduces additional leads and other parasitic sources, and weakens the source of parasitic inductance generation from the structural level.

The present application provides a three-dimensional stacking technology-based spatio-temporal differential vision sensor chip, and an imaging system. The chip comprises a pixel array, a storage circuit, and spatio-temporal differential and quantization circuits. The pixel array comprises a plurality of pixel units, and a photosensitive circuit is provided in the pixel array. By means of three-dimensional stacking, the pixel array is arranged on a top wafer, and the spatio-temporal differential and quantization circuits are arranged on a same bottom wafer, thereby greatly improving the integration level, effectively reducing the area of the chip, and also relieving the output bandwidth pressure. The photosensitive circuit converts acquired optical signals of the pixel units into analog electrical signals of the pixel units; the storage circuit stores the analog electrical signals or digital electrical signals of the pixel units; and the spatio-temporal differential and quantization circuits perform spatio-temporal differential and quantization processing on the analog electrical signals of the pixel units to obtain digital spatio-temporal differential electrical signals of the pixel units. Thus, the spatial and temporal variations of visual signals can be obtained simultaneously, and an efficient and robust visual representation is formed.

Provided in the embodiments of the present disclosure are a protocol controller, a protocol control method, a chiplet, a system on a chip, and an electronic device. The protocol controller comprises: a first bus interface, which is connected to a system bus, wherein the first bus interface implements an inter-chip interconnect protocol, and a first partial sub-protocol of a peripheral protocol; and a second bus interface, which is connected to the system bus, wherein the second bus interface implements a second partial sub-protocol of the peripheral protocol, and the first partial sub-protocol and the second partial sub-protocol are configured to be implemented by different bus interfaces; and a chiplet uses one of the inter-chip interconnect protocol and the peripheral protocol at the same time.

The invention belongs to the technical field of welding, and discloses a welding robot system, a chip welding method, a chip welding device and a computer storage medium, the welding robot system comprises a calibration module used for bearing a calibration plate, and the calibration plate calibrates a bonding pad to obtain a three-dimensional coordinate of the bonding pad; the mechanical arm is arranged adjacent to the calibration module; the detection module is arranged adjacent to the mechanical arm and the calibration module and is used for collecting sensor data so as to determine a height sequence of welding spots, a temperature field distribution diagram of a welding area and defect characteristics of the to-be-welded chip in combination with the three-dimensional coordinates; and the main control unit is electrically connected with the detection module and / or is in signal connection with the detection module, and is used for carrying out feature fusion and determining welding laser power and a welding speed adjusting instruction according to the obtained multi-sensor fusion features to obtain a preset welding track so as to control the mechanical arm to execute the preset welding track. According to the method, submicron heterogeneous material calibration, thermal interface cooperative control, cross-material process rapid adaptation and multi-modal interface reliability evaluation can be realized.

The invention provides a communication method, device, equipment, system, chip and storage medium, and the method comprises the steps that a first network element judges whether a first terminal and a second terminal are connected with the same satellite or not when the first terminal requests to carry out an IMS call with the second terminal, the satellite comprises a first UPF, and the first UPF is connected with the second terminal; and under the condition that the first terminal and the second terminal are determined to be connected with the same satellite, an indication message is sent to the second network element, and the indication message is used for indicating that the first terminal and the second terminal meet the condition of performing the IMS call through the satellite. Therefore, the second network element can conveniently know that the first terminal and the second terminal meet the condition of performing the IMS call through the satellite through the indication information, so that the first terminal and the second terminal can directly perform the IMS call through the satellite; the transmission time delay of the first terminal and the second terminal during the IMS call through the satellite communication network is reduced, and the call efficiency between the first terminal and the second terminal is improved.

In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

Systems, methods, and apparatuses to low-latency page decompression and compression acceleration are described. In one embodiment, a system on a chip (SoC) includes a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core, cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit, and in response to a second descriptor sent from the hardware processor core separately from the first descriptor, cause the decompressed data to be written from the buffer to memory external to the accelerator circuit by the direct memory access circuit.

A system on a chip for enabling communication between a building management system (BMS) device and a BMS network. The system on a chip includes a device interface, a network interface, and a processing circuit. The device interface is configured to connect the system on a chip to the BMS device via a serial communication link. The network interface configured to connect the system on a chip to the BMS network. The processing circuit is configured to identify and update an attribute of an equipment object associated with the BMS device that corresponds to a command received from the BMS network via the network interface and transmit a message to the BMS device via the device interface using the updated attribute of the equipment object.

Eyewear devices that include two SoCs that share processing workload. Instead of using a single SoC located either on the left or right side of the eyewear devices, the two SoCs have different assigned responsibilities to operate different devices and perform different processes to balance workload. In one example, the eyewear device utilizes a first SoC to operate the OS, a first color camera, a second color camera, a first display, and a second display. A second SoC is configured to run computer vision (CV) algorithms, visual odometry (VIO), tracking hand gestures of the user, and providing depth from stereo. This configuration provides organized logistics to efficiently operate various features, and balanced power consumption.

The invention relates to the technical field of data encryption, and discloses a data encryption device, a memory encryption and decryption system and a chip. A password root output end; the key generation circuit is used for generating an n-bit first key and an n-bit second key; the data encryption logic circuit comprises a four-round encryption module, a four-round encryption unit in the four-round encryption module comprises an n-bit interleaver, four columns of 64-bit round function components correspondingly arranged on the two sides of the interleaver and two sub-circuits for encrypting residual data and residual keys, and the four-round encryption unit is connected with an address input end, a password root output end and a key generation circuit. And the four-round encryption module is used for performing alignment processing on the memory access address, performing interleaving encryption processing based on the four-round encryption module according to the n-bit alignment address obtained by the alignment processing, the first key and the second key, and generating an n-bit password root, so that the encryption device encrypts the write data according to the password root, and the decryption device decrypts the read data according to the password root.

The invention discloses a data acquisition method, device and system, a chip and electronic equipment, and relates to the technical field of wireless communication, node data acquisition of a communication baseband chip can be realized through hardware, the method comprises the following steps: receiving first frame data and second frame data, the first frame data and the second frame data being continuous data frames; storing the first frame data in a first storage space; and in response to reading at least part of the first frame data, storing the second frame data in a second storage space which is not overlapped with the first storage space. In this way, software participation can be reduced, system overhead can be reduced, and power consumption of system operation can be saved. And for two continuous frames of data, the storage spaces are not overlapped, so that the risk of data coverage caused by software reset is avoided, the error risk caused by excessive intervention of software is released, and the real-time performance of the system is remarkably improved.

Testing a semiconductor can be time-consuming as the chip architecture becomes more complex. Testing the possible scenarios becomes increasingly difficult. Chip quality characteristics relating to the chips on a wafer can be used to estimate a probability or rating relating to bypassing system-level testing (SLT). A chip can bypass SLT if there is a high likelihood of passing SLT. Thousands of chip characteristics can be received from wafer testing, chip probe testing, environmental parameters, factory parameters, and other parameters. A chip quality model can use chip quality characteristics as input to generate chip group and SLT parameters. The chip quality model can be a machine learning model or other types of machine learning systems. The chip group parameter or the SLT parameter can be used to direct the testing path of a chip where some chips can bypass SLT thereby saving production time.