214results about How to "High device yield" patented technology

A method for processing semiconductor devices includes providing a semiconductor substrate. The method includes forming a pad oxide layer overlying the substrate and forming a silicon nitride layer overlying the pad oxide layer. The method includes forming a trench region extending through an entirety of a portion of the silicon nitride layer and extends into a depth of the semiconductor substrate. The method also includes filling the trench region with an oxide material. The oxide material extends from a bottom portion of the trench region to an upper surface of the silicon nitride layer. The method includes planarizing the oxide material and selectively removing the silicon nitride layer to form an isolation structure. A polysilicon material is deposited overlying the isolation structure. The polysilicon material is planarized to expose a top portion of the isolation structure and form a first electrode and a second electrode structures separated by a portion of the isolation structure.

A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.

A method for bonding substrates together. The method includes providing a first substrate comprising a first surface. The first substrate comprises a plurality of first chips thereon. Each of the chips has integrated circuit devices. The first substrate includes a first alignment mark on the first substrate and a second alignment mark on the first substrate. The method also includes providing a second substrate comprising a silicon bearing material and second surface. The second substrate comprising a plurality of second chips thereon. Each of the chips comprises a plurality of mechanical structures. The second substrate has a first silicon based pattern on the second substrate and a second silicon based pattern on the second substrate. The method includes moving the first alignment mark of the first substrate to the first silicon based pattern on the second substrate and aligning the second alignment mark of the first substrate to the second silicon based pattern on the second substrate. A portion of at least one of the first substrate or the second substrate is illuminated with electromagnetic radiation. The method includes detecting a portion of the electromagnetic radiation and using the detected portion of the electromagnetic radiation to align the first substrate with the second substrate. The method also includes coupling the first substrate with the second substrate by contacting the first surface with the second surface and bonding the first surface with the second surface.

A method and structure for fabricating a monolithic integrated CMOS and MEMS device. The method includes providing a first semiconductor substrate having a first surface region and forming one or more CMOS IC devices on a CMOS IC device region overlying the first surface region. The CMOS IC device region can also have a CMOS surface region. A bonding material can be formed overlying the CMOS surface region to form an interface by which a second semiconductor substrate can be joined to the CMOS surface region. The second semiconductor substrate having a second surface region to the CMOS surface region by bonding the second surface region to the bonding material, the second semiconductor substrate comprising one or more first air dielectric regions. One or more free standing MEMS structures can be formed within one or more portions of the processed first substrate.

A plurality of integrated electronic compasses and circuit system. The system includes a semiconductor substrate and one or more CMOS integrated circuits formed on one or more portions of the semiconductor substrate. The system has a plurality of electronic compass devices operably coupled to the one or more CMOS integrated circuits. The plurality of electronic compass devices can be integrated with one or more sensors, MEMS, or other devices.

An improved MEMS transducer apparatus and method is provided. The apparatus has a movable base structure including an outer surface region and at least one portion removed to form at least one inner surface region. At least one intermediate anchor structure is disposed within the inner surface region. The apparatus includes an intermediate spring structure operably coupled to the central anchor structure, and at least one portion of the inner surface region. A capacitor element is disposed within the inner surface region.

A method of manufacturing a multi-substrate semiconductor package. The method includes providing a first substrate with a plurality of first dies present thereon and forming a plurality of electrical contacts on an upper surface of a lateral extension portion of at least one of the plurality of first dies on the first substrate. The method also includes providing a second substrate, the second substrate comprising a plurality of second dies, at least one of the plurality of second dies comprising an interconnect region. Further, the method includes forming a sandwich structure by bonding the second substrate to an upper surface of the first substrate to form an intermediate level within the sandwich structure and separating the dies. The method also includes coupling an electrically conductive structure through the interconnect region of the one second dies to the lateral extension portion of the one first die.

A method for bonding substrate structures. The method includes providing a transparent substrate structure, the transparent substrate structure comprising a face region and an incident light region, providing a spacer structure, the spacer structure comprising a selected thickness of material, the spacer structure having a spacer face region and a spacer device region, and providing a device substrate structure, the device substrate having a device face region and a device backside region. The method further includes applying a first glue material to the spacer face region and bonding the spacer face region to the face region of the transparent substrate structure. The method also includes applying a second glue material to the spacer device region and bonding the spacer device region to the device face region.

A method for fabricating a monolithic integrated electronic device using edge bond pads as well as the resulting device. The method includes providing a substrate having a surface region and forming one or more integrated micro electro-mechanical systems and electronic devices on a first region overlying the surface region. One or more trench structures can be formed within one or more portions of the first region. A passivation material and a conduction material can be formed overlying the first region and the one or more trench structures. The passivation material and the conduction material can be etched to form one or more bonding pad structure. The resulting device can then be singulated within a vicinity of the one or more bond pad structures to form two or more integrated micro electro-mechanical systems and electronic devices having edge bond pads.

A method for forming CMOS integrated circuits. The method forms a blanket layer of silicon dioxide overlying an entirety of the surface region of a first well region and a second well region provided on a semiconductor substrate. The blanket layer of silicon dioxide is overlying the hard mask on the first gate structure and the second gate structure. The blanket layer of silicon dioxide is also overlying a region to be protected. Depending upon the embodiment, the region can be a sidewall spacer structure and portion of an MOS device on a peripheral region of the substrate. Of course, there can be other variations, modifications, and alternatives. The method protects the region to be protected using a masking layer, while the surface region of the first well region and the second well region being exposed. The method selectively removes exposed portions of the blanket layer of silicon dioxide, including the hard mask on the first gate structure and the second gate structure, while exposing a first polysilicon material on the first gate structure and while exposing a second polysilicon material on the second gate structure. The method strips the masking layer. The method also includes forming a silicided layer overlying the first polysilicon material on the first gate structure and the second polysilicon material on the second gate structure, while the region to be protected remains free from the silicided layer.

A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.

A method for manufacturing integrated objects, e.g., electronic devices, biological devices. The method includes providing a holder substrate, which has at least one recessed region, the recessed region having a predetermined shape. The holder substrate has a selected thickness and is characterized as being substantially rigid in shape. The method includes aligning a chip comprising a face and a backside into the predetermined shape of the recessed region and disposing the chip into the recessed region. The chip is secured into the recessed region. The method includes providing a first film of insulating material having a first thickness overlying the face and portions of the holder substrate to attach the chip to a portion of the first film of insulating material and patterning the first film of insulating material to form at least one opening through a portion of the first thickness to a contact region on the face of the chip. The method includes forming a metallization layer overlying the first film of insulating material to couple to the contact region through the one opening and forming a protective layer overlying the metallization layer. The method includes releasing the chip from the holder substrate while maintaining attachment of the chip to the first film of insulating material.

An apparatus for inertial sensing. The apparatus includes a substrate member comprising a thickness of silicon. The apparatus also has a first surface region configured from a first crystallographic plane of the substrate and a second plane region configured from a second crystallographic plane of the substrate. The apparatus has a quartz inertial sensing device coupled to the first surface region, and one or more MEMS inertial sensing devices coupled to the second plane region.