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50 results about "Gigabyte" patented technology

The gigabyte (/ˈɡɪɡəbaɪt, ˈdʒɪɡə-/) is a multiple of the unit byte for digital information. The prefix giga means 10⁹ in the International System of Units (SI). Therefore, one gigabyte is 1000000000bytes. The unit symbol for the gigabyte is GB.

Modular disk memory apparatus with high transfer rate

A modular disk memory apparatus provides a modularly expandable, multi-gigabyte auxiliary memory for a computer or other host electronic device, and includes multiple, parallel serial data channels to maximize bidirectional data transfer rates between the apparatus and the host device. Maximization of READ/WRITE data transfer rates within the apparatus is achieved by utilizing a large number of small hard disk drives, typically eight 2.5-inch drives on each of a plurality of Disk Storage Modules, each including a plug-in printed circuit board capable of holding two 5-+E,fra 1/4+EE inch drives, thereby increasing the maximum data transfer rate per unit volume of the modules by a factor of two. Maximization of bidirectional data transfer rates between the apparatus and host device over that attainable using a single serial data channel such as a coaxial, quadaxial or fiber optic cable, is achieved by parsing or demultiplexing data to be transmitted from a single parallel channel onto p paralleled cables, thereby increasing the maximum transmittal rate by p. Data received over the parallel data channels is multiplexed or concatenated to comprise a data stream on a single parallel channel. Reconstruction data is embedded in data contained in the p parallel data channels specifying the number q of channels employed, where 1</=q</=p thereby configuring the demultiplexer to concatenate that number of data channels onto a single parallel data bus.
Owner:SIGNATEC

Method for the secure and timely delivery of large messages over a distributed communication network

A method for transferring messages between a sending application program and a receiving application program across a distributed communication network (e.g., the Internet) that includes a message source coupled to a message destination. The method includes segmenting a message (e.g., a relatively large message of one gigabyte or more) being received at the message source from the sending application program into a plurality of message segments. While this segmentation is occurring, a common message identifier and a unique sequence number are assigned to each of the plurality of message segments. The method also includes transferring the plurality of message segments from the message source to the message destination, along with the common message identifier and unique sequence number assigned to the plurality of message segments, with at least one of the plurality of message segments being transferred as the message is being received at the message source. In other words, prior to the entire message being received at the message source and segmented, message segments that have already been segmented from the message are transferred (i.e., sent) to the message destination. At the message destination, the plurality of message segments that have been transferred from the message source are assembled into a reassembled message as the plurality of message segments are received at the message destination. At least a portion of the reassembled message is delivered to the receiving application while the assembling is occurring.
Owner:CLOUDPRIME

Error correcting memory access means and method

ActiveUS7149934B2Low costEfficiently utilize error correctingCode conversionCoding detailsData streamByte
As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing costs are significant and will grow as the capacity of the devices grows—the higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. The cost of the testing can be calculated by dividing the amortized cost of the test equipment by the number of devices tested. As memory devices enter the Gigabyte range and larger, the number of devices that can be tested by a given piece of test equipment will go down. As a result, the cost per unit attributable to testing will rise. The present invention is a means and a method for accessing streams of data stored within a memory device so as to minimize the cost of device testing and thereby the cost of the device itself. By incorporating error-correcting bits in the data stream, the individual data bits need not be tested. Then, by accessing the memory locations so as to avoid having error correcting techniques fail due to common memory device faults, testing costs can be significantly reduced while maintaining high device yields. A sequential access of the memory device will access data bits in a somewhat diagonal path across the two-dimensional array. The key to the present invention is that the sequential data stream stored in the device is stored such that sequential access of that data will not dwell on a single (or a small number of) row or column line. In a three or more dimensional array, the sequential data stream stored in the device is stored such that sequential access of that data will not dwell on a single value in a given dimension for which bulk errors are considered likely.
Owner:WESTERN DIGITAL TECH INC

Error correcting memory access means and method

ActiveUS20070028150A1Low costEfficiently utilize error correctingCode conversionCoding detailsData streamTerm memory
As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing costs are significant and will grow as the capacity of the devices grows—the higher the memory's capacity, the more storage locations that must be tested, and the longer the testing operation will take. The cost of the testing can be calculated by dividing the amortized cost of the test equipment by the number of devices tested. As memory devices enter the Gigabyte range and larger, the number of devices that can be tested by a given piece of test equipment will go down. As a result, the cost per unit attributable to testing will rise. The present invention is a means and a method for accessing streams of data stored within a memory device so as to minimize the cost of device testing and thereby the cost of the device itself. By incorporating error-correcting bits in the data stream, the individual data bits need not be tested. Then, by accessing the memory locations so as to avoid having error correcting techniques fail due to common memory device faults, testing costs can be significantly reduced while maintaining high device yields. A sequential access of the memory device will access data bits in a somewhat diagonal path across the two-dimensional array. The key to the present invention is that the sequential data stream stored in the device is stored such that sequential access of that data will not dwell on a single (or a small number of) row or column line. In a three or more dimensional array, the sequential data stream stored in the device is stored such that sequential access of that data will not dwell on a single value in a given dimension for which bulk errors are considered likely.
Owner:WESTERN DIGITAL TECH INC

FC HBA (fiber channel host bus adapter) based on SSD (solid state disk) cache and design method thereof

The invention discloses an FC HBA (fiber channel host bus adapter) based on an SSD (solid state disk) cache and a design method thereof. An SSD memory is used as the buffer memory of the FC HBA, a server is communicated with the FC HBA through a PCIe (peripheral component interface express) interface, a memory device is communicated with the FC HBA through an FC interface; and the SSD buffer memory stores the transmitted data in a buffer manner, and the transmitted data includes the data transmitted between the server and the memory device, and the data transmitted between the memory device and another memory device. The SSD memory is used as the data cache of the FC HBA, namely a large-capacity high-speed buffer memory is provided for the FC HBA, the capacity of the buffer memory can reach 100 GB (gigabyte)-2TB(trillionbyte), or even a larger range. The server only needs to access to the SSD buffer memory in the FC HBA to obtain required data without accessing to the memory device, so that the data delay between the server and the memory device is reduced, and the IOPS (input / output operations per second) of the system is effectively improved. Besides, the SSD memory is used as the cache of the FC HBA, so that the transfer rate of stored network data is effectively improved.
Owner:无锡北方数据计算股份有限公司

Industrial robot three-dimensional real-time and high-precision positioning device and method

The invention discloses an industrial robot three-dimensional real-time and high-precision positioning device and method. The device comprises an industrial robot system, an industrial computer and a camera unit, wherein the industrial computer is connected with the industrial robot controller through a first gigabyte Ethernet, and then is connected into the industrial robot system, the industrial computer is connected with the camera unit through a second gigabyte Ethernet, and the camera unit is an active camera unit or a multi-camera unit. The method includes the following steps that: the position state of the camera unit is set according to the positions of a feature point and an actual target point; a mapping relationship of three-dimensional coordinates in a robot space and two-dimensional coordinates in a camera space is established; the position of a target point in the three-dimensional robot space is obtained, the industrial robot controller sends a command so as to control a robot to move to the target point and position the robot on the target point; and finally, the robot is positioned on the actual target point through judgment. The industrial robot three-dimensional real-time and high-precision positioning device and method of the invention have the advantages of no need for calibration, high precision, wide field of vision and high real-time performance.
Owner:南京赫曼机器人自动化有限公司

Management system and method of processor last level high-speed buffer

The invention discloses a management system and a method of processor last level high-speed buffer. The management system of the processor last level high-speed buffer comprises recording a couple of an access block and a discharge block every time when a last level buffer fails to access by a gigabyte (GB) monitor, switching a replacement pattern or a bypass pattern by studying behavior guide of an optimal bypass algorithm, wherein action of the optimal bypass algorithm is formed through actions of selection and adoption of a replacement method and a bypass method according to conditions of the optimal bypass algorithm occurred in follow-up access of the last level high-speed buffer in an accumulation mode; judging a first condition which satisfies the optimal bypass algorithm according to an access block tag and a discharge block tag of a present record in once occurrence of failure of the last level high-speed buffer, and adopting the replacement method when reusable distance of the access block is smaller than the reusable distance of the discharge block, and otherwise, adopting the bypass method. Bypass and replacement are treated as the same strategy to be switched in the management system and the method of the processor last level high-speed buffer.
Owner:北京北大众志微系统科技有限责任公司

Method for fast scanning dirty page bitmap of full-virtualization virtual machine

The invention discloses a method for fast scanning a dirty page bitmap of a full-virtualization virtual machine. The method comprises the following steps: a zone bit initialization phase, allocating a first class zone bit and a second class zone bit for 4 gigabyte (GB) memory space of the full-virtualization virtual machine in Xen address space, and meanwhile, initializing the first class zone bit and the second class zone bit into zero, wherein the number of the first class zone bit is 4GB/128MB=32, and the number of the second class zone bit is one; a zone bit setting phase, reading an address in a second class page table entry of an Xen and setting the values of the first class zone bit and the second class zone bit according to the address; and a zone bit scanning phase, scanning the dirty page bitmap of the full-virtualization virtual machine according to the values of the first class zone bit and the second class zone bit so as to obtain a dirty page number. According to the method for fast scanning the dirty page bitmap of the full-virtualization virtual machine, the time for suspending the virtual machine caused by scanning of the dirty page bitmap in a dynamic migration or a Remus HA system of the virtual machine is reduced, so that the calculated performance and the service quality of the virtual machine are enhanced.
Owner:HUAZHONG UNIV OF SCI & TECH

Global system for mobile communications (GSM) double frequency co-located station cell resource leveling method based on gigabyte (Gb) interface signaling

The invention discloses a global system for mobile communications (GSM) double frequency co-located station cell resource leveling method based on gigabyte (Gb) interface signaling. According to the method, double frequency co-located station coverage cells in a GSM network are screened out according to a base station foundation database at first; then, Gb interface signaling data is collected, rate values under the co-located station double frequency cells are counted, and the configuration number of packet data channels (PDCH) under the condition that the co-located station double frequency cells meet requirements of different user sensing is calculated according to the rate value under the co-located station double frequency cells; and at last, the calculated PDCH number is compared with PDCH configuration of an existing network, and configuration for co-located station double frequency cells with unbalanced business is achieved. According to the method, cell resource balance is achieved through reasonable configuration for cell PDCH resources, configuration information of the cells is just changed, conditions of reselection parameters, coverage and power are not changed, influences on network quality, performance and test indexes of a speech network are little, and reasonable configuration for the cells can be achieved according to the level of user sensing.
Owner:BEIJING TUOMING COMM TECH
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