221 results about "Signal trace" patented technology

The embodiment of the invention provides a flexible circuit board and electronic equipment, relates to the technical field of signal transmission, and is used for relieving the problem of relatively high signal loss of an FPC (Flexible Printed Circuit) caused by electromagnetic shielding. The flexible circuit board may have a first region and a second region. A reference layer of the flexible circuit board is located in the first area, and the reference layer and the signal layer are stacked. The first shielding layer is located in the first area, and the first shielding layer is stacked on the side, away from the reference layer, of the signal layer. The second shielding layer is located in the second area, and the second shielding layer and the signal layer are stacked. The first grounding wire is electrically connected with the first shielding layer and the reference layer. The first grounding wire is also electrically connected with the second shielding layer. A backflow signal of a signal transmitted by the signal line in the signal layer can flow through the first grounding line from the second shielding layer in the second area, and respectively flows into the first shielding layer and the reference layer in the first area.

A high performance (HP) standard cell architecture for logic cells used in a semiconductor device or product. An example semiconductor device includes a plurality of cells surrounded by a cell boundary, and a backside power delivery network (PDN) routed to the plurality of cells. At least one cell of the plurality of cells has an arrangement of transistors within the cell boundary, the arrangement of transistors coupled together to generate an output signal at an output signal node. There is a metal 0 layer above the arrangement of transistors, the metal 0 layer includes one or more input signal traces and an output signal trace. The output signal trace and the input signal traces are substantially parallel inside the cell boundary and have a first width near the cell boundary; the output signal trace has a region of a wider metal 0 inside the cell boundary.

Receiving a compute express link (CXL) packet at a link controller of an input / output (I / O) chip, and responsively terminating the CXL packet to generate a load / store memory transaction having a plurality of parameters comprising a host physical address (HPA), and a logical device ID (LD_ID), translating, using a forwarding engine, the HPA into a device physical address (DPA) based on the LD_ID, and appending network-on-chip (NoC) routing information to the load / store memory transaction, outputting, the load / store memory transaction and the NoC routing information to a plurality of signal traces on a printed circuit board (PCB), receiving the load / store memory transaction and the NoC routing information, and routing, using a NoC, the load / store memory transaction based on the NoC routing information to a destination port on the NoC, the NoC comprising (i) memory controller ports, (ii) edge processing unit (EPU) ports, and (iii) die-to-die interface ports.

A layout of signal traces includes a first set of signal traces and a second set of signal traces that are used for transmitting a first differential signal and a second differential signal respectively. Each set of signal traces includes a first part, a second part, and a third part along the direction of signal transmission. Different parts of the same signal trace as a whole is not straight. All the first parts are in a first signal layer and parallel. The second parts of the two sets of signal traces are in a second signal layer and the first signal layer, respectively, and are across each other. The second part of the first / second set of signal traces is coupled with the first and third parts of the first / second set of signal traces. All the third parts are in the first signal layer and parallel.

A computer-implemented method includes: accessing ground-force signal traces measured at each source location when applying a pilot sweep signal characterized by a sweeping instantaneous frequency that includes a fundamental component, wherein each ground-force signal trace comprises a fundamental mode signal component as well as at least one harmonic mode signal component; obtaining an analytic function representation for the pilot sweep signal and each ground-force signal trace, wherein the analytic function representation comprises a phase portion; establishing a matrix representation characteristic of the phase portion of the analytic function representation for the fundamental component in the ground-force signal, and wherein the matrix representation is size limited; retrieving, from the analytic function representation for each ground-force signal trace and after inverting the matrix representation, the fundamental mode signal component of the ground-force signal trace; and providing the retrieved fundamental mode signal component of each ground-force signal trace for subsequent data processing.

The utility model provides a circuit board structure, and relates to the technical field of circuit boards. The structure comprises a circuit board body, at least two resistance-capacitance devices and at least four signal wires, the circuit board body is provided with at least two signal holes, at least two backflow ground holes and at least two bonding pad assemblies, each bonding pad assembly comprises at least two bonding pads which are arranged in sequence, the same resistance-capacitance device is correspondingly connected with two adjacent bonding pads in the same bonding pad assembly, the signal wire is correspondingly connected with the bonding pads connected with the resistance-capacitance device, and the signal wire is connected with the signal wire. The through bonding pad assembly and the signal hole are both located between the at least two backflow ground holes. The quality and stability of signal transmission can be enhanced through the signal hole, the backflow ground hole provides a plurality of backflow paths, in high-speed signal transmission and high-frequency application, signal delay and distortion are reduced, the signal quality is improved, the device is suitable for high-speed signal transmission, such as 32Gbps, and the bonding pad assembly, the signal hole and the backflow ground hole are compact in layout structure, small in occupied space and high in reliability. And the high-density arrangement requirement is met.

The invention provides a tumor electric field treatment device and an electrode patch thereof, and the electrode patch comprises an electrode array which comprises twenty electrode units and sixteen temperature sensors. The sixteen temperature sensors are located on the edge and the center of the electrode array and corresponding electrode units located in the middle of the edge and the center respectively in the space structure. The sixteen temperature sensors are arranged on a circuit in four rows and four columns, a flexible circuit board of the electrode array is provided with four grounding traces and four signal traces, and the grounding traces are arranged on the back face of the flexible circuit board and electrically connected with the grounding ends of the temperature sensors in the corresponding row respectively. And the four paths of signal traces are also arranged on the back surface of the flexible circuit board and are electrically connected with the signal ends of the corresponding columns of temperature sensors respectively. According to the tumor electric field treatment device and the electrode patch thereof, the temperature sensors are arranged on part of the electrode units at different positions of the electrode array, so that comprehensive temperature measurement can be realized, and wiring of conductive traces on the flexible circuit board can be simplified.

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display, the display panel comprises a display area and a dam area, and the display panel comprises a substrate, at least one conductive layer, an insulating layer and a touch layer. The at least one conductive layer is located on one side of the substrate, and the conductive layer comprises signal wires; the insulating layer is located on the side, away from the substrate, of the at least one conductive layer, and the thickness of the insulating layer in the display area is larger than that of the insulating layer in the dam area; the touch layer is located on the side, away from the substrate, of the insulating layer and comprises touch wires, and the touch wires are located in the display area. According to the display panel, the thickness of the insulating layer in the display area is set to be larger than that of the insulating layer in the dam area, the risk that the metal wires in the dam area are damaged can be reduced while signal interference of the signal wires in the conductive layer on the touch wires in the touch layer is reduced, and therefore the touch effect and the display effect of the display panel can be improved.

The present disclosure relates to a display panel, a display area of the display panel has a middle area and an edge area located outside the middle area, the display panel comprises a plurality of data lines, a plurality of first power signal lines and a plurality of second power signal lines located in the display area, wherein each data line located in the edge area is led to the middle area through a signal trace, at least part of the signal trace corresponds to the position of the first power signal line, the conductive layer where the signal trace is located further comprises a dummy pattern, the dummy pattern is arranged separately from the signal trace, and at least part of the dummy pattern is electrically connected with the second power signal line.

A display substrate includes a first display area (A1). The first display area (A1) includes a plurality of display island areas (A11) arranged in an array and light-transmissive areas (A121, A122) between adjacent display island areas (A11). The display island area (A11) includes a plurality of first pixel circuits (11) and a plurality of first light-emitting elements (13) disposed on a substrate. At least one first pixel circuit (11) is electrically connected with at least one first light-emitting element (13) and configured to drive the at least one first light-emitting element (13) to emit light. The first pixel circuits (11) in adjacent display island areas (A11) are connected by a plurality of first signal traces in a first direction (X), and the first pixel circuits (11) in adjacent display island areas (A11) are connected by a plurality of second signal traces in a second direction (Y). The material of the plurality of second signal traces includes a transparent conductive material, or the material of the plurality of first signal traces and the plurality of second signal traces both includes a metal material.

A system and method for FPGA-based emulation for verification of an RTL design. A first part of an FPGA is configured to realize user logic according to user RTL received by a network, and a second part of the FPGA is configured to realize control and interface logic that enables remote control and interaction with the user logic. The first portion of the FPGA may further realize emulated off-chip components and interfaces to real off-chip components to provide a realistic environment for the user logic. The second portion of the FPGA may further realize logic-analyzer logic for probing internal signals of the user logic and for capturing and storing signal traces. Memory elements that are coupled to the user logic are expunged at the end of an emulation session prevent data leaks between sessions.

A method includes grouping signal traces based on signal trace characteristics. The method includes sampling at least one of a set of signal traces to a uniform time sequence and generating an image including visual indicators associated with the set of signal traces with signal trace characteristics. Each visual indicator corresponds to a signal characteristic of a respective signal trace of the set of signal traces and a time value based on the uniform time sequence. The method includes detecting a defect in operation of one or more components of manufacturing equipment based on a deviation of one of the visual indicators of the image. The method includes classifying the defect based on the respective signal trace corresponding to the image.

A display panel and a display device are provided. A first entity portion is connected with a data line and a signal trace, and a first gap is provided between the first entity portion and a first dummy portion. The display panel includes a first metal layer and a second metal layer that are stacked. The first entity portion includes a first portion located on the first metal layer. The first dummy portion includes a third portion located on the first metal layer. The first portion includes a first end of the first entity portion, and the third portion includes a first end of the first dummy portion.

The application discloses a display panel and a display device, and relates to the technical field of display. In the display panel, a pixel circuit and a first signal trace are connected through a first connection position, a second signal trace is connected through a second connection position, and a pixel electrode is connected through a third connection position. Moreover, the orthographic projection of a first opening area in a common electrode on a substrate covers the orthographic projection of each connection position on the substrate, so that the coupling capacitance of the conductive film layer at the common electrode and each connection position can be avoided, and the abnormal increase of the coupling capacitance at each connection position can be avoided. Therefore, the display panel can be prevented from generating a heating phenomenon, and the yield of the display panel can be ensured.

The application discloses a kind of SMD high-speed connector differential signal wire generation device, obtain the component requirement information of high-speed connector, obtain the via requirement information of high-speed signal via, differential signal wire is divided into fixed several section line segment, and the parameter of each line segment is set, the parameter of each line segment of differential signal wire, component requirement information, via requirement information is substituted into simulation program, input simulation requirement, obtain simulation result, according to simulation result analysis obtains the parameter of each line segment of differential signal wire, component requirement information, via requirement information, call the function module of PCB design program, automatically generate differential signal wire.The application provides a kind of SMD high-speed connector differential signal wire generation device, greatly reduce the workload of PCB designer, improve the generation efficiency of differential signal wire and the precision of differential signal wire.

The application provides a display panel and a display device. The display panel comprises a substrate and a binding assembly. The substrate comprises a main body part and a bending part connected with the main body part. Two ends of the binding assembly are electrically connected with the main body part and the bending part respectively. The bending part and one end of the binding assembly away from the main body part are bent to the back of the main body part. By connecting part of signal traces in the main body part of the substrate with the bending part through the binding assembly, the number of traces that need to be electrically connected with the bending part is reduced, and the size of the frame area of the display panel is reduced, and the narrow frame effect is improved.

A semiconductor wiring board includes a first wiring layer, a second wiring layer, a plurality of first signal traces, and a plurality of second signal traces. The second circuit layer and the first circuit layer are arranged in parallel. A part of the plurality of first signal wires and a part of the plurality of second signal wires are arranged on the first circuit layer, and the other part of the plurality of first signal wires and the other part of the plurality of second signal wires are arranged on the second circuit layer. A part of the plurality of first signal wires and a part of the plurality of second signal wires are arranged on the first circuit layer along the first direction, and the other part of the plurality of first signal wires and the other part of the plurality of second signal wires are arranged on the second circuit layer along the first direction. Through the circuit layout of the semiconductor wiring board, a first bit group signal transmitted by the first signal wire and a second bit group signal transmitted by the second signal wire can be transmitted between the adjacent first circuit layer and the second circuit layer, so that crosstalk between the first signal wire and the second signal wire is reduced.

An embodiment of the present application discloses a display panel and a mobile terminal, wherein the display panel includes a substrate, a driving circuit, multiple test terminals, multiple test traces, a control terminal group, and a protective function layer, wherein the driving circuit is arranged on the substrate and includes multiple binding terminals and multiple signal traces, a binding terminal is connected to a signal trace; a test terminal is connected to the signal trace through a test trace, and at least one control switch is connected to the test trace; the control terminal of the control terminal group is connected to the control end of the control switch; the protective function layer is arranged on the substrate, the driving circuit, and the test trace, and covers the driving circuit and the control switch.

A leak sensor for monitoring a liquid cooing assembly of an information handling system includes a flexible dielectric substrate. A reference trace is formed on the flexible dielectric substrate. A first signal trace is formed on the flexible substrate substantially in parallel with a first portion of the reference trace. A second signal trace formed on the flexible substrate substantially in parallel with a second portion of the reference trace. The first and second signal traces are separated by insulation into separate regions on the flexible dielectric substrate. Electrically driving the first and second signal traces induces voltages on the first and second signal traces, the voltages correlated with an amount of liquid within the separate regions.

The present invention discloses a display panel and display device. By ensuring that the orthographic projections of each effective light-emitting area on a substrate overlap with the orthographic projections of signal traces on the substrate, and that the first overlapping region is non-linear, light emitted from the effective light-emitting area can form optical interference through the signal traces in the first overlapping region. Consequently, when the display panel is used in a 3D display device, moiré patterns can be reduced, enhancing the display quality.

The present disclosure provides a display substrate and a preparation method thereof, and belongs to the technical field of display. The display substrate of the present disclosure comprises: a substrate, having a connecting via hole penetrating through the thickness direction thereof; the substrate comprises a first surface and a second surface oppositely arranged along the thickness direction thereof; a pixel driving circuit arranged on the first surface; a signal trace arranged on the second surface; a connecting structure arranged in the connecting via hole, and the connecting structure electrically connects the signal trace and the pixel driving circuit; wherein part of the connecting via hole is filled with the connecting structure.

The invention relates to the technical field of power electronics, in particular to a semiconductor device, a vehicle-mounted charger and a vehicle wherein the semiconductor device comprises: a substrate, a power circuit, a power pin (102) and a signal pin (101); the power circuit is arranged on the substrate; the power pin (102) and the signal pin (101) are connected with a power circuit; the signal pins (101) arranged on the same side edge of the substrate are arranged in groups, and the distance between the signal pins (101) in different groups is larger than the distance between the power pins (102). According to the embodiment of the invention, the power line and the signal line in the semiconductor device are separated, so that the cross line and mutual interference of the power line and the signal line are avoided; and the problem that wiring is difficult due to many pins on the side of the signal pin (101) is avoided.

A display panel and a display device are provided. A first entity portion is connected with a data line and a signal trace, and a first gap is provided between the first entity portion and a first dummy portion. The display panel includes a first metal layer and a second metal layer that are stacked. The first entity portion includes a first portion located on the first metal layer. The first dummy portion includes a third portion located on the first metal layer. The first portion includes a first end of the first entity portion, and the third portion includes a first end of the first dummy portion.

The invention relates to the technical field of defect detection, in particular to a solar water heater PCB control panel structure optimization method and system. The method comprises the steps of obtaining thermal parameters of all components, calculating time weighted thermal power, generating a board heat source distribution diagram, evaluating condensation risks of all areas of a board according to the heat source distribution diagram and a preset installation inclination angle of a PCB control board, generating a condensation risk distribution diagram, constructing an electromagnetic coupling model between a key signal wire and a power supply wire, basic electromagnetic interference intensity is calculated, condensation risk distribution on the key signal wiring path is extracted, the basic electromagnetic interference intensity is corrected to obtain a comprehensive risk assessment value, and wiring is optimized according to a priority strategy when the comprehensive risk assessment value is larger than a preset threshold value. According to the scheme, the condensation risk area of the board can be predicted and quantified, the condensation risk and the electromagnetic interference risk can be associated, and the working reliability of the PCB control board in the damp and hot alternating environment is improved.

A printed circuit board (PCB), vertical conductive structures (VeCSs) for the PCB, and a method of fabricating a printed circuit board (PCB). The VeCS includes a VeCS slot at least partially defined in a dielectric substrate. A vertical signal trace is positioned on a first side of the VeCS slot and a vertical reference trace is positioned on a second side of the VeCS slot opposite the vertical signal trace. The VeCS has a predetermined impedance. A plurality of signal ground planes is positioned at a respective predetermined distance from the vertical signal trace. Each signal ground plane defines a cutout.

An audio kill switch provides a noiseless passive cessation of an audio signal. A printed circuit board is joined to an upper shell and has a plurality of interlaced three mil copper signal and ground traces from a center signal trace and outer grounding ring respectively, with three mil spaces between traces interlaced in a way to gradually shunt the signal to ground over several milliseconds when contact between them is made by the conductive rubber button. A target pad is arranged on the center of the printed circuit board. An outer shell is surrounding the printed circuit board. A conductive rubber button is joined to a spring. A nylon outer sleeve is arranged against the conductive rubber button. A spring-loaded connector is arranged against the target pad and joined to a rubber sleeve.

A radiating element for a base station antenna comprises a feed stalk printed circuit board and a dipole radiator printed circuit board mounted on the feed stalk printed circuit board. The feed stalk printed circuit board includes a first ground line that includes a first integrated parallel LC circuit, a second ground line that includes a second integrated parallel LC circuit, a first signal trace that extends through an opening in the dipole radiator printed circuit board, and a second signal trace.

Provided is a display substrate, comprising: a base substrate; a driving circuit layer, which comprises a plurality of first pixel driving circuit groups located in a first display region; a first conductive layer, which comprises a plurality of first trace groups, wherein each first trace group comprises a first power source signal line and two trace sub-groups respectively located on two sides of the first power source signal line in a first direction, and each trace sub-group comprises a first signal trace and a second signal trace; and a second conductive layer, which is located between the driving circuit layer and the first conductive layer, and comprises a plurality of third signal traces and a plurality of fourth signal traces, wherein the first power source signal lines are electrically connected to a pixel driving circuit unit by means of the third signal traces, the plurality of fourth signal traces include a plurality of first adapter traces, the plurality of second signal traces include a plurality of second adapter traces located in a second display region, and the second adapter traces are used for receiving data signals provided by binding pads and connecting the data signals to the first pixel driving circuit groups by means of the first adapter traces and the trace sub-groups.

This application provides a display panel and a display device. The display panel includes a display area and a non-display area adjacent to the display area. The bezel area includes a substrate and signal traces, a planarization layer, lead traces, and an encapsulation layer sequentially stacked on the substrate. The encapsulation layer includes a first inorganic layer disposed on the lead traces. The display area includes a substrate, a planarization layer, and an anode located on the side of the planarization layer away from the substrate. The lead traces extend from the side of the anode into the bezel area and are connected to the signal traces. This application provides a barrier layer between the lead traces and the first inorganic layer. The orthographic projection of the barrier layer on the lead traces covers the orthographic projection of the first inorganic layer on the lead traces, thereby avoiding the bombardment damage to the lead traces by high-energy plasma when the first inorganic layer is fabricated using plasma-enhanced chemical vapor deposition in the prior art, and thus avoiding the phenomenon of uneven thickness of the first inorganic layer.

A cross-dipole radiating element includes a feed shank having a base and a distal end positioned forward of the base; a first dipole radiator mounted at the distal end of the feed handle, the first dipole radiator comprising a first dipole arm and a second dipole arm; and a second dipole radiator mounted at the distal end of the feed handle, the second dipole radiator comprising a third dipole arm and a fourth dipole arm. The feed stem includes a first ground line and a first signal trace at least partially overlapping the first ground line. The first ground line includes at least a first widened conductive segment, a second widened conductive segment, and a third widened conductive segment, where the first widened conductive segment and the second widened conductive segment are connected by a first narrowed conductive trace, and the second widened conductive segment and the third widened conductive segment are connected by a second narrowed conductive trace.