169 results about "Signal trace" patented technology

The embodiment of the invention provides a flexible circuit board and electronic equipment, relates to the technical field of signal transmission, and is used for relieving the problem of relatively high signal loss of an FPC (Flexible Printed Circuit) caused by electromagnetic shielding. The flexible circuit board may have a first region and a second region. A reference layer of the flexible circuit board is located in the first area, and the reference layer and the signal layer are stacked. The first shielding layer is located in the first area, and the first shielding layer is stacked on the side, away from the reference layer, of the signal layer. The second shielding layer is located in the second area, and the second shielding layer and the signal layer are stacked. The first grounding wire is electrically connected with the first shielding layer and the reference layer. The first grounding wire is also electrically connected with the second shielding layer. A backflow signal of a signal transmitted by the signal line in the signal layer can flow through the first grounding line from the second shielding layer in the second area, and respectively flows into the first shielding layer and the reference layer in the first area.

A high performance (HP) standard cell architecture for logic cells used in a semiconductor device or product. An example semiconductor device includes a plurality of cells surrounded by a cell boundary, and a backside power delivery network (PDN) routed to the plurality of cells. At least one cell of the plurality of cells has an arrangement of transistors within the cell boundary, the arrangement of transistors coupled together to generate an output signal at an output signal node. There is a metal 0 layer above the arrangement of transistors, the metal 0 layer includes one or more input signal traces and an output signal trace. The output signal trace and the input signal traces are substantially parallel inside the cell boundary and have a first width near the cell boundary; the output signal trace has a region of a wider metal 0 inside the cell boundary.

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display, the display panel comprises a display area and a dam area, and the display panel comprises a substrate, at least one conductive layer, an insulating layer and a touch layer. The at least one conductive layer is located on one side of the substrate, and the conductive layer comprises signal wires; the insulating layer is located on the side, away from the substrate, of the at least one conductive layer, and the thickness of the insulating layer in the display area is larger than that of the insulating layer in the dam area; the touch layer is located on the side, away from the substrate, of the insulating layer and comprises touch wires, and the touch wires are located in the display area. According to the display panel, the thickness of the insulating layer in the display area is set to be larger than that of the insulating layer in the dam area, the risk that the metal wires in the dam area are damaged can be reduced while signal interference of the signal wires in the conductive layer on the touch wires in the touch layer is reduced, and therefore the touch effect and the display effect of the display panel can be improved.

The present disclosure relates to a display panel, a display area of the display panel has a middle area and an edge area located outside the middle area, the display panel comprises a plurality of data lines, a plurality of first power signal lines and a plurality of second power signal lines located in the display area, wherein each data line located in the edge area is led to the middle area through a signal trace, at least part of the signal trace corresponds to the position of the first power signal line, the conductive layer where the signal trace is located further comprises a dummy pattern, the dummy pattern is arranged separately from the signal trace, and at least part of the dummy pattern is electrically connected with the second power signal line.

A display substrate includes a first display area (A1). The first display area (A1) includes a plurality of display island areas (A11) arranged in an array and light-transmissive areas (A121, A122) between adjacent display island areas (A11). The display island area (A11) includes a plurality of first pixel circuits (11) and a plurality of first light-emitting elements (13) disposed on a substrate. At least one first pixel circuit (11) is electrically connected with at least one first light-emitting element (13) and configured to drive the at least one first light-emitting element (13) to emit light. The first pixel circuits (11) in adjacent display island areas (A11) are connected by a plurality of first signal traces in a first direction (X), and the first pixel circuits (11) in adjacent display island areas (A11) are connected by a plurality of second signal traces in a second direction (Y). The material of the plurality of second signal traces includes a transparent conductive material, or the material of the plurality of first signal traces and the plurality of second signal traces both includes a metal material.

A system and method for FPGA-based emulation for verification of an RTL design. A first part of an FPGA is configured to realize user logic according to user RTL received by a network, and a second part of the FPGA is configured to realize control and interface logic that enables remote control and interaction with the user logic. The first portion of the FPGA may further realize emulated off-chip components and interfaces to real off-chip components to provide a realistic environment for the user logic. The second portion of the FPGA may further realize logic-analyzer logic for probing internal signals of the user logic and for capturing and storing signal traces. Memory elements that are coupled to the user logic are expunged at the end of an emulation session prevent data leaks between sessions.

A method includes grouping signal traces based on signal trace characteristics. The method includes sampling at least one of a set of signal traces to a uniform time sequence and generating an image including visual indicators associated with the set of signal traces with signal trace characteristics. Each visual indicator corresponds to a signal characteristic of a respective signal trace of the set of signal traces and a time value based on the uniform time sequence. The method includes detecting a defect in operation of one or more components of manufacturing equipment based on a deviation of one of the visual indicators of the image. The method includes classifying the defect based on the respective signal trace corresponding to the image.

A display panel and a display device are provided. A first entity portion is connected with a data line and a signal trace, and a first gap is provided between the first entity portion and a first dummy portion. The display panel includes a first metal layer and a second metal layer that are stacked. The first entity portion includes a first portion located on the first metal layer. The first dummy portion includes a third portion located on the first metal layer. The first portion includes a first end of the first entity portion, and the third portion includes a first end of the first dummy portion.

The application discloses a display panel and a display device, and relates to the technical field of display. In the display panel, a pixel circuit and a first signal trace are connected through a first connection position, a second signal trace is connected through a second connection position, and a pixel electrode is connected through a third connection position. Moreover, the orthographic projection of a first opening area in a common electrode on a substrate covers the orthographic projection of each connection position on the substrate, so that the coupling capacitance of the conductive film layer at the common electrode and each connection position can be avoided, and the abnormal increase of the coupling capacitance at each connection position can be avoided. Therefore, the display panel can be prevented from generating a heating phenomenon, and the yield of the display panel can be ensured.

The application discloses a kind of SMD high-speed connector differential signal wire generation device, obtain the component requirement information of high-speed connector, obtain the via requirement information of high-speed signal via, differential signal wire is divided into fixed several section line segment, and the parameter of each line segment is set, the parameter of each line segment of differential signal wire, component requirement information, via requirement information is substituted into simulation program, input simulation requirement, obtain simulation result, according to simulation result analysis obtains the parameter of each line segment of differential signal wire, component requirement information, via requirement information, call the function module of PCB design program, automatically generate differential signal wire.The application provides a kind of SMD high-speed connector differential signal wire generation device, greatly reduce the workload of PCB designer, improve the generation efficiency of differential signal wire and the precision of differential signal wire.

The application provides a display panel and a display device. The display panel comprises a substrate and a binding assembly. The substrate comprises a main body part and a bending part connected with the main body part. Two ends of the binding assembly are electrically connected with the main body part and the bending part respectively. The bending part and one end of the binding assembly away from the main body part are bent to the back of the main body part. By connecting part of signal traces in the main body part of the substrate with the bending part through the binding assembly, the number of traces that need to be electrically connected with the bending part is reduced, and the size of the frame area of the display panel is reduced, and the narrow frame effect is improved.

A semiconductor wiring board includes a first wiring layer, a second wiring layer, a plurality of first signal traces, and a plurality of second signal traces. The second circuit layer and the first circuit layer are arranged in parallel. A part of the plurality of first signal wires and a part of the plurality of second signal wires are arranged on the first circuit layer, and the other part of the plurality of first signal wires and the other part of the plurality of second signal wires are arranged on the second circuit layer. A part of the plurality of first signal wires and a part of the plurality of second signal wires are arranged on the first circuit layer along the first direction, and the other part of the plurality of first signal wires and the other part of the plurality of second signal wires are arranged on the second circuit layer along the first direction. Through the circuit layout of the semiconductor wiring board, a first bit group signal transmitted by the first signal wire and a second bit group signal transmitted by the second signal wire can be transmitted between the adjacent first circuit layer and the second circuit layer, so that crosstalk between the first signal wire and the second signal wire is reduced.

An embodiment of the present application discloses a display panel and a mobile terminal, wherein the display panel includes a substrate, a driving circuit, multiple test terminals, multiple test traces, a control terminal group, and a protective function layer, wherein the driving circuit is arranged on the substrate and includes multiple binding terminals and multiple signal traces, a binding terminal is connected to a signal trace; a test terminal is connected to the signal trace through a test trace, and at least one control switch is connected to the test trace; the control terminal of the control terminal group is connected to the control end of the control switch; the protective function layer is arranged on the substrate, the driving circuit, and the test trace, and covers the driving circuit and the control switch.

A leak sensor for monitoring a liquid cooing assembly of an information handling system includes a flexible dielectric substrate. A reference trace is formed on the flexible dielectric substrate. A first signal trace is formed on the flexible substrate substantially in parallel with a first portion of the reference trace. A second signal trace formed on the flexible substrate substantially in parallel with a second portion of the reference trace. The first and second signal traces are separated by insulation into separate regions on the flexible dielectric substrate. Electrically driving the first and second signal traces induces voltages on the first and second signal traces, the voltages correlated with an amount of liquid within the separate regions.

The present disclosure provides a display substrate and a preparation method thereof, and belongs to the technical field of display. The display substrate of the present disclosure comprises: a substrate, having a connecting via hole penetrating through the thickness direction thereof; the substrate comprises a first surface and a second surface oppositely arranged along the thickness direction thereof; a pixel driving circuit arranged on the first surface; a signal trace arranged on the second surface; a connecting structure arranged in the connecting via hole, and the connecting structure electrically connects the signal trace and the pixel driving circuit; wherein part of the connecting via hole is filled with the connecting structure.

The invention relates to the technical field of power electronics, in particular to a semiconductor device, a vehicle-mounted charger and a vehicle wherein the semiconductor device comprises: a substrate, a power circuit, a power pin (102) and a signal pin (101); the power circuit is arranged on the substrate; the power pin (102) and the signal pin (101) are connected with a power circuit; the signal pins (101) arranged on the same side edge of the substrate are arranged in groups, and the distance between the signal pins (101) in different groups is larger than the distance between the power pins (102). According to the embodiment of the invention, the power line and the signal line in the semiconductor device are separated, so that the cross line and mutual interference of the power line and the signal line are avoided; and the problem that wiring is difficult due to many pins on the side of the signal pin (101) is avoided.

The invention relates to the technical field of defect detection, in particular to a solar water heater PCB control panel structure optimization method and system. The method comprises the steps of obtaining thermal parameters of all components, calculating time weighted thermal power, generating a board heat source distribution diagram, evaluating condensation risks of all areas of a board according to the heat source distribution diagram and a preset installation inclination angle of a PCB control board, generating a condensation risk distribution diagram, constructing an electromagnetic coupling model between a key signal wire and a power supply wire, basic electromagnetic interference intensity is calculated, condensation risk distribution on the key signal wiring path is extracted, the basic electromagnetic interference intensity is corrected to obtain a comprehensive risk assessment value, and wiring is optimized according to a priority strategy when the comprehensive risk assessment value is larger than a preset threshold value. According to the scheme, the condensation risk area of the board can be predicted and quantified, the condensation risk and the electromagnetic interference risk can be associated, and the working reliability of the PCB control board in the damp and hot alternating environment is improved.

A printed circuit board (PCB), vertical conductive structures (VeCSs) for the PCB, and a method of fabricating a printed circuit board (PCB). The VeCS includes a VeCS slot at least partially defined in a dielectric substrate. A vertical signal trace is positioned on a first side of the VeCS slot and a vertical reference trace is positioned on a second side of the VeCS slot opposite the vertical signal trace. The VeCS has a predetermined impedance. A plurality of signal ground planes is positioned at a respective predetermined distance from the vertical signal trace. Each signal ground plane defines a cutout.

An audio kill switch provides a noiseless passive cessation of an audio signal. A printed circuit board is joined to an upper shell and has a plurality of interlaced three mil copper signal and ground traces from a center signal trace and outer grounding ring respectively, with three mil spaces between traces interlaced in a way to gradually shunt the signal to ground over several milliseconds when contact between them is made by the conductive rubber button. A target pad is arranged on the center of the printed circuit board. An outer shell is surrounding the printed circuit board. A conductive rubber button is joined to a spring. A nylon outer sleeve is arranged against the conductive rubber button. A spring-loaded connector is arranged against the target pad and joined to a rubber sleeve.

A radiating element for a base station antenna comprises a feed stalk printed circuit board and a dipole radiator printed circuit board mounted on the feed stalk printed circuit board. The feed stalk printed circuit board includes a first ground line that includes a first integrated parallel LC circuit, a second ground line that includes a second integrated parallel LC circuit, a first signal trace that extends through an opening in the dipole radiator printed circuit board, and a second signal trace.

This application provides a display panel and a display device. The display panel includes a display area and a non-display area adjacent to the display area. The bezel area includes a substrate and signal traces, a planarization layer, lead traces, and an encapsulation layer sequentially stacked on the substrate. The encapsulation layer includes a first inorganic layer disposed on the lead traces. The display area includes a substrate, a planarization layer, and an anode located on the side of the planarization layer away from the substrate. The lead traces extend from the side of the anode into the bezel area and are connected to the signal traces. This application provides a barrier layer between the lead traces and the first inorganic layer. The orthographic projection of the barrier layer on the lead traces covers the orthographic projection of the first inorganic layer on the lead traces, thereby avoiding the bombardment damage to the lead traces by high-energy plasma when the first inorganic layer is fabricated using plasma-enhanced chemical vapor deposition in the prior art, and thus avoiding the phenomenon of uneven thickness of the first inorganic layer.

The invention provides a display panel and a display device. The display panel comprises a substrate base plate; the first conductive layer is arranged on the substrate and comprises a signal wire, and the signal wire extends to the binding area in the direction from the display area to the binding area; the protective layer is arranged on the side, away from the substrate, of the first conductive layer and located in the non-display area, and the orthographic projection of the protective layer in the non-display area is partially overlapped with the binding area; the packaging layer is arranged on the side, away from the substrate, of the first conductive layer, the packaging layer extends to the non-display area from the display area, a first open groove is formed between the end, extending to the non-display area, of the packaging layer and the end, facing the display area, of the protective layer, and a part of the first conductive layer is exposed out of the first open groove; the touch control layer is arranged on the side, away from the substrate, of the packaging layer, the touch control layer comprises an inorganic film layer, the inorganic film layer extends to the non-display area from the display area, and the inorganic film layer covers the packaging layer and at least covers part of the first open groove.

The present disclosure provides a backlight module and a display device, wherein a first conductive layer is disposed on a substrate and includes signal traces and a first ground line unit; a second conductive layer is disposed on a side of the first conductive layer close to or away from the substrate. The second conductive layer includes a second ground line unit. The light-emitting member is electrically connected with the signal traces and the first ground line unit, and the first ground line unit is connected with the second ground line unit.

A power package includes at least one power substrate having at least one power trace, at least one power device on the at least one power trace, signal terminals, and at least one signal connection assembly. The at least one signal connection assembly includes at least one of the following: at least one signal trace that is thinner than the at least one power trace; at least one embedded routing layer within the at least one power substrate; and / or at least one routing layer on the at least one power substrate.

The utility model discloses an SMD (Surface Mount Device) high-speed connector differential signal wire, which comprises two parallel PCB (Printed Circuit Board) wires and is divided into six sections, the differential signal lines comprise a differential line zero line segment, a differential line first line segment, a differential line second line segment, a differential line third line segment, a differential line fourth line segment and a differential line fifth line segment, and the ends of the two line segments in any differential line segment are flush. The zero line segment of the differential line, the first line segment of the differential line, the second line segment of the differential line, the third line segment of the differential line, the fourth line segment of the differential line and the fifth line segment of the differential line are connected in sequence, and the end point of the zero line segment of the differential line is connected with the high-speed signal via hole. And the end point of the fifth line segment of the differential wire is connected with a high-speed signal bonding pad of the high-speed connector. The utility model provides an SMD (Surface Mount Device) high-speed connector differential signal wiring, and aims to provide a differential signal wiring which is convenient for calculation of a PCB (Printed Circuit Board) design program.

The disclosure relates to an arrangement of an electrical circuit for powering one or more phase windings of an electrical machine of an automated storage and retrieval system, and such a system and a vehicle for such a system which incorporate such an arrangement. The arrangement comprises: a plurality of layers 910 of the electrical circuit, interposed with electrically insulating material 920, wherein through-connections 930 are provided between the layers; and for each of the phase windings, a first set of electrical connections for mounting a first active device, a second set of electrical connections for mounting a second active device, and a connection point for electrical connection with the respective phase winding of the electrical machine; wherein for each of the phase windings there is provided a respective area of conductive material in at least one of the layers that forms at least a part of an electrical connection between the respective connection point and a respective supply terminal of the first active device and a respective receiving terminal of the second active device, wherein the respective supply terminal and the respective receiving terminal are electrically connected with their respective area by one or more of the through-connections and without using signal traces for that connection.

A box dipole radiating element uses a compact quadrilateral arrangement of substantially coplanar radiating arms that supports tilted polarized radiation in response to differential mode currents generated along four sides of the quadrilateral arrangement and in response to common mode currents that can be generated in substantially the same plane as the differential mode currents. A feed signal routing network is provided that includes a feed signal routing substrate located on portions of the radiating arms, first through fourth signal traces located on a front side of the substrate, and first through fourth ground plane segments located on a back side of the substrate. The first through fourth ground plane segments are capacitively coupled to the radiating arms. Each of the signal traces receives a corresponding feed signal and spans a corresponding air gap between a pair of the radiating arms.

This application discloses a filtering trace structure, device, and flexible circuit board. The filtering trace structure includes at least one high-impedance trace and at least one low-impedance trace. The high-impedance and low-impedance traces are alternately arranged and connected in series. The characteristic impedance of the high-impedance trace is greater than a preset threshold, and the characteristic impedance of the low-impedance trace is less than the preset threshold. By alternately arranging and connecting at least one high-impedance and at least one low-impedance trace in series, a transmission line structure with periodic impedance changes is formed. The filtering effect is achieved by utilizing the impedance mismatch effect between the high-impedance and low-impedance segments, thereby directly integrating the filtering capability into the signal trace and effectively suppressing radio frequency interference.

A display substrate and a display device are disclosed. The display substrate includes a plurality of sub-pixels, data signal lines, and second signal traces. The plurality of sub-pixels includes a first sub-pixel emitting red light, a third sub-pixel emitting blue light, and a second and a fourth sub-pixel emitting green light. The data signal lines include a first data signal line connected to a pixel driving circuit of the first sub-pixel, a second data signal line connected to pixel driving circuits of the second and fourth sub-pixels, and a third data signal line connected to a pixel driving circuit of the third sub-pixel. The pixel columns include a first pixel column and a second pixel column. The first pixel column includes a first data signal line, a third data signal line, a first sub-pixel, and a third sub-pixel. The second pixel column includes a second data signal line, a second signal trace, a second sub-pixel, and a fourth sub-pixel. The second signal traces transmit constant voltage signals or transmit data signals.

An integrated circuit assembly comprises a plurality of die connection points configured to couple to an integrated circuit die, and a plurality of external connection points configured to couple to external circuitry. A metal power signal trace and a metal ground signal trace are each coupled to at least a respective one of the plurality of die connection points to provide electrical power to the integrated circuit. A first metal-insulator-metal capacitor comprises a plurality of first extensions interleaved with a plurality of extensions of the metal power signal trace and is separated from the plurality of extensions of the metal power signal trace by an insulator. A second metal-insulator-metal capacitor comprises a plurality of second extensions interleaved with a plurality of extensions of the metal ground trace and is also separated from the plurality of extensions of the metal ground trace by an insulator.