124results about How to "Reduce parasitic capacitance" patented technology

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate; the memory unit is arranged on the substrate, the memory unit comprises a transistor and a capacitor, the transistor comprises a first source / drain electrode, a grid electrode, a second source / drain electrode and a semiconductor layer surrounding the side wall of the grid electrode, the first source / drain electrode, the second source / drain electrode and the semiconductor layer are sequentially arranged in the first direction, and the first source / drain electrode and the second source / drain electrode are connected with the grid electrode through the semiconductor layer; the capacitor is arranged on one side of the second source / drain electrode and covers part of the side surface of the semiconductor layer; the bit line is arranged on one side of the first source / drain electrode and covers part of the side face of the semiconductor layer, the contact area of the bit line and the semiconductor layer is smaller than the contact area of the capacitor and the semiconductor layer, the contact area of the bit line and the transistor is reduced, and the opposite area of the bit line and the grid electrode of the transistor is reduced; therefore, the parasitic capacitance between the bit line and the grid electrode of the transistor is reduced, and the reading capability of the transistor is improved.

The invention provides an EML laser and a preparation method of an air bridge, belongs to the technical field of optical communication lasers, and is used for solving the problem that the stray capacitance of connecting metal between a waveguide electrode and a PAD electrode of the EML laser is too large. The preparation method of the air bridge process of the EML comprises the following steps: growing a mask layer on the surface of an epitaxial InP wafer, photoetching to form a ridge waveguide pattern, etching the mask layer by adopting ICP (Inductively Coupled Plasma), and removing photoresist; etching the ohmic contact layer by adopting ICP (Inductively Coupled Plasma) and removing the mask layer; gluing and photoetching the surface of the wafer to form a pier pattern; adopting ICPCVD to grow a dielectric film at low temperature; gluing and photoetching the surface of the wafer to form a dielectric film bridge pattern; carrying out ICP etching on the dielectric film and removing the bridge and pier photoresist to form a dielectric film bridge; and performing wet etching on the InP epitaxial layer to the etching stop layer. According to the method, the dielectric film bridge is built at the connecting metal between the waveguide electrode and the PAD electrode, the low dielectric constant characteristic of air is utilized, the distance between the metal and the quantum well is greatly increased, the stray capacitance of the EML is reduced, and the bandwidth is improved.

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a mask layer on the substrate, and enabling the mask layer to expose an area, where a high-resistance structure needs to be formed, in the substrate; injecting ions into the region by adopting an ion injection process; and removing the mask layer and carrying out an annealing process, forming an insulating buried layer in the region, and forming a crystal layer on the insulating buried layer so as to form a high-resistance structure comprising the insulating buried layer and the crystal layer. The semiconductor device comprises a substrate and a high-resistance structure, and the high-resistance structure comprises an insulating buried layer located in the substrate and a crystallization layer located on the insulating buried layer. According to the invention, the high-resistance structure is formed in the substrate, the resistance uniformity of the high-resistance structure is improved, the thickness of an interlayer dielectric layer formed subsequently is reduced, and the parasitic capacitance and the power consumption of the semiconductor device are reduced.

The pull-type transient electromagnetic detection system comprises a detection module, a detection assembly comprises a transmitting coil, a receiving coil and a host, the transmitting coil and the receiving coil are arranged in parallel, the height between the transmitting coil and the receiving coil is adjustable, one end of the host is connected with the transmitting coil, and the other end of the host is connected with the receiving coil. The horizontal relative position of the receiving coil and the transmitting coil can also be adjusted, the position of the receiving coil is determined when the mutual inductance of the transmitting coil and the receiving coil is zero, the signal processing module comprises an amplifier and a noise processing module, and the receiving coil, the amplifier, the noise processing module and the host are sequentially connected. Signal processing is carried out through the following steps: 1, coil laying; 2, setting an amplifier circuit; 3, electromagnetic noise suppression; according to the invention, in the electromagnetic signal acquisition process and the electromagnetic signal processing process, the quality of the electromagnetic signal is improved, so that the electromagnetic signal with higher quality can be comprehensively obtained.

The invention discloses a semiconductor device, a manufacturing method thereof and an electronic device, and the semiconductor device comprises a semiconductor substrate which comprises a first surface and a second surface which are opposite to each other; a groove penetrating through the semiconductor substrate is formed in the semiconductor substrate, a lining layer is formed on the side wall of the groove, and the dielectric constant of the lining layer is smaller than that of the semiconductor substrate; a metal plug is formed in the lining layer, the first end of the metal plug is electrically connected with the first wiring layer located on one side of the first surface, and the second end of the metal plug is electrically connected with the second wiring layer located on one side of the second surface. The parasitic capacitance and resistance generated by the high-frequency signal in the semiconductor substrate are reduced so as to reduce the loss when the high-frequency signal is transmitted in the metal plug.

In order to solve the problem caused by uneven overlapping of data fan-out lines and control signal lines, the utility model provides a display panel and a display device, the display panel comprises a substrate, a plurality of sub-pixels and a plurality of data lines which are located in a display area, and a plurality of data fan-out lines and a plurality of control signal lines which are located in a first frame area. The plurality of data fan-out lines comprise a first group of data fan-out lines and a second group of data fan-out lines, and the plurality of control signal lines comprise a first group of control signal lines and a second group of control signal lines. The number of control signal lines in the first group of control signal lines is greater than the number of control signal lines in the second group of control signal lines. Each data fan-out line in the first group of data fan-out lines is overlapped with the orthographic projection of the first group of control signal lines on the substrate, and each data fan-out line in the second group of data fan-out lines is overlapped with the orthographic projection of the second group of control signal lines on the substrate. And at least one organic insulating layer is arranged between the data fan-out lines and the control signal lines with overlapped orthographic projections on the substrate.

The invention provides a filter, a preparation method thereof and electronic equipment. The filter comprises a substrate provided with conductive columns, a first structural layer is arranged on the first surface of the substrate, and a second structural layer, a first insulating layer, a lead layer, a second insulating layer and a bonding pad layer are arranged on the second surface of the substrate; each of the first structural layer and the second structural layer comprises a connecting electrode connected with the conductive column, the second structural layer further comprises a capacitor structure, the lead layer comprises at least one lead, the leads are connected with the capacitor structure, the pad layer comprises at least one pad, and the pads are connected with the leads; materials of the first insulating layer and the second insulating layer include organic materials. By arranging the first insulating layer and the second insulating layer which are made of organic materials, the performance stability and reliability of the filter can be improved, and the performance of the filter is improved.

The invention discloses an electronic component and terminal equipment, the electronic component comprises a component main body, a first terminal electrode, a second terminal electrode and a coil conductor, the coil conductor is provided with an upper side conductor, a first side conductor, a plurality of first bevel edge conductors, a lower side conductor, a plurality of second bevel edge conductors and a second side conductor, the first beveled edge conductors are arranged corresponding to the first terminal electrodes, the first beveled edge conductors are obliquely arranged relative to the first side edge conductors and the lower edge conductor, an included angle is formed between every two adjacent first beveled edge conductors, the second beveled edge conductors are arranged corresponding to the second terminal electrodes, and the second beveled edge conductors are obliquely arranged relative to the second side edge conductors and the lower edge conductor. An included angle is formed between every two adjacent second bevel edge conductors, and the first direction is perpendicular to the second direction. By adopting the scheme of the invention, the total resistance of the coil conductor can be reduced, and the quality factor and the self-resonant frequency of the electronic component can be improved.

The utility model is suitable for the technical field of sensors, and provides a capacitive sensor which comprises a capacitive digital conversion chip and an insulating substrate, a groove is formed in the front face of the insulating substrate and divides the front face of the insulating substrate into a measuring head area and a grounding area, a first via hole is formed in the measuring head area, and a second via hole is formed in the grounding area. A second via hole is formed in the grounding area, and copper plating layers are arranged on the measuring head area, the grounding area, the inner wall of the first via hole and the inner wall of the second via hole; the capacitance digital conversion chip is arranged on the back face of the insulating substrate, a detection pin of the capacitance digital conversion chip is electrically connected with the inner wall of the first via hole, and a grounding pin of the capacitance digital conversion chip is electrically connected with the inner wall of the second via hole. The stray capacitance in the capacitive sensor circuit can be reduced, the measurement precision and stability of the capacitive sensor can be improved, and the cost can be reduced at the same time.

The invention provides a semiconductor device and a manufacturing method, and the method comprises the following steps: providing a substrate, and forming a grid electrode on the substrate; forming a dielectric layer covering the grid electrode on the substrate; a dielectric layer is formed on the grid electrode, a plurality of conductive nano-columns arranged in an array are formed in the dielectric layer, a connecting conductive layer is formed on the dielectric layer, the connecting conductive layer is connected with the top ends of the conductive nano-columns, the conductive nano-columns are located on the same side of the grid electrode, and the bottom ends of the conductive nano-columns are not completely located on the same plane. According to the invention, the end face of each conductive nano-column is equivalent to a micro-field plate, the improvement capability of the electric field is stronger, a channel electric field with a single peak is changed into a channel electric field with a plurality of small peaks, and the distribution of the channel electric fields is more uniform; and moreover, the smaller end surface area in the conductive nanorod can bring smaller parasitic capacitance, and the reliability of the device is enhanced.

The invention provides a semiconductor crystal grain structure. The semiconductor crystal grain structure comprises a substrate, a first supporting framework, a second supporting framework, a first conductor block, a second conductor block and a third conductor block, the first supporting framework and the second supporting framework are arranged on the base. The first conductor block is disposed on the first support frame, and the second conductor block is disposed on the second support frame. The third conductor block is disposed between the first conductor block and the second conductor block. The third conductor block is suspended on the substrate.

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

The invention discloses a GaN vertical complementary field effect transistor (VCFET) and an inverter, the VCFET comprises a substrate, a first transistor, a second transistor and a common gate electrode, and the first transistor and the second transistor are sequentially and vertically stacked on the substrate; the first transistor is an n-type transistor, the second transistor is a p-type transistor, and an integral structural form of a GaN buffer layer, an n-tube GaN channel layer, an AlGaN barrier layer, a p-tube GaN channel layer and a p-tube GaN doping layer is formed; the control of the n-type channel and the p-type channel at the same time is realized through a common gate electrode. On the basis of the structure, the source electrode of the p-type transistor is connected with a high level, the source electrode of the n-type transistor is connected with a low level, the drain electrodes of the two transistors are connected together and serve as an output end at the same time, and the gate electrodes serve as an input end, so that the phase inverter can be realized. According to the VCFET, the electronic transmission characteristics of high efficiency and low power consumption are realized, the occupied area is smaller while the high performance is maintained, and the integration level is improved.

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

Provided is an antenna device that is small and low-profile, can reduce parasitic capacitance, and can be mixed with other media antennas without obstacles. The AM / FM antenna (13) is constructed by fixing a pair of capacitor-loaded vibrators (131, 132) to a retaining frame (133) through a fixing hole (1321), and fixing a helical antenna (134) at the bottom of the retaining frame (134). The capacitor-loaded vibrators (131, 132) are centered on a plane perpendicular to the roof and are opposite to each other at a specified interval and a specified angle. In addition, connecting parts are provided at locations lower than the upper edge, and are connected to each other via each connecting part. The edges of the capacitor-loaded vibrators (131, 132) are of a size that does not interfere with, for example, the SDARS antenna (14) and the GNSS antenna (19).

This application discloses a semiconductor device structure, a CMOS structure, and a method for fabricating the same, relating to the field of semiconductor device technology. The semiconductor device structure employs two buried oxide layers interleaved within a three-layer silicon SOI substrate. The epitaxial initiation layer of the source / drain regions is transferred from the top silicon layer of the SOI substrate to an intermediate or supporting silicon layer within the SOI substrate. This solves a series of process problems arising from the development of SOI technology nodes, particularly in epitaxially growing source / drain regions on a thinner top silicon layer, thus improving the epitaxial growth quality and structural stability of the source / drain regions. Furthermore, the parallel overlap length between the source / drain regions and the gate structure is reduced, significantly decreasing the parasitic capacitance between the source / drain regions and the gate structure. Moreover, the source / drain regions can directly contact the channel, enhancing the contact reliability between the source / drain regions and the channel, enabling stress control of the channel, and improving channel mobility, thus possessing significant application value.

The embodiment of the invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate; the word line structures are located on the substrate and arranged at intervals in the first direction, and each word line structure comprises a plurality of gate structures which are sequentially arranged at intervals in the third direction; the plurality of active column structures are arranged on the outer wall of each gate structure; at least one end of the active column structure along the second direction is provided with a groove with an opening facing the second direction; part of the active column structure surrounding the gate structure forms a channel structure, and part of the active column structure which is located at two sides of the channel structure along the second direction and is adjacent to the groove forms a source and a drain; the isolation structure is located on the inner wall, adjacent to the gate structure, in the groove; the first direction and the second direction intersect and are located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located.

The invention provides a preparation method of an N-type carbon-based semiconductor structure and a semiconductor device. The preparation method comprises the following steps: forming a channel layer on a substrate; forming a high-k dielectric layer on the channel layer; forming a gate structure on the high-k dielectric layer; etching the gate structure to form a gate, and forming a dielectric barrier layer on the gate and the high-k dielectric layer; forming an interlayer dielectric layer on the dielectric barrier layer; forming a source contact hole and a drain contact hole; a source electrode lamination structure is deposited in the source electrode contact hole, a drain electrode lamination structure is deposited in the drain electrode contact hole, a source electrode and a drain electrode are formed, and the source electrode lamination structure and the drain electrode lamination structure are lamination structures of titanium nitride and tungsten; a laminated structure of titanium nitride and ruthenium; a laminated structure of titanium nitride, tantalum nitride and tungsten; and a laminated structure of titanium nitride, tantalum nitride and ruthenium, or a laminated structure of titanium nitride, tantalum nitride and copper, in which the titanium nitride serves as an interface contact layer and contacts the channel layer.

The application discloses an acceleration sensor and a manufacturing method thereof. The acceleration sensor comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor on a substrate. The first capacitor comprises a second detection mass and a first detection electrode. The second capacitor comprises a first detection mass and a first detection electrode. The third capacitor comprises a second detection mass and a second detection electrode. The fourth capacitor comprises a first detection mass and a second detection electrode. The first detection electrode and the second detection electrode are located between the first detection mass and the second detection mass and are independent of each other and located in the same plane. The application forms a full-bridge capacitor detection structure by the first detection mass, the second detection mass, the first detection electrode and the second detection electrode located between the first detection mass and the second detection mass, which can effectively reduce parasitic capacitance, optimize noise, improve stability and sensitivity.

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a substrate which comprises an array region and a peripheral region; the bit line structure is located in the array region, and the bit line structure comprises a bit line contact structure in contact with the substrate; the gate structure is located in the peripheral region, the gate structure comprises a first conductive layer located on the substrate, and the top surface of the bit line contact structure is not higher than the top surface of the first conductive layer in the direction parallel to the surface of the substrate. The semiconductor structure provided by the embodiment of the invention at least can improve the performance of the semiconductor structure.

The invention provides a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. According to the transistor, a collector region, a field region silicon oxide layer, an outer base isolation layer, an outer base region polycrystalline silicon layer and an emitter region are sequentially formed on a substrate; afterwards, a metal or metal silicide shielding layer is arranged on the first dielectric layer covering the surface of the device, and the shielding layer is located above an area between any two of the collector electrode, the base electrode and the emitter electrode and then is covered by a second dielectric layer. The shielding layer can optimize the electric field distribution between the electrodes, significantly improve the breakdown voltage between the emitter and the base, between the collector and the base and between the collector and the emitter, and enhance the power capability and reliability of the device. Meanwhile, electric field coupling between the electrodes is effectively shielded, and related parasitic capacitance is greatly reduced. The improvement of the breakdown voltage and the reduction of the parasitic capacitance act together, and the current gain cut-off frequency, the maximum oscillation frequency and other core electrical properties of the transistor are directly improved.

The invention provides a stacked transistor, a preparation method thereof, a device and electronic equipment. The method comprises the following steps: forming an active structure on a substrate; forming a pseudo gate stack structure on the substrate; the pseudo gate stack structure comprises a first pseudo gate structure surrounding the first active structure, a gate isolation layer and a second pseudo gate structure surrounding the second active structure; forming a first source-drain epitaxy of the first transistor and a second source-drain epitaxy of the second transistor; removing the first pseudo gate structure and the second pseudo gate structure, and forming a through hole penetrating through the gate isolation layer; forming a second gate metal layer of the second transistor and a first gate metal layer of the first transistor, and forming a gate interconnection through hole in the through hole; the gate interconnection through holes are respectively connected with the first gate metal layer and the second gate metal layer; a first orthographic projection of the gate interconnection via in the first direction is located inside a second orthographic projection of the active structure in the first direction. According to the invention, parasitic capacitance can be reduced.

The invention provides a semiconductor crystal grain structure. The semiconductor crystal grain structure comprises a substrate, a first supporting framework, a first conductor block and an air gap structure, the first supporting framework is arranged on the base. The first conductor block is disposed on the first support frame and includes a first barrier layer and a first conductive layer disposed in the first barrier layer. The air gap structure is disposed on the substrate and contacts the first support frame and the first conductor block.

The present application provides a kind of vibration power generation element, can substantially reduce the parasitic capacitance possibly generated in vibration power generation element, thereby can expand the frequency band that can be generated.A kind of vibration power generation element, characterized in that, with: fixed electrode, it has multiple comb-shaped electrodes;Movable electrode, it has multiple comb-shaped electrodes with the fixed electrode interlock;And elastic support part, it makes the movable electrode relative to the fixed electrode in the same plane on the predetermined direction relative movement, in the state of at least one of the fixed electrode and the movable electrode is electrified, the fixed electrode and the engagement length of the movable electrode and the deflection of the elastic support part are same, or the fixed electrode and the engagement length of the movable electrode is less than the deflection of the elastic support part.

The present application relates to a kind of feedforward equalizer circuit using distributed tap, including M distributed tap circuit, input end resistance and output end resistance;Each distributed tap circuit includes N transconductance amplifier, N input signal delay unit and N output signal delay unit;M, N are integer greater than or equal to 2.Input signal VI enters from the input end of the first distributed tap circuit, after passing through the first, the second, …, the Mth distributed tap circuit respectively, is connected to the one end of input end resistance, the other end of input end resistance is grounded;The output signal of each distributed tap circuit is connected together with the one end of output end resistance, and output signal VO is generated;The other end of output end resistance is connected to power supply.A kind of feedforward equalizer circuit using distributed tap proposed in the present application reduces the parasitic capacitance of transconductance amplifier, reduces the degree of signal reflection, and further reduces the bit error rate of received signal.

Provided is a semiconductor structure manufacturing method, comprising: providing a first wafer, the upper surface of the first wafer having a void structure extending to the interior of the first wafer; providing a second wafer, the lower surface of the second wafer having an insulating layer; bonding the second wafer and the first wafer with the insulating layer and the upper surface of the first wafer as the bonding surface, the insulating layer sealing the void structure; manufacturing a device on the upper surface of the second wafer; and forming a through-silicon via structure, at least part of the side surface of the through-silicon via structure being surrounded by the void structure. The application can seal the void structure with the existing insulating layer, thereby maintaining the design pattern of the void structure, ensuring the stress release effect of the subsequently formed through-silicon via structure, increasing the area of the region around the through-silicon via structure that is not affected by internal stress, increasing the number of transistors arranged, and improving the performance of the semiconductor structure. In addition, the device is formed on the insulating layer, which can greatly reduce the parasitic capacitance, improve the clock, reduce the current leakage current of the device, and improve the performance of the semiconductor structure.

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor technology, for reducing parasitic capacitance between adjacent memory contacts and improving the driving capability of the semiconductor device. The semiconductor device includes: a substrate, bit line structures, memory contacts, and an isolation portion. The substrate has an active region. The bit line structures are formed on the substrate and contact a portion of the active region. The memory contacts and the isolation portion are formed between two adjacent bit line structures. The memory contacts contact another portion of the active region. The isolation portion isolates two adjacent memory contacts. The material contained in the isolation portion includes a low-k material. The manufacturing method of the semiconductor device is used to manufacture the semiconductor device provided by the above-described technical solution.

The present invention relates to the technical field of PCBs, and discloses a slot plugging member, a method for manufacturing a PCB sidewall circuit, and a PCB. The slot plugging member is used to plug into a through slot where a sidewall circuit is to be manufactured, and the slot plugging member includes an electroplating body that is hollow inside and made of a copper-platable material; the outer structure of the electroplating body is the same as the inner structure of the through slot, and the outer dimensions are the same as the inner dimensions of the through slot; the inner wall of the electroplating body is provided with an anti-plating film, and the anti-plating film is provided with a gap, and the shape, size, and position of the gap and the sidewall circuit are the same. In an embodiment of the present invention, a slot plugging member with a partial plating resistance function is used to plug into the through slot, and then the through slot is subjected to conventional copper electroplating to manufacture a refined sidewall circuit on the side wall of the through slot, and the sidewall circuit is used to replace conventional metallized vias for signal transmission, which greatly reduces the circuit width compared to metallized vias, thereby effectively improving the signal transmission quality.

The present application discloses a micro-electromechanical structure and a manufacturing method thereof, a wafer, a microphone and a terminal. The manufacturing method comprises: forming a first back plate above a substrate; forming a second sacrificial layer on the first back plate; forming a diaphragm on the second sacrificial layer, the diaphragm extending to the substrate along the side wall of the second sacrificial layer and the side wall of the first back plate; and removing part of the second sacrificial layer, with the remaining second sacrificial layer serving as a second supporting portion. The manufacturing method reduces the risk of the release liquid corroding the side wall of the second sacrificial layer during the release process by allowing the diaphragm to cover the side wall of the second sacrificial layer.

An embodiment of the present specification discloses a display device including: a display panel including a display area and a non-display area surrounding the display area; and a metal dam disposed in the non-display area to surround at least three surfaces of the display panel, in which the display panel includes: a substrate; the pixel driving circuit is arranged on the substrate; and a light emitting element driven by the pixel driving circuit, the metal dam may be spaced apart from an edge of the display panel by a predetermined distance, the metal dam may be formed of a plurality of metal layers connected through at least one hole, and the metal dam may include a first metal dam, a second metal dam, and a third metal dam, a first metal dam, a second metal dam, and a third metal dam are disposed in the non-display area while surrounding at least three surfaces of the display area.