55results about How to "Reduce parasitic capacitance" patented technology

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

The application discloses a super-junction LDMOS device with high-resistance substrate TSV grounding and a manufacturing method thereof. The super-junction LDMOS device comprises a high-resistance substrate, a body region and a drift region formed in the high-resistance substrate, a body region contact region and a source region formed in the body region, a polysilicon gate formed on a substrate surface above the body region, and a drain region formed in the drift region. The drift region comprises a super-junction structure formed by a first column region and a second column region arranged at intervals in a gate width direction. A first buffer layer is arranged between the first column region and the drain region, a second buffer layer is arranged between the second column region and the drain region, and the first buffer layer and the second buffer layer are arranged to surround the drain region. The super-junction LDMOS device can effectively suppress substrate auxiliary effect, can realize optimal design of device breakdown voltage and on-resistance, and can reduce output capacitance of the device.

This application discloses a semiconductor device structure, a CMOS structure, and a method for fabricating the same, relating to the field of semiconductor device technology. The semiconductor device structure employs two buried oxide layers interleaved within a three-layer silicon SOI substrate. The epitaxial initiation layer of the source / drain regions is transferred from the top silicon layer of the SOI substrate to an intermediate or supporting silicon layer within the SOI substrate. This solves a series of process problems arising from the development of SOI technology nodes, particularly in epitaxially growing source / drain regions on a thinner top silicon layer, thus improving the epitaxial growth quality and structural stability of the source / drain regions. Furthermore, the parallel overlap length between the source / drain regions and the gate structure is reduced, significantly decreasing the parasitic capacitance between the source / drain regions and the gate structure. Moreover, the source / drain regions can directly contact the channel, enhancing the contact reliability between the source / drain regions and the channel, enabling stress control of the channel, and improving channel mobility, thus possessing significant application value.

The invention provides a preparation method of an N-type carbon-based semiconductor structure and a semiconductor device. The preparation method comprises the following steps: forming a channel layer on a substrate; forming a high-k dielectric layer on the channel layer; forming a gate structure on the high-k dielectric layer; etching the gate structure to form a gate, and forming a dielectric barrier layer on the gate and the high-k dielectric layer; forming an interlayer dielectric layer on the dielectric barrier layer; forming a source contact hole and a drain contact hole; a source electrode lamination structure is deposited in the source electrode contact hole, a drain electrode lamination structure is deposited in the drain electrode contact hole, a source electrode and a drain electrode are formed, and the source electrode lamination structure and the drain electrode lamination structure are lamination structures of titanium nitride and tungsten; a laminated structure of titanium nitride and ruthenium; a laminated structure of titanium nitride, tantalum nitride and tungsten; and a laminated structure of titanium nitride, tantalum nitride and ruthenium, or a laminated structure of titanium nitride, tantalum nitride and copper, in which the titanium nitride serves as an interface contact layer and contacts the channel layer.

The application discloses an acceleration sensor and a manufacturing method thereof. The acceleration sensor comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor on a substrate. The first capacitor comprises a second detection mass and a first detection electrode. The second capacitor comprises a first detection mass and a first detection electrode. The third capacitor comprises a second detection mass and a second detection electrode. The fourth capacitor comprises a first detection mass and a second detection electrode. The first detection electrode and the second detection electrode are located between the first detection mass and the second detection mass and are independent of each other and located in the same plane. The application forms a full-bridge capacitor detection structure by the first detection mass, the second detection mass, the first detection electrode and the second detection electrode located between the first detection mass and the second detection mass, which can effectively reduce parasitic capacitance, optimize noise, improve stability and sensitivity.

The invention provides a germanium-silicon heterojunction bipolar transistor and a manufacturing method thereof. According to the transistor, a collector region, a field region silicon oxide layer, an outer base isolation layer, an outer base region polycrystalline silicon layer and an emitter region are sequentially formed on a substrate; afterwards, a metal or metal silicide shielding layer is arranged on the first dielectric layer covering the surface of the device, and the shielding layer is located above an area between any two of the collector electrode, the base electrode and the emitter electrode and then is covered by a second dielectric layer. The shielding layer can optimize the electric field distribution between the electrodes, significantly improve the breakdown voltage between the emitter and the base, between the collector and the base and between the collector and the emitter, and enhance the power capability and reliability of the device. Meanwhile, electric field coupling between the electrodes is effectively shielded, and related parasitic capacitance is greatly reduced. The improvement of the breakdown voltage and the reduction of the parasitic capacitance act together, and the current gain cut-off frequency, the maximum oscillation frequency and other core electrical properties of the transistor are directly improved.

The invention provides a stacked transistor, a preparation method thereof, a device and electronic equipment. The method comprises the following steps: forming an active structure on a substrate; forming a pseudo gate stack structure on the substrate; the pseudo gate stack structure comprises a first pseudo gate structure surrounding the first active structure, a gate isolation layer and a second pseudo gate structure surrounding the second active structure; forming a first source-drain epitaxy of the first transistor and a second source-drain epitaxy of the second transistor; removing the first pseudo gate structure and the second pseudo gate structure, and forming a through hole penetrating through the gate isolation layer; forming a second gate metal layer of the second transistor and a first gate metal layer of the first transistor, and forming a gate interconnection through hole in the through hole; the gate interconnection through holes are respectively connected with the first gate metal layer and the second gate metal layer; a first orthographic projection of the gate interconnection via in the first direction is located inside a second orthographic projection of the active structure in the first direction. According to the invention, parasitic capacitance can be reduced.

The present application provides a kind of vibration power generation element, can substantially reduce the parasitic capacitance possibly generated in vibration power generation element, thereby can expand the frequency band that can be generated.A kind of vibration power generation element, characterized in that, with: fixed electrode, it has multiple comb-shaped electrodes;Movable electrode, it has multiple comb-shaped electrodes with the fixed electrode interlock;And elastic support part, it makes the movable electrode relative to the fixed electrode in the same plane on the predetermined direction relative movement, in the state of at least one of the fixed electrode and the movable electrode is electrified, the fixed electrode and the engagement length of the movable electrode and the deflection of the elastic support part are same, or the fixed electrode and the engagement length of the movable electrode is less than the deflection of the elastic support part.

The present application relates to a kind of feedforward equalizer circuit using distributed tap, including M distributed tap circuit, input end resistance and output end resistance;Each distributed tap circuit includes N transconductance amplifier, N input signal delay unit and N output signal delay unit;M, N are integer greater than or equal to 2.Input signal VI enters from the input end of the first distributed tap circuit, after passing through the first, the second, …, the Mth distributed tap circuit respectively, is connected to the one end of input end resistance, the other end of input end resistance is grounded;The output signal of each distributed tap circuit is connected together with the one end of output end resistance, and output signal VO is generated;The other end of output end resistance is connected to power supply.A kind of feedforward equalizer circuit using distributed tap proposed in the present application reduces the parasitic capacitance of transconductance amplifier, reduces the degree of signal reflection, and further reduces the bit error rate of received signal.

Provided is a semiconductor structure manufacturing method, comprising: providing a first wafer, the upper surface of the first wafer having a void structure extending to the interior of the first wafer; providing a second wafer, the lower surface of the second wafer having an insulating layer; bonding the second wafer and the first wafer with the insulating layer and the upper surface of the first wafer as the bonding surface, the insulating layer sealing the void structure; manufacturing a device on the upper surface of the second wafer; and forming a through-silicon via structure, at least part of the side surface of the through-silicon via structure being surrounded by the void structure. The application can seal the void structure with the existing insulating layer, thereby maintaining the design pattern of the void structure, ensuring the stress release effect of the subsequently formed through-silicon via structure, increasing the area of the region around the through-silicon via structure that is not affected by internal stress, increasing the number of transistors arranged, and improving the performance of the semiconductor structure. In addition, the device is formed on the insulating layer, which can greatly reduce the parasitic capacitance, improve the clock, reduce the current leakage current of the device, and improve the performance of the semiconductor structure.

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor technology, for reducing parasitic capacitance between adjacent memory contacts and improving the driving capability of the semiconductor device. The semiconductor device includes: a substrate, bit line structures, memory contacts, and an isolation portion. The substrate has an active region. The bit line structures are formed on the substrate and contact a portion of the active region. The memory contacts and the isolation portion are formed between two adjacent bit line structures. The memory contacts contact another portion of the active region. The isolation portion isolates two adjacent memory contacts. The material contained in the isolation portion includes a low-k material. The manufacturing method of the semiconductor device is used to manufacture the semiconductor device provided by the above-described technical solution.

A semiconductor structure and a method for forming the same, wherein the structure comprises: a substrate; a gate structure and a plurality of source / drain doping layers, the gate structure is located on the substrate, and the source / drain doping layers are located in the substrate on both sides of the gate structure; a first conductive structure and a second conductive structure, the first conductive structure is located on the source / drain doping layers, and the second conductive structure is located on the gate structure; a first filling opening which exposes the side wall of the first conductive structure and the gate structure; a first filling layer located in the first filling opening, and the first filling layer has a first air gap therein. Since there is no other filling material between the first conductive structure and the gate structure, the first filling layer has a larger filling space, and the cavity of the first air gap in the first filling layer is larger. When the cavity of the first air gap is larger, the dielectric constant between the first conductive structure and the gate structure is smaller, and the parasitic capacitance between the first conductive structure and the gate structure is smaller, so that the performance of the semiconductor structure finally formed is better.

The embodiments of the present disclosure disclose a semiconductor device and a manufacturing method thereof, and a memory. The semiconductor device comprises: a plurality of active pillars; a first gate structure located between two adjacent active pillars and covering at least part of a channel of one of the two adjacent active pillars; a second gate structure located between the first gate structure and the other of the two adjacent active pillars and covering at least part of a channel of the other of the two adjacent active pillars; a first isolation structure located between the first gate structure and the second gate structure; a second isolation structure comprising a first part located between the first gate structure and the first isolation structure and a second part located between the second gate structure and the first isolation structure; wherein the first part and the second part are connected below the first isolation structure; a third isolation structure located above the first isolation structure; wherein the dielectric constant of the first isolation structure is less than the dielectric constant of the second isolation structure or the third isolation structure.

The application discloses a power magnetic core common mode inductor and a preparation method thereof, and belongs to the technical field of electronic component manufacturing, and comprises a winding execution unit, a magnetic circuit assembly unit and a material flow transfer module, wherein the winding execution unit comprises a main shaft rotating motor and a wire arranging servo module, the magnetic circuit assembly unit comprises a servo press and a glue injection nozzle, and the material flow transfer module is connected with the winding execution unit and the magnetic circuit assembly unit. The scheme physically increases the average distance of interlayer conductors through staggered span actions, changes the distribution direction of electric field vectors, effectively reduces the parasitic capacitance between windings, directly improves the high-frequency characteristics of the common mode inductor, expands the high-frequency impedance bandwidth, and enables the common mode inductor to more effectively inhibit high-frequency noise transmission.

To provide a display device in which parasitic capacitance between wirings can be reduced, a display device in which display quality is high, and a display device in which power consumption can be reduced. The display device of the present invention includes a signal line 121; a scan line 103; a first electrode 123; a second electrode 125a; a third electrode 125b; a first pixel electrode 139a; a second pixel electrode 139b; and a semiconductor film 135, wherein the signal line and the scan line cross, the first electrode is electrically connected to the signal line, the first electrode includes a region overlapping the scan line, the second electrode faces the first electrode, the third electrode faces the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is provided between the scan line and the first electrode to the third electrode.

The application relates to a source adjustable resistance circuit for a high-speed differential amplifier, belonging to the technical field of high-speed analog and radio frequency integrated circuits, comprising a high-speed differential amplifier, a degeneration resistance unit and a control unit; the degeneration resistance unit is composed of a first MOS transistor; the source and the drain of the first MOS transistor are respectively connected to two source nodes of a differential pair transistor of the high-speed differential amplifier, serving as source degeneration resistance thereof, and the gate voltage of the first MOS transistor is generated by the control unit; the control unit is used for generating the gate control voltage of the first MOS transistor. The application replaces a large resistance array with a single MOS transistor, greatly reduces the area, greatly reduces the chip cost, significantly reduces the parasitic capacitance of the degeneration node to the ground, and improves the amplifier bandwidth.

Embodiments of the present application disclose a contact pad structure and a manufacturing method thereof. The contact pad structure comprises a substrate, a plurality of first contact pads arranged on a first region of the substrate, a first dielectric layer arranged on the substrate and covering the plurality of first contact pads, the first dielectric layer forming a recess between two adjacent first contact pads, an etching stop layer arranged on the first dielectric layer and filling part of the recess, the etching stop layer being provided with a first gap in each recess, and a second dielectric layer arranged on the etching stop layer, the second dielectric layer filling the recess and being provided with a second gap in the recess. In this way, the parasitic capacitance between adjacent contact pads can be reduced, thereby improving the interference problem between the contact pads.

This application discloses a GaN-based micro-LED epitaxial structure, device, and fabrication method. The GaN-based micro-LED epitaxial structure includes, along the growth direction, a substrate, a buffer layer, an N-type doped GaN electron injection layer, an active region, and an Al2O3 layer. y Ga 1‑y The substrate consists of an N-type electron blocking layer and a P-type doped GaN hole injection layer; the substrate is selected from a (111) crystal plane single-crystal silicon substrate, a c-axis single-crystal sapphire substrate, a c-axis single-crystal silicon carbide substrate, or a c-axis self-supporting single-crystal gallium nitride substrate; the active region includes an InGaN-based light-emitting structure, which is at least one of an InGaN / GaN alternating multi-quantum-well structure, a GaN / InGaN / GaN single-quantum-well structure, and an InGaN quantum dot structure. This application shortens the carrier radiative recombination lifetime, weakens the quantum-confined Stark effect, and improves the radiative recombination rate by employing a thin quantum well or quantum dot active region structure, thereby enhancing the device's modulation bandwidth and photoelectric efficiency, meeting the performance requirements of light sources for applications such as data center optical interconnects, co-packaged optics, and high-speed visible light communication.

This invention belongs to the field of liquid crystal display technology and discloses a multi-grayscale active-matrix cholesteric liquid crystal display device and its array substrate. The substrate body has multiple pixel units, each pixel unit including multiple sub-units, allowing different pixel units to display the same or different grayscale levels. The sub-pixel electrode of each sub-unit is connected to a scan line via a TFT device, and multiple sub-pixel electrodes are connected to the same data line via TFT devices. In the process of achieving grayscale in a single pixel unit of the cholesteric liquid crystal by dividing it into sub-units, multiple sub-pixel electrodes within a single pixel unit are connected to scan lines for control and to the same data line, reducing the number of data lines and significantly reducing the parasitic capacitance between the data lines and the common electrode. This avoids excessive transient current in the common electrode traces during power-on due to capacitive coupling between a large number of data lines and the common electrode, which could cause burnout, thus significantly improving the panel's lifespan.

The utility model particularly relates to a power supply topology circuit structure used for grid driving power supply. The power supply topology circuit structure comprises a control unit, an LLC circuit connected with the control unit, and a grid voltage division circuit connected with a rectification structure of the LLC circuit. According to the utility model, the LLC circuit and the grid voltage division circuit are combined, so that the power transformer in the LLC circuit has relatively large leakage inductance and relatively small parasitic capacitance from the first side to the second side, thereby effectively reducing EMI noise coupling, achieving the purpose of improving EMC performance of a new energy motor technology, and improving the reliability of the new energy motor. The circuit at least has the advantages of low EMI noise and high EMC performance.

The invention relates to the technical field of transistors, in particular to a transistor base metal manufacturing method, which comprises the following steps of: depositing a dielectric layer on the surface of an epitaxial wafer of an emitter layer; coating two layers of light resistors on the surface of the dielectric layer, exposing and developing, and etching to remove the exposed dielectric layer; etching a channel with an inverted trapezoidal cross section on the exposed emitter layer; evaporating Y-shaped base metal on the channel, wherein the channel is filled with the lower part of the base metal; and removing the light resistor to complete the manufacturing of the transistor base metal. The Y-shaped base metal with the suspended upper portion is manufactured, the upper portion of the base metal is designed to be suspended, the base metal does not make direct contact with a dielectric layer, stray capacitance is effectively reduced, and the maximum working frequency of a device can be improved without optimizing an epitaxial structure of a transistor. Meanwhile, the volume of the base metal is increased, the rb is reduced, the base metal can fully cover the exposed base layer, the interface defect of the base layer is improved, the surface recombination is reduced, the base is prevented from being exposed and oxidized, and the rb is further effectively reduced.

A semiconductor structure and a forming method thereof, the structure comprising: a substrate; a channel layer structure suspended above the substrate, the channel layer structure comprising one or more spaced channel layers; a gate structure located on the substrate and across the channel layer structure, the gate structure surrounding the channel layers along a gate structure extending direction, wherein the gate structure located between adjacent channel layers and between the channel layer structure and the substrate is a stacked gate; source-drain doped layers located on the substrate on both sides of the gate structure and in contact with end portions of the channel layer structure; inner side walls located on sidewalls of the stacked gate, the stacked gate being spaced apart from the source-drain doped layers by the inner side walls; and an isolation layer located between the source-drain doped layers and the substrate, the isolation layer being in an integral structure with the inner side walls. The present application is advantageous in improving the working performance of the semiconductor structure.

The application provides a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping and a preparation method thereof. The two-dimensional multi-bridge channel transistor comprises a substrate and a plurality of channel structures arranged on the substrate. Each of the plurality of channel structures comprises a gate metal layer arranged on the substrate, a first high-k gate dielectric layer arranged around the first gate metal layer, a low-k gate dielectric layer arranged around the side surface of the first high-k gate dielectric layer, and a two-dimensional semiconductor material layer arranged on the high-k gate dielectric layer and the low-k gate dielectric layer, wherein part of the two-dimensional semiconductor material is induced to phase change into a two-dimensional semimetal / metal material layer by a solid source doping source. According to the two-dimensional multi-bridge channel transistor and the preparation method thereof, the source-drain contact resistance is reduced, the low-k sidewall process compatible with the two-dimensional semiconductor integrated circuit is realized, the parasitic is reduced, and the speed of the transistor is improved.

This invention discloses a power amplifier and electronic device employing a thin-gate device. The power amplifier uses a fully thin-gate low-threshold voltage transistor architecture, amplifying signals through multiple parallel cascode amplification units. The gate of the input stage transistor is coupled to the input signal via a DC-blocking capacitor, and the drain of the cascode transistor is connected to the power supply via an inductor. By introducing a segmented complementary gain control strategy—selectively turning off the input stage transistor while keeping the cascode transistor on in the high-power output range, and selectively turning off the cascode transistor while keeping the input stage transistor on in the low-power output range—this invention overcomes the performance limitations of traditional hybrid gate oxide schemes, significantly reducing parasitic capacitance and dynamic power consumption, and improving conversion efficiency. It simultaneously resolves the contradiction between the withstand voltage safety and deep turn-off of thin-gate devices, ensuring reliability across the entire power range; and simplifies the manufacturing process and optimizes current efficiency.

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, vertically arranged active pillars, a gate dielectric layer, a gate, a drain extension liner layer and a grid support structure. The gate dielectric layer is formed only in the channel region of the active pillars; the drain extension liner layer is formed on the sidewall of the drain region to increase the surface area; the grid support structure is formed outside the drain extension liner layer and comprises at least two layers of material and forms a ladder structure along the word line direction. The manufacturing method comprises the steps of forming an active pillar pattern, forming a gate dielectric layer only in the channel region, forming a drain extension liner layer and forming the multi-layer ladder grid support structure through a self-alignment process. The application significantly enhances the mechanical stability of the pillars, reduces the parasitic capacitance and leakage current and comprehensively improves the device performance and reliability by virtue of the unique structural design and self-alignment manufacturing process while effectively reducing the drain contact resistance.

The application provides an array substrate and a display panel. The array substrate comprises a substrate, a common electrode layer arranged on the substrate and comprising a common electrode and a plurality of first scan lines extending along a first direction, and a wiring layer arranged on the common electrode layer and comprising a plurality of second scan lines extending along a second direction intersecting the first direction, each second scan line being electrically connected with a corresponding first scan line, the second scan lines being used for transmitting a scan signal, the potential of the scan signal comprising a pulse peak value and a pulse valley value. The common electrode has the pulse valley value, which comprises making the voltage on the common electrode be the pulse valley value for making a switch transistor be closed, thereby reducing the parasitic capacitance between the common electrode and the second scan lines in most working processes of the pixel, and improving the influence of the coupling effect of the parasitic capacitance between the wiring in the vertical direction of the scan line and the common electrode on the pixel on the display of the display panel in the related art.

This invention provides a semiconductor structure and its fabrication method. The semiconductor structure includes at least one transistor, which includes: a channel region located in a semiconductor layer; a gate region located at least on one side of the channel region; a source region located at a first end of the channel region; and a drain region located at a second end of the channel region. The first end and the second end are opposite ends of the channel region in a first direction, which is the direction of the semiconductor layer thickness. At least one of the source and drain regions includes a first layer region and a second layer region, and both the source and drain regions contain a third layer region. The first layer region is located on the side closer to the channel region; the third layer region is located on the side farther from the channel region; and a second layer region is located between the first and third layer regions. The doping type of the second layer region is different from the doping types of the first and third layer regions, or the second layer region is an intrinsically undoped region. This invention can reduce the parasitic capacitance of the transistor and improve its response speed.

The invention discloses a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the steps of providing a substrate; forming a channel bulge structure on the substrate, wherein the channel bulge structure comprises a channel bulge part and a first sacrificial layer on the channel bulge part; forming a pseudo gate structure crossing the channel bulge structure, wherein the pseudo gate structure covers part of the top and the side wall of the channel bulge structure; after the pseudo gate structure is formed, the pseudo gate structure and the first sacrificial layer at the bottom of the pseudo gate structure are sequentially removed, and the removal selection ratio between the first sacrificial layer and the channel protruding part is larger than the removal selection ratio between the pseudo gate structure and the channel protruding part. According to the embodiment of the invention, the first sacrificial layer can reduce the probability that the top of the channel lug boss is damaged in the process of removing the pseudo gate structure; and the removal selection ratio between the first sacrificial layer and the channel lug boss is greater than the removal selection ratio between the pseudo gate structure and the channel lug boss, so that the damage probability of the top of the channel lug boss can be reduced in the process of removing the first sacrificial layer.

This invention discloses a high PSR, low power consumption, capacitor-free N-type low-dropout linear regulator, belonging to the field of analog integrated circuits. The regulator includes an error amplifier, a voltage buffer, a PSR enhancement circuit, and an NMOS power transistor. The voltage buffer uses a unity-gain negative feedback configuration, employing a smaller quiescent current at the same output impedance. At the output voltage... V OUT When the voltage rises, the error amplifier and voltage buffer suppress the rise through a negative feedback loop. V OUT To achieve circuit stability, the PSR enhancement circuit uses a high-pass filter for sampling. V OUT Ripple at mid-to-high frequencies creates negative feedback, generating gain that acts on... V OUT This ultimately improves power supply rejection at mid-to-high frequencies. Compared to PMOS transistors, using NMOS transistors as power transistors allows for a smaller footprint while maintaining the same current. This invention offers advantages such as low power consumption, high PSR, and small footprint, making it suitable for mobile smart terminals, embedded systems, low-power IoT devices, and various high-precision analog circuit systems sensitive to power supply noise.

The invention provides a process processing method for an out-of-plane capacitive micro-electromechanical accelerometer, and the method comprises the steps: S1, bonding a silicon electrode layer on the upper surface of a TSV layer, and carrying out the dry etching of the silicon electrode layer, and obtaining an independent silicon electrode and a sealing ring; preparing a bonding dielectric layer on the upper surface of the silicon electrode layer; s2, bonding a structural layer on the lower surface of the cover plate layer, processing a capacitor gap in the lower surface of the structural layer through wet etching, and then forming a seesaw structure through dry etching; s3, aligning the seesaw structure of the structural layer with the silicon electrode, and bonding the lower surface of the structural layer with the upper surface of the bonding dielectric layer to obtain a capacitor gap; and S4, metalizing the through hole of the TSV layer, and leading out an electric signal of the silicon electrode to the lower surface of the TSV layer. And z-axis accelerometer detection can be realized, and a solution is provided for design and manufacturing of a surface external speedometer.