111results about How to "Reduce layout area" patented technology

The invention discloses an external bias pixel structure of a light receiving stage circuit in a dynamic vision sensor pixel. The external bias pixel structure comprises a photodiode, a logarithmic tube, an amplifier tube, a switch tube and a bias tube, the bias tube, the switch tube and the amplifier tube are sequentially connected in series, a source electrode of the bias tube is connected with a power supply, a drain electrode of the bias tube is connected with a drain electrode of the switch tube, a source electrode of the switch tube is connected with a drain electrode of the amplifier tube, and a source electrode of the amplifier tube is grounded; the grid electrode of the bias tube is in signal connection with Vbias, the grid electrode of the switch tube is in signal connection with Vcpr, the source electrode of the switch tube and the drain electrode of the amplifier tube are connected with the grid electrode of the logarithmic tube, the drain electrode of the logarithmic tube is connected with a power supply, the source electrode of the logarithmic tube is connected with the negative electrode of the photodiode, and the positive electrode of the photodiode is grounded. And a grid electrode of the amplifier tube is also connected between the source electrode of the logarithmic tube and the negative electrode of the photodiode.

The invention provides a static random access memory mismatch test structure and a test method, the static random access memory mismatch test structure comprises a plurality of rows of ring oscillators with different stages, a decoder and a multiplexer, and the stages of each row of ring oscillators are sequentially increased. The ring oscillator in each row comprises a plurality of first phase inverters connected in series and a plurality of second phase inverters connected in series, the input ends of the plurality of first phase inverters are connected in series with the output ends of the plurality of second phase inverters, each first phase inverter is composed of a first PMOS tube and a first NMOS tube in the storage unit, and each second phase inverter is composed of a second PMOS tube and a second NMOS tube in the storage unit. The first phase inverter is composed of a first PMOS transistor and a first NMOS transistor in the memory cell, the second phase inverter is composed of a second PMOS transistor and a second NMOS transistor in the memory cell, so that the layout area of the static random access memory mismatch test structure is smaller than that of an existing mismatch device test structure, and the area occupied by the static random access memory mismatch test structure is saved.

The embodiment of the invention discloses a display panel and a display device, according to the display panel and the display device, circuit modules correspondingly connected to sub-pixels of a display light-transmitting area are arranged in the display light-transmitting area, so that the signal transmission distance between the circuit modules and the sub-pixels is shortened; therefore, the duration uniformity of sub-pixel receiving signals in a display light-transmitting area is improved. Secondly, the circuit modules are arranged at the intersections of the signal wires, so that the arrangement area of the circuit modules and the signal wires can be reduced, and the light transmittance of the display light-transmitting area is improved; besides, part of the sub-pixels are overlapped with the circuit module and part of the sub-pixels are overlapped with the signal wires, so that the light-transmitting area is increased, and the light transmittance of the display light-transmitting area is improved.

The invention relates to a high-voltage level shift circuit and a layout structure thereof, and the high-voltage level shift circuit comprises a pulse generation module which is used for receiving an input signal and generating a double-path low-voltage domain narrow pulse signal; the level shift module is used for receiving the low-voltage domain narrow pulse signal and converting the low-voltage domain narrow pulse signal into a corresponding double-path high-voltage domain narrow pulse signal; the voltage transient noise detection module is used for detecting voltage transient noise and generating a transient noise intensity signal; the voltage transient noise filtering module is used for filtering voltage transient noise based on the received transient noise intensity signal to generate a double-path high-voltage domain filtering signal; and the RS trigger is used for converting the received high-voltage domain filtering signal into a high-side power device driving signal. The common-mode noise filtering capability and the VS negative bias resisting capability of the voltage transient noise filtering module can be enhanced, the transmission delay of a chip is effectively reduced, and the width of a narrow pulse signal is free of loss in the transmission process, so that the dynamic power consumption is reduced.

The utility model provides a low dropout linear regulator, which comprises a flip voltage follower, the flip voltage follower comprises a cascode current mirror, a power tube and a voltage control circuit, the voltage control circuit comprises an error amplifier, the error amplifier forms a voltage follower and is connected to the power tube through the cascode current mirror, and the power tube is connected to the flip voltage follower through the cascode current mirror. The output voltage of the low-dropout linear voltage regulator is stabilized at the reference voltage, the flip voltage follower is adopted, an off-chip capacitor does not need to be arranged, and compared with a traditional low-dropout linear voltage regulator based on a resistor voltage division feedback structure, the low-dropout linear voltage regulator is higher in circuit stability and faster in transient response, so that the low-dropout linear voltage regulator has wider application scenes.

The invention provides an EMI (Electro-Magnetic Interference) low-pass filter integrated with electrostatic and surge protection functions, which comprises a first TVS (Transient Voltage Suppressor) structure provided with a first P-type well region and a grounded P + heavily-doped active region, a second TVS structure provided with a floating second P-type well region and a grounded P + heavily-doped active region, N + heavily-doped active regions and N + heavily-doped active regions are arranged in the first P-type well region and the second P-type well region, and N + heavily-doped active regions are arranged in the first P-type well region and the second P-type well region. The bottom of the N-type semiconductor substrate is grounded, a forward ESD path in the vertical direction is formed between the N + heavily doped active region in the first P-type well region and the bottom of the N-type semiconductor substrate, and a reverse ESD path in the horizontal direction is formed between the P + heavily doped active region of the first TVS structure and the N + heavily doped active region in the first P-type well region. The second TVS structure is also formed with a forward ESD path and a reverse ESD path. The circuit has the beneficial effects that a high-frequency signal suppression function and electrostatic and surge protection capability can be realized.

The invention provides an infrared detector reading circuit based on a dark current suppression structure, which comprises a dark current suppression circuit, an integrating circuit, a double sampling circuit, a source follower, a differential amplification circuit and an output buffer circuit which are electrically connected in sequence, and also comprises a sequential logic circuit, the dark current suppression circuit is used for generating a controllable current which is not influenced by temperature change, and the current is mirrored and then used for counteracting the dark current of the infrared detector; the sequential logic circuit is used for providing row selection logic, column selection logic and a sampling time sequence when a target pixel is selected from an infrared detector pixel array; the reading circuit can read the current signal of the target pixel according to the row selection logic, the column selection logic and the sampling time sequence; according to the invention, the signal-to-noise ratio of the readout system is improved by suppressing dark current, the function of reading out according to the column is realized based on the sequential logic circuit, the noise interference among the readout circuits in the array can be effectively reduced, and the focal plane array readout circuit is suitable for preparing a large-array-scale focal plane array readout circuit.

The invention provides a low clamp voltage type EMI filter integrated with an electrostatic protection function, which comprises an N-type semiconductor substrate, an NPN triode Q1, an NPN triode Q2 and a resistor R. The NPN triode Q1 is provided with a first P-type well region, the NPN triode Q2 is provided with a second P-type well region, the first P-type well region is internally provided with a grounded P + heavily doped active region and an N + heavily doped active region connected with a first I / O port, and the second P-type well region is provided with a second P + heavily doped active region connected with a second I / O port. The bottom of the N-type semiconductor substrate is grounded, a forward ESD path in the vertical direction is formed between the N + heavily doped active region in the first P-type well region and the bottom of the N-type semiconductor substrate, a reverse ESD path in the horizontal direction is formed between the P + heavily doped active region and the N + heavily doped active region in the first P-type well region, and the second P-type well region and the first P-type well region are the same in structure. The beneficial effect of the invention is that dual functions of electrostatic protection and electromagnetic interference filtering can be realized at the same time.

The utility model is applicable to the field of radio frequency filtering, and discloses a resonator, a filter and a radio frequency front-end module, the resonator comprises a piezoelectric substrate and an interdigital transducer, and the interdigital transducer comprises a first bus bar and a second bus bar which are oppositely arranged along a first direction; the at least one first electrode finger, the at least one second electrode finger and the at least one suspension electrode are located between the first bus bar and the second bus bar, the first electrode fingers, the suspension electrodes and the second electrode fingers are arranged at intervals in the second direction, and the first electrode fingers and the second electrode fingers are arranged in a staggered mode in the second direction; in the second direction, the suspension electrodes and the main body parts of the first electrode fingers are alternately arranged and mutually overlapped to form a first resonance unit, and the suspension electrodes and the main body parts of the second electrode fingers are alternately arranged and mutually overlapped to form a second resonance unit. According to the resonator, the layout area can be reduced, and the performance of the resonator can be improved.

The invention discloses an LDO (Low Dropout Regulator) circuit based on current feedback, which comprises a transconductance amplifier for amplifying reference voltage into current and inputting the current into a positive phase input end of an error transresistance amplifier; the error transimpedance amplifier, the buffer, the second PMOS transistor, the first PMOS transistor and the current-current feedback network form an error current feedback loop, the negative phase input end of the error transimpedance amplifier receives feedback current from the current-current feedback network, and the output end of the error transimpedance amplifier outputs error voltage; the buffer receives the error voltage output by the error trans-impedance amplifier, generates a buffer stage output voltage and drives the second PMOS tube to generate an output voltage; the first PMOS transistor is used for detecting fluctuation of output voltage, if the output voltage fluctuates, current flowing through the first PMOS transistor changes, the current-current feedback network generates feedback current according to the current change of the first PMOS transistor, the feedback current is input to the negative phase input end of the error trans-impedance amplifier, and fluctuation of the output voltage is counteracted.

The invention provides an anti-backflow ESD protection circuit and system, and relates to the technical field of ESD protection. The anti-backflow ESD protection circuit comprises a plurality of MOS tubes and a plurality of resistors, the MOS tubes are connected in parallel, the source electrode and the drain electrode of each MOS tube are connected with one resistor, and the source electrodes or the drain electrodes of every two adjacent MOS tubes share the same resistor; wherein the plurality of MOS tubes share the source electrode and the drain electrode, and when the anti-backflow ESD protection circuit is switched on, the current flowing through each unit resistor is equal. The anti-backflow ESD protection circuit and the anti-backflow ESD protection system provided by the invention have the advantage that the layout occupied area is reduced under the condition that the ESD requirement is met.

The embodiment of the invention provides a phase shifter, an integrated transceiving channel and a phased array system. The phase shifter comprises a first phase shifting unit, a second phase shifting unit, a third phase shifting unit, a fourth phase shifting unit, a fifth phase shifting unit and a sixth phase shifting unit, wherein the first phase shifting unit, the third phase shifting unit, the fourth phase shifting unit and the sixth phase shifting unit adopt a low-pass and band-pass switching type phase shifter structure; the second phase shifting unit and the fifth phase shifting unit adopt a high-pass and low-pass switching type phase shifter structure; and the phase shifter is used for performing phase shifting on the received signal when the configured signal receiving and transmitting device is used for receiving the signal, and performing phase shifting on the transmitted signal when the signal receiving and transmitting device is used for transmitting the signal. The phase shifter can realize a relatively large phase shifting range and has a relatively wide working frequency band, so that the phase shifter can be multiplexed when phase shifting is carried out on a receiving signal and a transmitting signal, and the overall layout area of a transceiving chip can be saved.

The embodiment of the invention provides a capacitance value determination method, a capacitance calibration method and an MOMCAP capacitance modeling method of a calibration test structure. The capacitance value determination method comprises the following steps: acquiring a test object comprising a plurality of groups of calibration structures, wherein the calibration structures are associated with the same MOMCAP standard test structure; selecting a plurality of groups of representative calibration structures from the plurality of groups of calibration structures according to a specific parameter combination; carrying out capacitance value testing on each group of selected calibration structures to obtain corresponding actually measured capacitance value data; based on the actually measured capacitance value data, analyzing and determining a function relationship between the calibration capacitance value and the selected parameter; and calculating capacitance values of other calibration structures with different parameter combinations by using the function relationship. According to the embodiment of the invention, the method efficiently obtains the call data of the MOMCAP capacitor, reduces the occupied area of a chip, reduces the test pressure, and improves the modeling efficiency of a device.

The invention relates to a small-pixel-size infrared detector reading circuit with a self-adaptive integrating capacitor, and belongs to the technical field of infrared detector reading circuits. According to the circuit, the NMOS variable capacitor is adopted to replace a traditional capacitor, and the characteristic that the capacitance value of the NMOS variable capacitor is adaptively adjusted along with the change of light intensity is utilized, so that the condition of supersaturation or underexposure of integral charge quantity is effectively avoided, and the dynamic range of the reading circuit is enlarged. Besides, the circuit adopts a folding cascode operational amplifier, good injection efficiency and linearity are guaranteed, the scheme that four pixels share one CTIA structure in a time-sharing mode is adopted, the layout area of the reading circuit is optimized, and the reading circuit can adapt to infrared detectors with smaller pixels and larger arrays. The circuit is simple in structure and easy to realize, has the advantages of low power consumption, wide dynamic range and the like, and is suitable for the design of an intelligent infrared detector reading circuit with high integration, low power consumption and wide dynamic range.

The invention discloses a reconfigurable logic unit based on a ferroelectric transistor, a control method and a reconfigurable logic system, and belongs to the technical field of integrated circuit design. The reconfigurable logic unit comprises a P-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a first N-type FeFET, a second N-type FeFET and a third N-type FeFET; wherein the first N-type FeFET and the second N-type FeFET are connected in parallel, drain electrodes of the first N-type FeFET and the second N-type FeFET are connected with a drain electrode of the P-type MOSFET, and source electrodes of the first N-type FeFET and the second N-type FeFET are connected with a drain electrode of the third N-type FeFET; the source electrode of the third N-type FeFET is grounded; according to the reconfigurable logic unit, the grid electrode of the N-FeFET serves as an input terminal, the polarization characteristic of a ferroelectric device is fully utilized, high-state threshold voltage and low-state threshold voltage can be separated under the control of polarization voltage, logic reconfiguration is achieved, and the reconfigurable logic unit has the advantages of being small in layout area, low in calculation power consumption, high in reconfiguration capacity, compatible with a CMOS, easy to process integration and the like.

The application discloses a low-power bandgap reference current source circuit and a control method, and the circuit comprises a current mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit and a current mirror circuit; the current mode bandgap circuit is internally provided with an error amplifier OPAMP and a proportional resistance network; the error amplifier input stage circuit is a PMOS pair tube input stage circuit; the threshold modulation circuit is a source-liner forward bias threshold modulation circuit, which is used for forward biasing the threshold voltage of all PMOS tubes in the low-power bandgap reference current source circuit and enabling the NMOS tube connected with the error amplifier OPAMP output stage to work in a saturation region; and the current mirror circuit is a series diode compensation method current mirror circuit structure. The application is compatible with a standard CMOS process, realizes sub-1V low voltage, micro-nano ampere level low power consumption, high-precision low-noise small area effect, solves various technical pain points of a traditional scheme, and has excellent application prospects in a wearable device power management system.

The application provides a chip internal bias current test circuit and a chip, and belongs to the field of semiconductor integrated circuit chips. A measured current mirror module, a test mirror module and a path control module are arranged in the chip. The measured current mirror module generates a bias current in the chip. The test mirror module is connected with the measured current mirror module, and mirrors the bias current when the test mirror module is turned on, so as to adjust the total current of the chip. When the control signal is a first level, the path control module controls the test mirror module to be disconnected. When the control signal is a second level, the path control module controls the test mirror module to be turned on. The detection processing module is connected with the power supply of the chip, and detects the first total current of the chip when the circuit is disconnected and the second total current of the chip when the circuit is turned on, so as to determine the bias current. No additional special test chip peripheral pin is needed, the layout area is reduced, and the problems in the prior art are solved.

The disclosed embodiment discloses a layout of a delay circuit unit, a layout of a delay circuit, and a semiconductor memory, wherein the layout of the delay circuit unit includes a plurality of layout units, the layout units are used to form a NAND gate circuit, and the layout units are arranged in an array; wherein, in the first row of the array, a plurality of layout units conforming to a first layout mode are sequentially arranged; and in the second row of the array, a plurality of layout units conforming to a second layout mode are sequentially arranged; wherein, the first layout mode is different from the second layout mode, and the first layout mode and the second layout mode make the first row and the second row present a central symmetrical structure. In this way, it is not only conducive to achieving the consistency of delay between signals of different phases, but also the overall layout of the delay circuit unit is compact, and the layout area can be saved.

The embodiment of the invention relates to the technical field of semiconductors, and provides a storage unit structure, a manufacturing method thereof and a storage unit array structure, and the storage unit structure comprises a first transistor, a storage region and a second transistor which are in contact connection in sequence along a first direction; the first transistor comprises a first doped region, a second doped region and a third doped region which are in contact connection in sequence in the second direction, the second transistor comprises a fourth doped region, a fifth doped region and a sixth doped region which are in contact connection in sequence in the second direction, and the storage region is provided with a first side and a second side which are opposite in the first direction; the second doped region is in contact connection with the first side, and the fifth doped region is in contact connection with the second side; the first doped region, the third doped region, the fourth doped region and the sixth doped region are all doped with first doped ions, and the second doped region, the storage region and the fifth doped region are all doped with second doped ions. The embodiment of the invention at least can be beneficial to improving the electrical performance of the storage unit structure.

The invention discloses a power amplification circuit and a radio frequency module. The power amplification circuit comprises a power amplification module and a bias module. The power amplification module comprises M first power amplifiers and M second power amplifiers, the M first power amplifiers are correspondingly connected to the M first signal ends, and the M second power amplifiers are correspondingly connected to the M second signal ends. The bias module comprises a first bias unit and a second bias unit, the first bias unit is connected to the M first signal ends, and the second bias unit is connected to the M second signal ends. The phases of M paths of radio frequency signals input by the M first power amplifiers are roughly the same, and the phases of M paths of radio frequency signals input by the M second power amplifiers are roughly the same, so that bias signals can be provided for the M first power amplifiers and the M second power amplifiers by arranging the first bias unit and the second bias unit; the circuit structure of the power amplification circuit is simplified, and the layout area is reduced.

The invention belongs to the technical field of phase-locked loops and filters, and particularly relates to an active loop filter for a low-jitter phase-locked loop. The pulse signal selection circuit and the signal transmission circuit provide stable input for the operational amplifier circuit; a resistance-capacitance circuit which cooperates with the operational amplifier circuit to realize frequency selection and amplitude control of the input signal; and the operational amplifier circuit is used for enhancing the amplitude of the output signal of the charge pump and converting the current signal into a stable voltage signal. The signal transmission circuit can reduce burrs and overshoot of signals, is good in voltage transmission characteristic, high in noise margin, high in anti-interference capability and low in power consumption, and can provide stable signals as input of an operational amplifier, so that the jitter performance of a phase-locked loop is optimized.

The invention provides a radio frequency front-end module and electronic equipment. The radio frequency front-end module comprises a radio frequency power amplifier, a coupler, a filter, a switch, a first input / output end, a second input / output end and an antenna end, the radio frequency power amplifier comprises a transmitting end, and the coupler comprises a power detection end and a receiving end; the switch comprises a frequency band selection end, and the antenna end is electrically connected with the output end of the switch; the first input and output end is used for receiving a working state signal of an external network; and the second input / output end is used for outputting a working state signal of the radio frequency front-end module. The radio frequency power amplifier, the coupler, the filter and the switch are integrated into the radio frequency front-end module, so that an ultrahigh-frequency radio frequency identification product is optimized, the ultrahigh-frequency radio frequency identification product is simpler and more efficient, and the arrangement area of devices is reduced. The first input / output end and the second input / output end are introduced, so that the influence between the ultrahigh-frequency radio frequency identification product and the cellular network when the ultrahigh-frequency radio frequency identification product and the cellular network work at the same time is reduced.

The present application provides a magnetoresistive random access memory and a preparation method thereof, which relates to the field of semiconductor technology and is used to solve the technical problem of low reliability of data writing and storage. The magnetoresistive random access memory includes: a substrate, a bottom electrode layer arranged on the substrate, and at least two magnetic tunnel junctions arranged on the bottom electrode layer; the bottom electrode layer includes at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear; each electrode part has at least one magnetic tunnel junction; when a write current is applied to the bottom electrode layer, one of the at least two magnetic tunnel junctions has a first resistance state, and the other of the at least two magnetic tunnel junctions has a second resistance state, so that the resistance between the at least two magnetic tunnel junctions forms a differential state. The present application can improve the success rate of data writing, thereby improving the reliability of data storage of the magnetoresistive random access memory.

This application provides a readout module, pixel unit and manufacturing method, pixel array and image sensor, including at least two readout circuits. Each readout circuit includes at least two first readout sub-modules, a floating diffusion node, and a second readout sub-module. The first readout sub-module is connected between the charge output terminal of the photosensitive module and the floating diffusion node, and the second readout sub-module is connected to the floating diffusion node. Each first readout sub-module can read an electrical signal of one phase, so the readout circuit can read at least two electrical signals of different phases. Correspondingly, the readout module can output at least four electrical signals of different phases, thereby ensuring that at least four electrical signals of different phases are read synchronously within a single frame. Furthermore, each readout circuit reuses one floating diffusion node and one second readout sub-module, which helps to reduce the layout area, improve the overall chip resolution, and reduce fixed-mode noise of the pixels.

The application relates to a microstrip coupler, a circuit board and a communication device. The microstrip coupler comprises a first ground layer, a first dielectric layer, a second ground layer, a coupling line, a second dielectric layer, a third ground layer and a signal line. The first projection of the coupling line on the third ground layer in the direction perpendicular to the third ground layer is completely non-overlapped with the second hollow area, and the second projection of the signal line on the second ground layer in the direction perpendicular to the second ground layer is completely non-overlapped with the first hollow area. Thus, a cavity is not needed on the signal line as in the related art, so that the product volume of the microstrip coupler can be reduced, miniaturization design is realized, the line length of the output end and the input end of the signal line can be reduced, the insertion loss is reduced, and the output efficiency of the power amplifier is improved; the coupling line and other devices located on both sides of the signal line do not interfere with each other, so that the signal can be normally and stably transmitted; in addition, the product area is reduced, which is beneficial to the arrangement of other devices.

The invention provides an efuse unit and a layout structure thereof, the efuse unit comprises a double-gate-end NMOS tube and an AA fuse, the NMOS tube is a four-port (ports G1, G2, S and BL) device formed by connecting an N0 tube and an N1 tube in series, the AA fuse is connected with the N1 tube in parallel, the gate end of the N1 tube is the port G2, the gate end of the N0 tube is the port G1, the source end of the N1 tube is the port S, one end of the AA fuse is connected with the drain end of the N0 tube and the drain end of the N1 tube, and the other end of the AA fuse is connected with the drain end of the N0 tube and the drain end of the N1 tube. And the other end of the AA fuse is connected with the source end of the N1 tube and is a port BL. The fuse and the MOS tube are integrated, so that the layout area of the efuse unit array can be reduced, the layout working efficiency is improved, and meanwhile, the reliability of a system and the fuse is improved.

The invention discloses a transmitter circuit with ringing suppression, which is suitable for being applied to a controller area network. The transmitter circuit comprises a controller area network bus driving circuit, a first operational transduction amplifier, a second operational transduction amplifier and a controller area network bus driving circuit, wherein the controller area network bus driving circuit is used for receiving a transmission data signal and generating a controller area network high-level signal and a controller area network low-level signal; the first operational transduction amplifier is used for receiving the controller area network high-level signal; and a second operational transduction amplifier for receiving the controller area network low level signal. A common-mode voltage signal in a dominant state and a control signal are adopted, and when the control signal is at a high voltage level, the first operation transduction amplifier and the second operation transduction amplifier can actively adjust high and low level signals of a controller area network to be consistent with the common-mode voltage, so that the ringing problem on a bus is inhibited and eliminated.

The invention discloses a universal test system for radio frequency industry, relates to the field of radio frequency test technology, a data board includes a system power supply and a plurality of preset peripheral interfaces; a core board includes a main chip, an interface circuit connected between the core board and the data board, a main chip peripheral circuit, a power configuration circuit and a power early warning circuit; a test board includes an ADC input circuit, a DAC output circuit, and an interface circuit connected between the test board and the core board; a three-layer structure design is adopted, which is sequentially a test board, a core board and a data board from top to bottom, the test board is connected to the core board through a first connecting component, the core board is connected to the data board through a second connecting component, and the test board is connected to the data board through a third connecting component. The test system of the present invention not only reduces the layout area occupied by the entire test system, but also facilitates the unified power management of the test system, and also solves the problem that the test cannot be completed or the test fails due to power anomaly.

The present invention discloses a cross-power domain electrostatic discharge protection circuit, wherein a clamping circuit 1 is connected between VDD1 and VSS1, a device SCR1 is connected between VDD1 and VSS2, the anode of SCR1 is connected to VDD1, the cathode of SCR1 is connected to VSS2, and the P well of SCR1 is connected to VSS1; a clamping circuit 2 is connected between VDD2 and VSS2, a device SCR2 is connected between VDD2 and VSS2, the anode of SCR2 is connected to VDD2, the cathode of SCR2 is connected to VSS1, and the P well of SCR2 is connected to VSS2. The structure of the present invention only needs to expand the isolation diode in the traditional solution into an SCR device and make appropriate connections, the increased layout area is small, the expanded SCR device can be formed by the most basic structure, and no additional trigger circuit is required.

The present disclosure provides a data error correction circuit and a data transmission method. The data transmission circuit includes: a data error correction module, receiving first data and a first check code corresponding to the first data, the data error correction module is used to correct the first data according to the first check code to generate second data, and output the second data; a check code generation module, receiving the first data and the first check code, and generating and outputting a second check code according to the first data and the first check code. The embodiments of the present disclosure can save the components and layout area required for the data error correction function.