43results about How to "Reduce layout area" patented technology

The invention discloses an external bias pixel structure of a light receiving stage circuit in a dynamic vision sensor pixel. The external bias pixel structure comprises a photodiode, a logarithmic tube, an amplifier tube, a switch tube and a bias tube, the bias tube, the switch tube and the amplifier tube are sequentially connected in series, a source electrode of the bias tube is connected with a power supply, a drain electrode of the bias tube is connected with a drain electrode of the switch tube, a source electrode of the switch tube is connected with a drain electrode of the amplifier tube, and a source electrode of the amplifier tube is grounded; the grid electrode of the bias tube is in signal connection with Vbias, the grid electrode of the switch tube is in signal connection with Vcpr, the source electrode of the switch tube and the drain electrode of the amplifier tube are connected with the grid electrode of the logarithmic tube, the drain electrode of the logarithmic tube is connected with a power supply, the source electrode of the logarithmic tube is connected with the negative electrode of the photodiode, and the positive electrode of the photodiode is grounded. And a grid electrode of the amplifier tube is also connected between the source electrode of the logarithmic tube and the negative electrode of the photodiode.

The embodiment of the invention discloses a display panel and a display device, according to the display panel and the display device, circuit modules correspondingly connected to sub-pixels of a display light-transmitting area are arranged in the display light-transmitting area, so that the signal transmission distance between the circuit modules and the sub-pixels is shortened; therefore, the duration uniformity of sub-pixel receiving signals in a display light-transmitting area is improved. Secondly, the circuit modules are arranged at the intersections of the signal wires, so that the arrangement area of the circuit modules and the signal wires can be reduced, and the light transmittance of the display light-transmitting area is improved; besides, part of the sub-pixels are overlapped with the circuit module and part of the sub-pixels are overlapped with the signal wires, so that the light-transmitting area is increased, and the light transmittance of the display light-transmitting area is improved.

The invention provides an infrared detector reading circuit based on a dark current suppression structure, which comprises a dark current suppression circuit, an integrating circuit, a double sampling circuit, a source follower, a differential amplification circuit and an output buffer circuit which are electrically connected in sequence, and also comprises a sequential logic circuit, the dark current suppression circuit is used for generating a controllable current which is not influenced by temperature change, and the current is mirrored and then used for counteracting the dark current of the infrared detector; the sequential logic circuit is used for providing row selection logic, column selection logic and a sampling time sequence when a target pixel is selected from an infrared detector pixel array; the reading circuit can read the current signal of the target pixel according to the row selection logic, the column selection logic and the sampling time sequence; according to the invention, the signal-to-noise ratio of the readout system is improved by suppressing dark current, the function of reading out according to the column is realized based on the sequential logic circuit, the noise interference among the readout circuits in the array can be effectively reduced, and the focal plane array readout circuit is suitable for preparing a large-array-scale focal plane array readout circuit.

The utility model is applicable to the field of radio frequency filtering, and discloses a resonator, a filter and a radio frequency front-end module, the resonator comprises a piezoelectric substrate and an interdigital transducer, and the interdigital transducer comprises a first bus bar and a second bus bar which are oppositely arranged along a first direction; the at least one first electrode finger, the at least one second electrode finger and the at least one suspension electrode are located between the first bus bar and the second bus bar, the first electrode fingers, the suspension electrodes and the second electrode fingers are arranged at intervals in the second direction, and the first electrode fingers and the second electrode fingers are arranged in a staggered mode in the second direction; in the second direction, the suspension electrodes and the main body parts of the first electrode fingers are alternately arranged and mutually overlapped to form a first resonance unit, and the suspension electrodes and the main body parts of the second electrode fingers are alternately arranged and mutually overlapped to form a second resonance unit. According to the resonator, the layout area can be reduced, and the performance of the resonator can be improved.

The invention provides an anti-backflow ESD protection circuit and system, and relates to the technical field of ESD protection. The anti-backflow ESD protection circuit comprises a plurality of MOS tubes and a plurality of resistors, the MOS tubes are connected in parallel, the source electrode and the drain electrode of each MOS tube are connected with one resistor, and the source electrodes or the drain electrodes of every two adjacent MOS tubes share the same resistor; wherein the plurality of MOS tubes share the source electrode and the drain electrode, and when the anti-backflow ESD protection circuit is switched on, the current flowing through each unit resistor is equal. The anti-backflow ESD protection circuit and the anti-backflow ESD protection system provided by the invention have the advantage that the layout occupied area is reduced under the condition that the ESD requirement is met.

The embodiment of the invention provides a capacitance value determination method, a capacitance calibration method and an MOMCAP capacitance modeling method of a calibration test structure. The capacitance value determination method comprises the following steps: acquiring a test object comprising a plurality of groups of calibration structures, wherein the calibration structures are associated with the same MOMCAP standard test structure; selecting a plurality of groups of representative calibration structures from the plurality of groups of calibration structures according to a specific parameter combination; carrying out capacitance value testing on each group of selected calibration structures to obtain corresponding actually measured capacitance value data; based on the actually measured capacitance value data, analyzing and determining a function relationship between the calibration capacitance value and the selected parameter; and calculating capacitance values of other calibration structures with different parameter combinations by using the function relationship. According to the embodiment of the invention, the method efficiently obtains the call data of the MOMCAP capacitor, reduces the occupied area of a chip, reduces the test pressure, and improves the modeling efficiency of a device.

The application discloses a low-power bandgap reference current source circuit and a control method, and the circuit comprises a current mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit and a current mirror circuit; the current mode bandgap circuit is internally provided with an error amplifier OPAMP and a proportional resistance network; the error amplifier input stage circuit is a PMOS pair tube input stage circuit; the threshold modulation circuit is a source-liner forward bias threshold modulation circuit, which is used for forward biasing the threshold voltage of all PMOS tubes in the low-power bandgap reference current source circuit and enabling the NMOS tube connected with the error amplifier OPAMP output stage to work in a saturation region; and the current mirror circuit is a series diode compensation method current mirror circuit structure. The application is compatible with a standard CMOS process, realizes sub-1V low voltage, micro-nano ampere level low power consumption, high-precision low-noise small area effect, solves various technical pain points of a traditional scheme, and has excellent application prospects in a wearable device power management system.

The application provides a chip internal bias current test circuit and a chip, and belongs to the field of semiconductor integrated circuit chips. A measured current mirror module, a test mirror module and a path control module are arranged in the chip. The measured current mirror module generates a bias current in the chip. The test mirror module is connected with the measured current mirror module, and mirrors the bias current when the test mirror module is turned on, so as to adjust the total current of the chip. When the control signal is a first level, the path control module controls the test mirror module to be disconnected. When the control signal is a second level, the path control module controls the test mirror module to be turned on. The detection processing module is connected with the power supply of the chip, and detects the first total current of the chip when the circuit is disconnected and the second total current of the chip when the circuit is turned on, so as to determine the bias current. No additional special test chip peripheral pin is needed, the layout area is reduced, and the problems in the prior art are solved.

The present application provides a magnetoresistive random access memory and a preparation method thereof, which relates to the field of semiconductor technology and is used to solve the technical problem of low reliability of data writing and storage. The magnetoresistive random access memory includes: a substrate, a bottom electrode layer arranged on the substrate, and at least two magnetic tunnel junctions arranged on the bottom electrode layer; the bottom electrode layer includes at least two electrode parts connected in sequence, an angle is formed between two adjacent electrode parts, and the two adjacent electrode parts are not collinear; each electrode part has at least one magnetic tunnel junction; when a write current is applied to the bottom electrode layer, one of the at least two magnetic tunnel junctions has a first resistance state, and the other of the at least two magnetic tunnel junctions has a second resistance state, so that the resistance between the at least two magnetic tunnel junctions forms a differential state. The present application can improve the success rate of data writing, thereby improving the reliability of data storage of the magnetoresistive random access memory.

This application provides a readout module, pixel unit and manufacturing method, pixel array and image sensor, including at least two readout circuits. Each readout circuit includes at least two first readout sub-modules, a floating diffusion node, and a second readout sub-module. The first readout sub-module is connected between the charge output terminal of the photosensitive module and the floating diffusion node, and the second readout sub-module is connected to the floating diffusion node. Each first readout sub-module can read an electrical signal of one phase, so the readout circuit can read at least two electrical signals of different phases. Correspondingly, the readout module can output at least four electrical signals of different phases, thereby ensuring that at least four electrical signals of different phases are read synchronously within a single frame. Furthermore, each readout circuit reuses one floating diffusion node and one second readout sub-module, which helps to reduce the layout area, improve the overall chip resolution, and reduce fixed-mode noise of the pixels.

The application relates to a microstrip coupler, a circuit board and a communication device. The microstrip coupler comprises a first ground layer, a first dielectric layer, a second ground layer, a coupling line, a second dielectric layer, a third ground layer and a signal line. The first projection of the coupling line on the third ground layer in the direction perpendicular to the third ground layer is completely non-overlapped with the second hollow area, and the second projection of the signal line on the second ground layer in the direction perpendicular to the second ground layer is completely non-overlapped with the first hollow area. Thus, a cavity is not needed on the signal line as in the related art, so that the product volume of the microstrip coupler can be reduced, miniaturization design is realized, the line length of the output end and the input end of the signal line can be reduced, the insertion loss is reduced, and the output efficiency of the power amplifier is improved; the coupling line and other devices located on both sides of the signal line do not interfere with each other, so that the signal can be normally and stably transmitted; in addition, the product area is reduced, which is beneficial to the arrangement of other devices.

The invention discloses a transmitter circuit with ringing suppression, which is suitable for being applied to a controller area network. The transmitter circuit comprises a controller area network bus driving circuit, a first operational transduction amplifier, a second operational transduction amplifier and a controller area network bus driving circuit, wherein the controller area network bus driving circuit is used for receiving a transmission data signal and generating a controller area network high-level signal and a controller area network low-level signal; the first operational transduction amplifier is used for receiving the controller area network high-level signal; and a second operational transduction amplifier for receiving the controller area network low level signal. A common-mode voltage signal in a dominant state and a control signal are adopted, and when the control signal is at a high voltage level, the first operation transduction amplifier and the second operation transduction amplifier can actively adjust high and low level signals of a controller area network to be consistent with the common-mode voltage, so that the ringing problem on a bus is inhibited and eliminated.

The present application provides a radio frequency receiver and a wireless communication device, the radio frequency receiving device comprising: a first receiver comprising a first receiving channel and a second receiving channel. A second receiver comprising a third receiving channel, wherein the maximum signal bandwidth supported by the first receiving channel and the second receiving channel is less than the maximum signal bandwidth supported by the third receiving channel. An analog-to-digital converter ADC group, comprising a plurality of ADCs including a first ADC and a second ADC. A channel selector is used to allocate ADCs. When the channel selector is in a first state, the first receiving channel is coupled to the first ADC, and the second receiving channel is coupled to the second ADC. When the channel selector is in a second state, the third receiving channel is coupled to the first ADC and the second ADC. In the above scheme, the channel selector selects different ADCs to match the first receiver and the second receiver, thereby reducing the number of ADCs, reducing the volume and area of ​​the radio frequency receiving device, and reducing costs.

The invention discloses an eccentric swinging head, which belongs to the technical field of swinging heads and comprises a main shaft and a swinging shaft, the main shaft is arranged on one side of the swing shaft and can swing around the swing shaft, and eccentricity is arranged between the main shaft and the swing shaft. According to the eccentric swing head disclosed by the invention, the eccentricity is set between the main shaft and the swing shaft, so that the stroke range of the main shaft can be enlarged after the main shaft swings or when the main shaft swings, and the coverage range of the main shaft is enlarged; therefore, the machining range of the machine tool can be expanded to the greatest extent under the condition that the layout size of the machine tool and the movement strokes of other equipment parts of the machine tool are not changed, and meanwhile, a certain eccentricity is arranged between the main shaft and the swing shaft, so that the distance between the main shaft and parts possibly generating interference can be increased, and the machining efficiency is improved. Therefore, the main shaft does not interfere with other parts of the machine tool in position when rotating and swinging, collision and damage between equipment parts can be effectively avoided, and smooth machining is guaranteed.

The application discloses an LED backlight drive chip, which comprises an LED pin, a high-voltage MOS switch tube M1, a low-voltage drive current MOS switch tube M2, an operational amplifier, a drive resistor and a pre-charge module; the pre-charge module comprises a pre-charge MOS switch tube M3, a pre-charge power supply and a pre-charge control unit. The LED backlight drive chip utilizes the body diode characteristics of the high-voltage MOS tube, sets the control MOS tube in the pre-charge circuit as a low-voltage device, thereby reducing the layout area of the semiconductor integrated circuit. And the fast response characteristics of the low-voltage MOS device are utilized to improve the pre-charge efficiency.

The invention discloses a low-delay low-power-consumption level conversion circuit based on a charge pump, the circuit comprises a charge pump circuit, an internal conversion circuit and a latch circuit, the output end of the charge pump circuit is connected with the input end of the internal conversion circuit, and the output end of the internal conversion circuit is connected with the input end of the latch circuit. According to the invention, the voltage conversion range can be enlarged, and low time delay and low power consumption are realized. The low-delay low-power-consumption level conversion circuit based on the charge pump can be widely applied to the technical field of integrated circuits.

The invention provides a multiplexing system of a single-ended to differential signal driver and a detector reading chip, and belongs to the technical field of active electrical nonlinear devices. The system comprises a multi-channel capacitance trans-impedance amplifier, a corresponding ping-pong type switched capacitor sampling hold circuit, a multiplexer, a single-ended to differential signal driver and an ADC (Analog to Digital Converter). A capacitance trans-impedance amplifier of a selected channel receives an X-ray signal responded by a photoelectric sensor, voltage passes through a corresponding switched capacitor sampling holding circuit, and signal charges are stored on a group of holding capacitors; the ADC is connected to the input end of the single-ended to differential signal driver through the multiplexer and performs ADC quantization output; the single-ended to differential signal driver is of a switched capacitor type circuit structure. According to the invention, a unit gain voltage buffer required for driving CTIA output voltage during multi-channel switching is saved, extra noise introduced by Buffer is removed, and power consumption and layout area are reduced.

The embodiment of the application provides a multiplex card holder and a mobile terminal, the multiplex card holder is used for being installed in a card slot of the mobile terminal, and the multiplex card holder comprises a card holder body, an antenna, a feeding point and a feeding point, at least one SIM card insertion cavity is arranged on the card holder body, the antenna is at least formed on one side end surface of the card holder body along a thickness direction, the antenna is arranged along an outer periphery of the SIM card insertion cavity, the feeding point and the feeding point are arranged on an outer side wall of the card holder body, the feeding point is electrically connected with a radiation end of the antenna, and the feeding point is electrically connected with a grounding point of the antenna, wherein the feeding point and the feeding point are configured to be electrically connected with corresponding contact points of the mobile terminal, by arranging the antenna on the card holder body, the antenna setting position limit can be reduced, the antenna performance is improved, and the anti-interference capability is enhanced.

The invention provides a chip, a circuit board and mobile equipment, relates to the technical field of charging, and can solve the problems of poor integration level, high cost and low software development efficiency of a current mobile phone power transmission protocol chip and switch charging chip separation scheme. The chip comprises a charging sub-chip and a communication sub-chip, the first communication pin and the second communication pin are electrically connected with the communication sub-chip and are used for communication between the communication sub-chip and a charger; and the first power transmission interruption pin is electrically connected with the communication sub-chip and is used for reporting a first power transmission interruption signal to the processor by the communication sub-chip, and the first power transmission interruption signal is used for reporting the working state of the communication sub-chip and the change of the working state to the processor.

The utility model discloses a kind of radio frequency transceiving architecture and navigation equipment, it is related to radio frequency communication technical field, including array antenna module, radio frequency front-end Sip chip, transceiver chip and anti-interference baseband;Array antenna module is used to receive satellite navigation signal;Radio frequency front-end Sip chip integration finite amplifier, low-noise amplifier and acoustic surface filter, for processing satellite navigation signal to obtain pre-processing radio frequency signal;Transceiver chip integration has down-conversion module and up-conversion module;Down-conversion module converts pre-processing radio frequency signal into intermediate frequency signal;Anti-interference baseband is output to up-conversion module after intermediate frequency signal is handled by anti-interference algorithm;Up-conversion module converts intermediate frequency signal into radio frequency navigation signal and is output to navigation receiver.This scheme can solve the technical problems of numerous component models, high equipment cost, not conducive to miniaturization and light weight, high power consumption of existing navigation anti-interference equipment transceiving architecture.

The present invention provides an EMI filter with low clamping voltage type integrated electrostatic protection function, comprising an N-type semiconductor substrate, an NPN transistor Q1, an NPN transistor Q2 and a resistor R, wherein the NPN transistor Q1 is provided with a first P-type well region, the NPN transistor Q2 is provided with a second P-type well region, a grounded P+ heavily doped active region and an N+ heavily doped active region connected to an I / O port 1 are provided in the first P-type well region, the bottom of the N-type semiconductor substrate is grounded, a vertical forward ESD path is formed between the N+ heavily doped active region in the first P-type well region and the bottom of the N-type semiconductor substrate, a horizontal reverse ESD path is formed between the P+ heavily doped active region in the first P-type well region and the N+ heavily doped active region, and the second P-type well region has the same structure as the first P-type well region. The beneficial effects of the present invention are: it can simultaneously realize the dual functions of electrostatic protection and electromagnetic interference filtering.

An electronic package and a manufacturing method thereof are mainly characterized in that an electronic module including a bridge element and an electronic element is partially arranged on a bearing structure and partially protrudes out of the bearing structure, and a photonic element is electrically connected to the protruding part of the electronic module. By means of the configuration, the layout area of the bearing structure can be reduced, and the requirement for miniaturization is met.

The invention provides a multichannel capacitance acquisition system for time-sharing excitation output, which belongs to the technical field of airborne controllers and comprises a main processor, a capacitance excitation generation conditioning circuit, a gear matching circuit, a time-sharing excitation output circuit, an excitation signal acquisition circuit, a feedback signal acquisition circuit and an AD acquisition circuit. The main processor is connected with a capacitor excitation generation, gear matching and time-sharing excitation output circuit, the time-sharing excitation output circuit is connected with one end of a capacitor to be tested, an excitation signal is transmitted to the input end of an excitation signal acquisition circuit, and the other end of the capacitor to be tested is connected with a feedback signal acquisition circuit; the output ends of the excitation signal acquisition circuit and the feedback signal acquisition circuit are connected with the main processor through the AD acquisition circuit; the capacitance excitation generation conditioning circuit generates a sine excitation signal, the gear matching circuit performs gear excitation according to the capacitance value of the capacitor, and the time-sharing excitation output circuit outputs the excitation signal to each acquisition channel capacitor in a time-sharing manner. The capacitance acquisition efficiency and accuracy are improved, and interference between channels is reduced.

The application provides a MOS device testing system and a testing method. In the testing system, a multi-gate testing structure comprises a first injection well and a plurality of main gates above the first injection well, a first source-drain contact hole is formed above the substrate on both sides of each main gate, an auxiliary testing structure comprises a second injection well and a plurality of auxiliary gates above the second injection well, a second source-drain contact hole is formed above the substrate on both sides of each auxiliary gate, the auxiliary gates correspond to the main gates one by one, and the number of the source-drain contact holes formed on both sides of the corresponding auxiliary gate and main gate is different. The testing system can extract the relationship between the parasitic capacitance from the gate to the source-drain contact hole and the number of the source-drain contact hole, and the structure of the testing system is simple, which is beneficial to saving the layout area. The testing method tests the parasitic capacitance from the gate to the source-drain contact hole of the MOS device by using the above testing system.

This utility model belongs to the field of wafer insertion machine technology, specifically relating to a four-head wafer insertion machine layout structure, including: a conveyor production line, a three-axis transport device, a full basket conveyor line, and a return basket production line. Each conveyor production line is used to transport silicon wafers along the y-axis direction. Each conveyor production line has a lifting and loading device at its end, with a basket for loading silicon wafers mounted on it. The full basket conveyor line transports baskets loaded with silicon wafers along the y-axis direction, and the return basket production line transports empty baskets along the y-axis direction. The three-axis transport device moves baskets between the return basket production line, the full basket conveyor line, and the lifting and loading device. This utility model, through a reasonable equipment layout and automated operation process, effectively solves the technical problems of silicon wafer or equipment damage and low production efficiency caused by improper layout in existing technologies, achieving improved production efficiency and reduced breakage rate.

This invention discloses a high-gain transimpedance amplifier based on low-resistance feedback, belonging to the field of transimpedance amplifier technology for photoelectric sensors. It includes: a first resistor voltage divider bias circuit, a second resistor voltage divider bias circuit, a photodiode, a first feedback resistor, a second feedback resistor, and an operational amplifier. The operational amplifier is connected to the first resistor voltage divider bias circuit, the second resistor voltage divider bias circuit is connected to both the first and second feedback resistors, and the operational amplifier is connected to the photodiode. The first feedback resistor is connected to the operational amplifier, and the second feedback resistor is also connected to the operational amplifier. This invention provides the same voltage as the non-inverting input of the operational amplifier through the first feedback resistor. A voltage difference exists between the two input terminals of the operational amplifier, and the current is output through the transconductance effect of the operational amplifier. This enables the high-gain transimpedance amplifier to achieve high gain, reduces the total resistance of the feedback resistors, shrinks the overall layout area of ​​the transimpedance amplifier, and improves the circuit integration.

The present invention provides an EMI low-pass filter with integrated electrostatic and surge protection functions, including a first TVS structure provided with a first P-type well region and a grounded P+ heavily doped active region, a second TVS structure provided with a floating second P-type well region and a grounded P+ heavily doped active region, an N+ heavily doped active region provided in the first P-type well region and the second P-type well region, the bottom of the N-type semiconductor substrate is grounded, a vertical forward ESD path is formed between the N+ heavily doped active region in the first P-type well region and the bottom of the N-type semiconductor substrate, a horizontal reverse ESD path is formed between the P+ heavily doped active region of the first TVS structure and the N+ heavily doped active region in the first P-type well region, and the second TVS structure also forms a forward ESD path and a reverse ESD path. The beneficial effects of the present invention are: it can realize high-frequency signal suppression function, electrostatic and surge protection capabilities.

The present invention provides a gate transfer circuit and a display device. The gate transfer circuit includes multiple stages of gate transfer units. Each stage of the gate transfer unit includes a pre-charge module, a first output module, a second output module, an output pull-down module, a node pull-down module, and a stabilization module. The pre-charge module charges a first node according to a previous-stage transfer signal and a previous-stage gate signal. The first output module outputs a gate signal of the current stage according to the potential of the first node and a first clock signal of the current stage. The second output module outputs a transfer signal of the current stage according to the potential of the first node and a first clock signal of the current stage. The output pull-down module pulls down a first output terminal according to a subsequent-stage gate signal and a first low-level signal. The pull-down module pulls down the first node according to a subsequent-stage gate signal and a second clock signal of the current stage. The stabilization module is used to maintain a low level. The present invention can reduce the falling-edge time of the gate signal and improve the image quality of the product.

This invention discloses a SPAD-based capacitor-switching analog-domain dynamic visual imaging method. During the Nth frame exposure, a SPAD pulse successively decrements the voltage of the first analog counter, triggering capacitor switching and incrementing the digital counter; after exposure, the count value is latched and residual voltage is retained. In the quantization stage, quantization alignment is performed based on the count value and residual voltage, and synchronous flipping and inversion are performed, with a pre-stored inverse analog reference. During the N+1th frame exposure, pulses are simultaneously fed into the first and second analog counters; after exposure, the state of the first counter and the flip flag determine whether inversion is needed, and the second count value is output. In the quantization stage, the second counter is quantized using a high-frequency clock, and a low-frequency clock is injected into the first counter. The dynamic event pulse is obtained by comparing the transition times of the two counter outputs. This invention achieves low-power, high signal-to-noise ratio, high dynamic range, and low-latency analog-domain dynamic visual imaging.

The invention discloses an anti-interference straight-through switching circuit of a satellite transceiver. The anti-interference straight-through switching circuit comprises a first comparator, a second comparator, a B3 straight-through circuit, a B3 anti-interference circuit, an S straight-through circuit and an S anti-interference circuit, an external mode control signal is input into the input end of the first comparator and the input end of the second comparator, and the output end of the first comparator is connected with the input end of the first B3 change-over switch and the input end of the second S change-over switch. The output end of the second comparator is connected with the input ends of the second B3 change-over switch and the first S change-over switch; the first comparator and the second comparator output opposite output signals; the structure of the B3 frequency point signal processing circuit and the S frequency point signal processing circuit on the circuit board is a central symmetry structure. According to the invention, switching of the direct-through circuit and the anti-interference circuit of the B3 frequency point and the S frequency point can be controlled through the two comparator circuits, the number of components required by a control part is greatly reduced, and the size, the weight and the structural complexity of equipment are effectively reduced.