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In electronics, a common-source amplifier is one of three basic single-stage field-effect transistor (FET) amplifier topologies, typically used as a voltage or transconductance amplifier. The easiest way to tell if a FET is common source, common drain, or common gate is to examine where the signal enters and leaves. The remaining terminal is what is known as "common". In this example, the signal enters the gate, and exits the drain. The only terminal remaining is the source. This is a common-source FET circuit. The analogous bipolar junction transistor circuit may be viewed as a transconductance amplifier or as a voltage amplifier. (See classification of amplifiers). As a transconductance amplifier, the input voltage is seen as modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of current flowing through the FET, changing the voltage across the output resistance according to Ohm's law. However, the FET device's output resistance typically is not high enough for a reasonable transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major drawback is the amplifier's limited high-frequency response. Therefore, in practice the output often is routed through either a voltage follower (common-drain or CD stage), or a current follower (common-gate or CG stage), to obtain more favorable output and frequency characteristics. The CS–CG combination is called a cascode amplifier.
Noise elimination circuit structure, low noise amplifier, chip and electronic equipment
PendingCN120377837ADifferential amplifiersAmplifier input/output impedence modificationLow noiseRadar
The invention discloses a noise elimination circuit structure, a low noise amplifier, a chip and electronic equipment. The noise elimination circuit structure comprises an input matching network; a common source stage amplification path connected with the first differential output end of the input matching network, comprising a first common source stage differential amplifier, and outputting an amplified first signal inverted from the radio frequency input signal to the ground; the common-gate amplification path is connected with the second differential output end of the input matching network, comprises a first common-gate differential amplifier and outputs an amplified second signal which is opposite to the radio frequency input signal to the ground; and the output end of the common-source amplification path and the output end of the common-gate amplification path are connected in parallel to form the output end of the noise elimination circuit structure. The common-source amplification path and the common-gate amplification path required by the noise elimination structure are realized by using one amplifier path, the utilization rate of the layout area is improved, the compactness of the layout is realized, and the amplifier can be widely applied to the field of communication or radar.
Owner:SOUTH CHINA UNIV OF TECH
Vertical memory devices
ActiveUS12412855B2Semiconductor/solid-state device detailsSolid-state devicesDevice materialElectrical connection
Aspects of the disclosure provide a semiconductor device and method. An example method include forming a stack of layers on a substrate, the stack of layers including a source sacrificial layer, a conductive layer, gate sacrificial layers and insulating layers; forming a staircase into the stack of layers in a staircase region that is adjacent to an array region; forming channel structures in the array region, a channel structure including a channel layer surrounded by one or more insulating layers and extending into the stack of layers; replacing the source sacrificial layer with a source layer in conductive connection with the channel layer, the source layer and the conductive layer forming a common source layer; replacing the gate sacrificial layers with gate layers; and forming a first contact structure in the staircase region, the first contact structure forming a conductive connection with the common source layer.
Owner:YANGTZE MEMORY TECH CO LTD
Packaging structure of quasi-monolithic power multiplication amplifier
ActiveCN222939926USemiconductor/solid-state device detailsSolid-state devicesHemt circuitsStructural engineering
The utility model discloses a packaging structure of a quasi-monolithic power multiplication amplifier. The packaging structure comprises a frame base island, the lead frame is arranged on the periphery of the frame base island; the four tube core chips are respectively bonded on the front face of the frame base island through bonding materials, two of the tube core chips are connected through a lead to form a common-gate amplification structure, the other two tube core chips are connected through a lead to form a common-source amplification structure, and the four tube core chips are further connected with the lead frame through leads. The four tube core chips jointly form an amplifying circuit of a push-pull structure; and the frame base island, the lead frame, the four tube core chips and the leads are coated with the plastic package material to form a whole through plastic package. The heat dissipation of the power amplifier is facilitated.
Owner:SHENZHEN SANLAND ELECTRONICS
Read-only memory array and read-only memory thereof
The disclosure describes a read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines perpendicular to the common-source lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell has a control terminal coupled to the corresponding word bit line and a data terminal coupled to the corresponding common-source line and the corresponding word bit line. The read-only memory includes a field-effect transistor and a capacitor formed in a semiconductor region. The field-effect transistor and the capacitor commonly include a doped well. The doped well, overlapping the common-source line, is coupled to the common-source line.
Owner:YIELD MICROELECTRONICS CORP
High-linearity medium-power amplifier based on cascode RC negative feedback and composite matching network
PendingCN120582567AAmplifier modifications to reduce non-linear distortionAmplifier modifications to reduce noise influenceCapacitanceCascode
The invention discloses a high-linearity medium-power amplifier based on cascode RC negative feedback and a composite matching network. The high-linearity medium-power amplifier comprises a common-source transistor M1, a common-gate transistor M2, a single power supply VDD with an active bias circuit, an input matching network, an output matching network and a negative feedback loop, the input matching network comprises an inductor Lb and an inductor Lg, the output skin matching network comprises an inductor Ld1 and an inductor Ld2, and the negative feedback loop comprises a resistor Rf and a capacitor Cf; the source electrode of the common source transistor M1 is connected with the drain electrode of the common gate transistor M2, one side of the active bias circuit is connected to the grid electrode of the common source transistor M1 through the inductor Lb and the inductor Lg in sequence, the common end of the inductor Lb and the inductor Lg is connected with the input end, and the resistor Rf and the capacitor Cf are connected in series and connected between the grid electrode of the common source transistor M1 and the output end. One side of the inductor Ld2 is connected with the source electrode of the common-gate transistor M2, the other side of the inductor Ld2 is connected with one side of the inductor Ld1, the other side of the inductor Ld1 is connected with the single power supply VDD, and the common end of the inductor Ld1 and the inductor Ld2 is connected with the capacitor Cf and the output end; the method is suitable for radar and communication systems in industrial application, and has important significance for developing high-performance, low-cost and high-integration-level multifunctional chips.
Owner:杨哲辉
Radio frequency amplifier bandwidth expansion circuit based on resistor-capacitor series feedback
The invention belongs to the technical field of integrated circuits, and particularly relates to a radio frequency amplifier bandwidth expansion circuit based on resistor-capacitor series feedback. The bandwidth expansion circuit comprises a first-stage common-gate amplifier, a second-stage common-source amplifier, a transformer-based inter-stage matching network between the two stages of amplifiers, and two resistor-capacitor series feedback paths, and a resistor-capacitor series feedback path is bridged at two sides of the interstage matching network, and feedback is introduced from the output end of the common source amplifier to the output end of the common gate amplifier, so that the quality factors of two resonant cavities of the interstage matching transformer are adjusted, and the targets of adjusting the gain of the amplifier and expanding the bandwidth of the radio frequency amplifier are further realized.
Owner:FUDAN UNIVERSITY
Radio frequency power amplifier
ActiveUS12483208B2Amplifier modifications to raise efficiencyAmplifier modifications to reduce detrimental impedenceAudio power amplifierCascode
According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.
Owner:STMICROELECTRONICS FRANCE
FET device and a method for forming a FET device
According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device.
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
CMOS image sensors and manufacturing methods thereof
Various embodiments of the present disclosure are directed towards an integrated circuit on a semiconductor substrate. First and second gate electrode structures are disposed over the substrate and are spaced laterally from one another. A common source / drain region is disposed in the semiconductor substrate between the first and second gate electrode structures. An insulator layer overlies the first and second gate electrode structures. A source / drain contact extends through the insulator layer between the first and second gate electrode structures to contact the common source / drain region. First and second sidewall spacer structures are disposed along outer sidewalls of the first and second gate electrode structures, respectively, and have first and second outer sidewalls, respectively, adjacent to the source / drain contact. The first outer sidewall includes at least two indentations facing a first side of the source / drain contact, and the second outer sidewall includes at least two indentations facing a second side of the source / drain contact.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Semiconductor memory device and electronic system including the same
A semiconductor memory device and an electronic system including the same are provided. The semiconductor memory device includes a first cell array structure including a plurality of first cell strings, a plurality of first bonding pads, a first bit line, a first common source line, and a plurality of first word lines; and a second cell array structure including a plurality of second cell strings, a plurality of second bonding pads, a second bit line, a second common source line, and a plurality of second word lines, in which the plurality of first bonding pads are bonded to the plurality of second bonding pads, in which the plurality of first word lines are electrically connected to the plurality of second word lines, in which the plurality of first word lines are electrically connected to the plurality of second word lines. The first bit line is spaced apart from the second bit line, and wherein the first common source line is electrically separated from the second common source line.
Owner:SAMSUNG ELECTRONICS CO LTD
A voltage-stabilized starting circuit without operational amplifier for high voltage and a voltage-stabilized starting method thereof
The present invention discloses a high-voltage op-amp-free voltage-stabilizing startup circuit and a voltage-stabilizing startup method thereof. The circuit includes a voltage-stabilizing circuit and a startup circuit. The startup circuit generates a bias current Ibias2. In the voltage-stabilizing circuit, a transistor Q7 and a PMOS transistor PDM2 form a first common-emitter amplifier, an NMOS transistor NDM2 and a PMOS transistor PDM3 form a first common-source amplifier, and a PMOS transistor PDM4, a transistor Q6, a resistor R4, and a transistor Q5 form a second common-source amplifier. The present invention does not require the additional design of a pre-voltage-stabilizing circuit and a high-voltage operational amplifier, thereby saving chip area. Furthermore, after the voltage-stabilizing startup circuit is started, the startup circuit does not need to be shut down.
Owner:上海帝迪集成电路设计有限公司
Comparator circuit with dynamic hysteresis
ActiveUS12316330B2Multiple input and output pulse circuitsElectric pulse generatorSoftware engineeringHemt circuits
A comparator circuit with dynamic hysteresis. A common source branch is configured to conduct a differential current at first and second intermediate outputs responsive to a differential input at first and second inputs, and a common gate branch is configured to generate a voltage at a third intermediate output responsive to the differential current at the first and second intermediate outputs. A hysteresis branch includes a hysteresis current generator including first and second replica transistors having source / drain paths coupled in parallel, and gates coupled to the first and second inputs, respectively. A hysteresis capacitor is coupled between the sources of the first and second replica transistors and the common terminal. Current mirror circuitry is coupled to the source / drain paths of the first and second replica transistors, to supply a hysteresis current responsive to the absence of current conducted by the parallel first and second replica transistors.
Owner:TEXAS INSTRUMENTS INC
Non-volatile memory with stacked transistor pairs
A bit cell (100) is disclosed that includes a non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal that switches a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source / drain terminal (121) of the transistor arrangement, and a second common source / drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor device includes a pair of stacked complementary transistors, where a gate (213) of an upper transistor is connected to a first word line (WLN), and where a gate (233) of a lower transistor is connected to a second word line (WLP). A memory device including an array of such bit cells, and a method for controlling bit cells are also disclosed.
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
Low-noise amplifier circuit capable of improving stability and bypass linearity
ActiveCN120934463AAmplifier modifications to reduce non-linear distortionAmplifier modifications to reduce noise influenceLow noiseNoise (radio)
The invention discloses a low-noise amplifier circuit capable of improving stability and bypass linearity, and relates to the technical field of radio frequency integrated circuits. The circuit comprises an input matching module, a low noise amplification module, an output matching module, a bypass module, a common source electrode switch module and a negative feedback virtual ground module. A leakage path is cut off according to cooperative control of an enable signal and an MOS switch tube through the common source electrode switch module so as to improve the linearity of a bypass mode, and a negative feedback loop network is generated by the negative feedback virtual ground module and the output matching module, so that a high-frequency signal is fed back from the negative feedback loop network, and the linearity of the bypass mode is improved. The problem of stability under high gain is solved.
Owner:CHENGDU GANIDE TECH
Semiconductor memory and method of making the same, electronic device
The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.
Owner:YANGTZE MEMORY TECH CO LTD
Bidirectional switch semiconductor packaging device, AC / DC converter and automobile
The utility model discloses a bidirectional switch semiconductor packaging device, an AC / DC converter and an automobile, and relates to the technical field of power supplies, the device comprises a first switch chip, a second switch chip, a plastic package shell and a heat dissipation substrate; the drain electrode or the source electrode of the first switch chip is electrically connected with the drain electrode or the source electrode corresponding to the second switch chip through the same heat dissipation substrate, so that a bidirectional switch structure with the common drain electrode or the common source electrode is formed, and heat dissipation can be carried out on the two switch chips at the same time by utilizing a single heat dissipation substrate. Meanwhile, on the surface of the plastic package shell, a creepage path extension part used for increasing the creepage distance is arranged between the heat dissipation substrate and any group of pins located on the two sides of the plastic package shell. Through the structure, the packaging size of the bidirectional switch semiconductor packaging device can be kept as small as possible, and meanwhile, the problems of power output control, heat dissipation, electrical safety and the like caused by the too small packaging size can be prevented.
Owner:SUZHOU INOSA UNITED POWER SYST CO LTD
Asymmetric common source inductances to reduce turn-off overvoltage in mosfets
A circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) (110) having a gate, a source, and a drain. The circuit further includes a first inductor (140A) and a second inductor (140B). The first inductor has a small inductance value that is less than a larger inductance value of the second inductor. The circuit further includes a switch (130) configured to include the first inductor in a current path shared by a gate loop and a source loop of the MOSFET when the MOSFET is turning on, and to include the second inductor in the current path shared by the gate loop and the source loop when the MOSFET is turning off.
Owner:SEMICON COMPONENTS IND LLC
Electronics unit for an electric device
The invention relates to an electronics unit (10) for controlling a load current (I) of an electric load (12), in particular of an electric motor (14), of an electric device by means of at least one power transistor (18) which has at least one control electrode (34) and two power electrodes (36, 38), wherein a control circuit (48) of the power transistor (18) comprises a driver circuit (26) controlling the control electrode (34) and a power circuit (52) of the power transistor (18) comprises the two power electrodes (36, 38) and the electric load (12), and wherein a parasitic inductance of the control circuit (48) and at least one parasitic inductance of the power circuit (52) form a common source inductance (LCSH, LCSH1, LCSH2). According to the invention, the switching behaviour of the at least one power transistor (18) can be influenced during a switching phase (T2, T7), in particular a switch-off phase T7), in which the load current (I) changes over time, by means of at least one controlled current source (54) which is connected to one of the power electrodes (38), in such a way that a negative voltage feedback to the control electrode (34) takes place as a result of the change over time of the load current (dI / dt) via the common source inductance (LCSH, LCSH1, LCSH2). In addition, the invention relates to an electric device, in particular a motor-operated electric device, comprising an electronics unit (10) according to the invention for controlling an electric load (12), in particular a one-phase or multiphase electric motor (14).
Owner:ROBERT BOSCH GMBH
A variable gain amplifier with high temperature stability
PendingCN122119534AAmplifier modifications to reduce temperature/voltage variationAmplifier combinationsVariable-gain amplifierHemt circuits
The embodiment of the present disclosure provides a variable gain amplifier with high temperature stability, which is applied to the technical field of electronic circuit. The amplifier comprises a constant transconductance bias circuit, a first variable gain amplifier and a second variable gain amplifier; wherein the output end of the constant transconductance bias circuit is connected with the input common source transistor of the first variable gain amplifier and the second variable gain amplifier, and is used for providing a constant transconductance bias signal which is compensated according to temperature change; the input end of the first variable gain amplifier is used for receiving an externally input differential signal, and the output end is connected with the input end of the second variable gain amplifier, and is used for transmitting the differential signal after coarse adjustment attenuation to the second variable gain amplifier; and the output end of the second variable gain amplifier is used for outputting an attenuation differential signal with temperature stability. In this way, by restraining the influence of temperature change on the transconductance characteristic of the input common source transistor of the variable gain amplifier, the stable attenuation characteristic of the variable gain amplifier in a wide temperature range is ensured.
Owner:TUOWEI ELECTRONIC TECH (SHANGHAI) CO LTD
Vertical storage device and method of operating the same
The present disclosure provides a vertical memory device and an operation method thereof. An operation method of a memory device is provided, the memory device including a plurality of strings on a substrate, where the plurality of strings include a main string connected to a bit line and a dummy string spaced apart from the bit line, the operation method including: pre-programming the dummy string; and erasing the main string and the dummy string, where pre-programming includes: applying a pre-programming voltage to a word line connected to the dummy string; applying a pass voltage to a ground selection line of a ground selection transistor connected to the dummy string; and applying a common source line voltage to a common source line connected to the dummy string.
Owner:SAMSUNG ELECTRONICS CO LTD
Bidirectional power device module integrating a drive circuit and an active substrate clamp circuit
The application relates to a bidirectional power device module integrated with a driving circuit and an active substrate clamping circuit, which comprises a common-drain bidirectional power device, a driving circuit used for providing a driving signal to the common-drain bidirectional power device to turn on and turn off the device, and a substrate clamping circuit comprising a first switch tube and a second switch tube, wherein the first switch tube and the second switch tube are commonly connected to the substrate of the common-drain bidirectional power device, the drain of the first switch tube is connected to the first source of the common-drain bidirectional power device, and the gate is connected to the output end of a third driving unit; the drain of the second switch tube is connected to the second source of the common-drain bidirectional power device, and the gate is connected to the output end of a fourth driving unit; the input end of the third driving unit inputs a first PWM input signal which is subjected to logic processing; and the input end of the fourth driving unit inputs a second PWM input signal which is subjected to logic processing. The application can improve the substrate clamping speed and reduce the substrate potential.
Owner:SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
Power selection control
PendingCN121079865ABatteries circuit arrangementsDc source parallel operationControl engineeringControl theory
A system and method for power selection control. A plurality of power sources of a power supply unit are each connected to a high-power load via a plurality of switching circuits, each of the plurality of switching circuits including at least one pair of transistors connected in a common source configuration and located between a positive lead of a respective one of the power sources and the high-power load. The controller detects the presence of a current flow from at least one of the power sources, selects one of the power sources accordingly, and activates a respective switching circuit of the plurality of switching circuits to conduct the current flow from the selected respective power source to the high power load.
Owner:QUALITY & FLOW
Integrated circuit for prevention of circuit design theft
ActiveUS12406946B2Semiconductor/solid-state device detailsSolid-state devicesComputer networkField effect
Various embodiments describe an integrated circuit. The integrated circuit includes at least seven planar field effect transistors provided in a common substrate next to one another with a maximum feature size in accordance with a technology node of a maximum of 65 nm. Each field effect transistor of the at least seven planar field effect transistors includes a first source / drain diffusion region, a second source / drain diffusion region, a channel region between the drain diffusion region and the source diffusion region, and a gate terminal. Each field effect transistor of the at least seven planar field effect transistors includes at least one common source / drain diffusion region with another field effect transistor of the at least seven planar field effect transistors. The common source / drain diffusion regions are free of vertical terminal contact material.
Owner:INFINEON TECHNOLOGIES AG
High-Voltage DC Circuit Topology
ActiveCN114977816BAc-dc conversion without reversalDc-dc conversionCapacitanceRadio frequency energy
The present invention discloses a high-voltage DC circuit topology. In the high-voltage DC circuit topology, the positive pole of the DC power supply DC is connected to the positive terminal of the bus capacitor C0 via the diode D1, and the negative pole is connected to the negative terminal of the bus capacitor C0; the positive terminal of the bus capacitor C0 is connected to the common drain of the fault current limiting unit and the full-bridge circuit, and the negative terminal is connected to the common source of the full-bridge circuit to form a radio frequency oscillator. The primary winding of the radio frequency transformer T1 is connected in parallel with the tuning capacitor C2. The radio frequency feed electrode a is connected to the a end of the first secondary winding of the radio frequency transformer, and the radio frequency feed electrode b is connected to the b end of the second secondary winding of the radio frequency transformer. A voltage multiplier is placed between the radio frequency feed electrode a and the radio frequency feed electrode b to achieve voltage superposition. The voltage multiplier is composed of a cascade of multiple radio frequency energy coupling electrodes and radio frequency rectifiers. One end of the parallel resonance filter is connected to the last-stage radio frequency energy coupling electrode of the voltage multiplier, and the other end is connected to the load to achieve a DC voltage with low ripple on the load.
Owner:XI AN JIAOTONG UNIV
Semiconductor device and method for forming the same, electronic device
The application discloses a semiconductor device and a forming method thereof and an electronic device, wherein the semiconductor device comprises a substrate, a source layer is formed in the substrate, a plurality of discrete gate structures are formed in the substrate, the bottom of the gate structure is located on the surface of the source layer, a plurality of drains are formed in the substrate on both sides of the top of the gate structure, and each drain is located between two adjacent gates. The application can realize the common source scheme of the corresponding semiconductor device, reduce the size of the semiconductor device, and improve the area utilization of the chip.
Owner:SHANGHAI AIWEI SEMICON TECH CO LTD
Integrated circuit device and electronic system including the same
A cell array structure of an integrated circuit device includes a gate stack including gate electrodes and mold insulation layers, which extend in a horizontal direction and are alternately stacked in a vertical direction, a channel structure extending in the vertical direction in the gate stack including a channel layer and a gate insulation layer conformally covering the channel layer, the gate stack and gate insulation layer exposing a portion of an upper surface of the channel layer, an insulation pattern layer disposed on the gate stack, and the gate insulation layer and exposing the portion of the upper surface of the channel layer, and a common source line structure contacting the gate insulation layer, the insulation pattern layer, and the upper surface of the channel layer, wherein a sidewall of the common source line structure disposed in the gate stack has a staircase shape.
Owner:SAMSUNG ELECTRONICS CO LTD
Excitation type dual-power contact pressing device
ActiveCN223347645UContact driving mechanismsPower network operation systems integrationLoad busTransfer switch
The utility model discloses an excitation type dual power supply contact pressing device, which relates to the technical field of dual power supply change-over switches, and comprises a load bus and a power supply module, the upper end of the power supply module is provided with a common source bus, the rear end of the common source bus is provided with a standby power supply bus, and the standby power supply bus is connected with the load bus. A controller is arranged on one side of the power module, a debugging handle is arranged on one side of the controller, a mounting groove is formed in the other side of the controller, a wiring terminal is arranged in the mounting groove, a protection assembly is arranged outside the debugging handle, and the protection assembly comprises a protection sleeve. By means of the scheme, the problems that a debugging handle of an existing dual-power-supply change-over switch lacks protection, is prone to being damaged due to stress during use, installation and maintenance, and is prone to misoperation due to stress, and the protection performance is poor are solved.
Owner:JIANGSU YONG XUN ELECTRICAL CO LTD
Semiconductor device, memory and method of manufacturing the same, electronic device
The present disclosure relates to a semiconductor device, a memory and a preparation method thereof, and an electronic device, and relates to the technical field of storage, so as to improve the performance and reliability of the semiconductor device and the memory. The semiconductor device comprises a first gate, a second gate, a third gate, a first semiconductor layer, a second semiconductor layer and a common source line. The first semiconductor layer is insulatively surrounded around the side wall of the first gate. The second gate is located on the side of the first semiconductor layer away from the first gate, and comprises a first part electrically connected with the first semiconductor layer, and a second part located on the side of the first part away from the first semiconductor layer and electrically connected with the first part. The second semiconductor layer is insulatively surrounded around the side wall of the second part and the bottom wall of the second part away from the first part. The third gate and the common source line are insulatively spaced around the side of the second semiconductor layer away from the side wall of the second part.
Owner:BEIJING SUPERSTRING ACAD OF MEMORY TECH
A differential pair circuit with improved linearity
ActiveCN115276571BAmplifier modifications to reduce non-linear distortionDifferential amplifiersTerminal voltageHemt circuits
The present invention provides a differential pair circuit with improved linearity, comprising a differential pair and a bias tube, wherein the differential pair comprises: a first input pair tube, controllably connected between a first node and a common source terminal under the action of a first input voltage; a second input pair tube, controllably connected between a second node and a common source terminal under the action of a second input voltage; a source of the bias tube connected to the common source terminal, and the type of the bias tube is opposite to that of the differential pair tube, and controllably connected to the common source terminal under the action of the bias voltage. Beneficial effect: The bias tube provides a bias current that can change with the differential input voltage to the two input pairs of the differential pair tubes. Compared with the traditional differential pair circuit, the change in the common source terminal voltage Vs in the unbalanced state is smaller, and the sum of the drain terminal currents flowing through the two input pairs of tubes is increased, thereby improving the output current Io (i.e., I D1 ‑I D2 ) and the input voltage Vi (ie V in1 ‑V in2 ) between the linearity.
Owner:2PAI SEMICON (SHANGHAI) CO LTD
Embedded flash memory below 110nm and its preparation method
An embedded flash memory device with a size of less than 110nm and a method for fabricating the same include: a substrate, a memory array region, and a peripheral logic region on the substrate. The memory array region includes at least one memory cell, each memory cell comprising: a common source located in the substrate, a common line located above and connected to the common source; a pair of stacked gates located on either side of the common line, each stacked gate comprising a floating gate and a control gate vertically stacked above it; and a pair of select gates located adjacent to the non-common line sides of the stacked gates. The peripheral logic region includes at least one logic transistor, each logic transistor comprising a logic gate. The control gate in the memory cell is at the same height as the logic gate of the logic transistor. This embedded flash memory device has excellent and stable performance and reliability, and its fabrication method is simple, convenient, and low-cost.
Owner:CHENGDU RUICHENGXIN MICRO TECHNOLOGY CO LTD