Patents
Literature
414 results about "Common source" patented technology
Efficacy Topic
Property
Owner
Technical Advancement
Application Domain
Technology Topic
Technology Field Word
Patent Country/Region
Patent Type
Patent Status
Application Year
Inventor
In electronics, a common-source amplifier is one of three basic single-stage field-effect transistor (FET) amplifier topologies, typically used as a voltage or transconductance amplifier. The easiest way to tell if a FET is common source, common drain, or common gate is to examine where the signal enters and leaves. The remaining terminal is what is known as "common". In this example, the signal enters the gate, and exits the drain. The only terminal remaining is the source. This is a common-source FET circuit. The analogous bipolar junction transistor circuit may be viewed as a transconductance amplifier or as a voltage amplifier. (See classification of amplifiers). As a transconductance amplifier, the input voltage is seen as modulating the current going to the load. As a voltage amplifier, input voltage modulates the amount of current flowing through the FET, changing the voltage across the output resistance according to Ohm's law. However, the FET device's output resistance typically is not high enough for a reasonable transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major drawback is the amplifier's limited high-frequency response. Therefore, in practice the output often is routed through either a voltage follower (common-drain or CD stage), or a current follower (common-gate or CG stage), to obtain more favorable output and frequency characteristics. The CS–CG combination is called a cascode amplifier.
Noise elimination circuit structure, low noise amplifier, chip and electronic equipment
PendingCN120377837ADifferential amplifiersAmplifier input/output impedence modificationLow noiseRadar
The invention discloses a noise elimination circuit structure, a low noise amplifier, a chip and electronic equipment. The noise elimination circuit structure comprises an input matching network; a common source stage amplification path connected with the first differential output end of the input matching network, comprising a first common source stage differential amplifier, and outputting an amplified first signal inverted from the radio frequency input signal to the ground; the common-gate amplification path is connected with the second differential output end of the input matching network, comprises a first common-gate differential amplifier and outputs an amplified second signal which is opposite to the radio frequency input signal to the ground; and the output end of the common-source amplification path and the output end of the common-gate amplification path are connected in parallel to form the output end of the noise elimination circuit structure. The common-source amplification path and the common-gate amplification path required by the noise elimination structure are realized by using one amplifier path, the utilization rate of the layout area is improved, the compactness of the layout is realized, and the amplifier can be widely applied to the field of communication or radar.
Owner:SOUTH CHINA UNIV OF TECH
Image sensors having data converters with low noise comparators
ActiveUS12207009B2Electric signal transmission systemsAnalogue/digital conversionLow noiseHemt circuits
An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.
Owner:SEMICON COMPONENTS IND LLC
Vertical memory devices
ActiveUS12412855B2Semiconductor/solid-state device detailsSolid-state devicesDevice materialElectrical connection
Aspects of the disclosure provide a semiconductor device and method. An example method include forming a stack of layers on a substrate, the stack of layers including a source sacrificial layer, a conductive layer, gate sacrificial layers and insulating layers; forming a staircase into the stack of layers in a staircase region that is adjacent to an array region; forming channel structures in the array region, a channel structure including a channel layer surrounded by one or more insulating layers and extending into the stack of layers; replacing the source sacrificial layer with a source layer in conductive connection with the channel layer, the source layer and the conductive layer forming a common source layer; replacing the gate sacrificial layers with gate layers; and forming a first contact structure in the staircase region, the first contact structure forming a conductive connection with the common source layer.
Owner:YANGTZE MEMORY TECH CO LTD
Dynamic current-sharing layout design method and system for multi-chip parallel power module
The invention belongs to the field of power semiconductor devices, and discloses a dynamic current-sharing layout design method and system for a multi-chip parallel power module, and the method comprises two aspects of main power loop layout and wiring and driving loop layout and wiring. A main power loop is designed in a vertical commutation manner, and parallel chip source electrodes and drain electrodes are designed in an integrated manner, so that quasi-common-source-electrode inductors of the chips are consistent and integrated, and parallel dynamic current sharing of multiple gallium nitride chips is facilitated; wiring of the driving loop is in vertical commutation and is vertical to the main power loop, mutual inductance of the power loop to the driving loop is basically zero, and parallel dynamic current sharing of gallium nitride chips is facilitated; when the design is met and grid leading-out ends and Kelvin source leading-out ends of the four chips are symmetrical about the symmetry axis of the main power loop, the mutual inductance of the main power loop to a part of wiring from a drive to each chip grid is equal, and the mutual inductance of the main power loop to a wiring from a Kelvin source to a drive ground of each chip is also equal. And an excellent gallium nitride multi-chip parallel dynamic current sharing effect can be realized.
Owner:HUAZHONG UNIV OF SCI & TECH
Power cover structure for multi-chip semiconductor package
PendingCN119495676ASemiconductor/solid-state device detailsSolid-state devicesDevice materialSemiconductor package
The invention relates to a power cover structure for a multi-chip semiconductor package. A multi-chip semiconductor package, the multi-chip semiconductor package comprising: a dielectric interconnect layer having an upper surface and a bottom surface; at least one common source pad disposed on an upper surface of the interconnect layer; at least one common gate pad disposed on an upper surface of the interconnect layer; and a plurality of semiconductor devices each including a gate pad and at least one source pad bonded to the interconnect layer, where the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and where the source pads of the plurality of semiconductor devices are electrically connected in parallel with each other, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel with each other.
Owner:GENERAL ELECTRIC CO
Packaging structure of quasi-monolithic power multiplication amplifier
ActiveCN222939926USemiconductor/solid-state device detailsSolid-state devicesHemt circuitsStructural engineering
The utility model discloses a packaging structure of a quasi-monolithic power multiplication amplifier. The packaging structure comprises a frame base island, the lead frame is arranged on the periphery of the frame base island; the four tube core chips are respectively bonded on the front face of the frame base island through bonding materials, two of the tube core chips are connected through a lead to form a common-gate amplification structure, the other two tube core chips are connected through a lead to form a common-source amplification structure, and the four tube core chips are further connected with the lead frame through leads. The four tube core chips jointly form an amplifying circuit of a push-pull structure; and the frame base island, the lead frame, the four tube core chips and the leads are coated with the plastic package material to form a whole through plastic package. The heat dissipation of the power amplifier is facilitated.
Owner:SHENZHEN SANLAND ELECTRONICS
Read-only memory array and read-only memory thereof
The disclosure describes a read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines perpendicular to the common-source lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell has a control terminal coupled to the corresponding word bit line and a data terminal coupled to the corresponding common-source line and the corresponding word bit line. The read-only memory includes a field-effect transistor and a capacitor formed in a semiconductor region. The field-effect transistor and the capacitor commonly include a doped well. The doped well, overlapping the common-source line, is coupled to the common-source line.
Owner:YIELD MICROELECTRONICS CORP
Multi-input BUCK circuit, charging circuit, chip and electronic equipment
PendingCN119813777AEfficient power electronics conversionDc-dc conversionHemt circuitsControl theory
The invention provides a multi-input BUCK circuit, a charging circuit, a chip and electronic equipment. The circuit comprises a plurality of power supply circuits, a conversion circuit and a driving circuit, the driving circuit comprises an upper switch tube driving circuit and a plurality of isolation tube driving circuits, the power supply circuit comprises isolation tubes used for isolating power supply voltages accessed to the power supply circuits, the conversion circuit and the isolation tubes form a BUCK circuit, and the isolation tubes are back-to-back NMOS isolation tubes with common sources. A common-source back-to-back NMOS (N-channel metal oxide semiconductor) tube is used as an isolation tube in each power supply circuit, and one power supply circuit can be selected to supply power to the BUCK circuit on the basis of the control of an upper switch tube driving circuit and a plurality of isolation tube driving circuits on the power supply circuits, namely one input source is selected from a plurality of input sources to supply power to the BUCK circuit. Flexible electricity taking logic is realized; the isolation tube is multiplexed as the upper switch tube of the BUCK circuit, the number of NMOS (N-channel Metal Oxide Semiconductor) tubes is reduced, the conduction impedance of the NMOS tubes is smaller than that of PMOS (P-channel Metal Oxide Semiconductor) tubes, and the efficiency of the system is improved.
Owner:ZHUHAI NANXIN SEMICON TECH CO LTD
High-linearity medium-power amplifier based on cascode RC negative feedback and composite matching network
PendingCN120582567AAmplifier modifications to reduce non-linear distortionAmplifier modifications to reduce noise influenceCapacitanceCascode
The invention discloses a high-linearity medium-power amplifier based on cascode RC negative feedback and a composite matching network. The high-linearity medium-power amplifier comprises a common-source transistor M1, a common-gate transistor M2, a single power supply VDD with an active bias circuit, an input matching network, an output matching network and a negative feedback loop, the input matching network comprises an inductor Lb and an inductor Lg, the output skin matching network comprises an inductor Ld1 and an inductor Ld2, and the negative feedback loop comprises a resistor Rf and a capacitor Cf; the source electrode of the common source transistor M1 is connected with the drain electrode of the common gate transistor M2, one side of the active bias circuit is connected to the grid electrode of the common source transistor M1 through the inductor Lb and the inductor Lg in sequence, the common end of the inductor Lb and the inductor Lg is connected with the input end, and the resistor Rf and the capacitor Cf are connected in series and connected between the grid electrode of the common source transistor M1 and the output end. One side of the inductor Ld2 is connected with the source electrode of the common-gate transistor M2, the other side of the inductor Ld2 is connected with one side of the inductor Ld1, the other side of the inductor Ld1 is connected with the single power supply VDD, and the common end of the inductor Ld1 and the inductor Ld2 is connected with the capacitor Cf and the output end; the method is suitable for radar and communication systems in industrial application, and has important significance for developing high-performance, low-cost and high-integration-level multifunctional chips.
Owner:杨哲辉
Radio frequency amplifier bandwidth expansion circuit based on resistor-capacitor series feedback
The invention belongs to the technical field of integrated circuits, and particularly relates to a radio frequency amplifier bandwidth expansion circuit based on resistor-capacitor series feedback. The bandwidth expansion circuit comprises a first-stage common-gate amplifier, a second-stage common-source amplifier, a transformer-based inter-stage matching network between the two stages of amplifiers, and two resistor-capacitor series feedback paths, and a resistor-capacitor series feedback path is bridged at two sides of the interstage matching network, and feedback is introduced from the output end of the common source amplifier to the output end of the common gate amplifier, so that the quality factors of two resonant cavities of the interstage matching transformer are adjusted, and the targets of adjusting the gain of the amplifier and expanding the bandwidth of the radio frequency amplifier are further realized.
Owner:FUDAN UNIVERSITY
Radio frequency power amplifier
ActiveUS12483208B2Amplifier modifications to raise efficiencyAmplifier modifications to reduce detrimental impedenceAudio power amplifierCascode
According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.
Owner:STMICROELECTRONICS FRANCE
Drain sharing split LNA
A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
Owner:PSEMI CORP
Forward and reverse rotation module of three-phase motor
ActiveCN222638422Uquick responseQuickly respond to outputElectronic switchingAC motor direction controlMOSFETHemt circuits
The utility model discloses a forward and reverse rotation module of a three-phase motor, which comprises a forward rotation circuit and a reverse rotation circuit, and each of the forward rotation circuit and the reverse rotation circuit comprises a time delay circuit, an interlocking circuit, an optocoupler driving circuit and a switching circuit. The input end of the time delay circuit is connected with the output end of a three-phase power supply, the interlocking circuit is connected to the time delay circuit in parallel, the output end of the time delay circuit is connected with the input end of the optical coupler driving circuit, the optical coupler driving circuit comprises a light emitting diode and two common-source-electrode metal-oxide-semiconductor field effect transistor (MOSFET) tubes which are connected in series reversely, and the two common-source-electrode metal-oxide-semiconductor field effect transistor (MOSFET) tubes are connected in parallel. The output end of the optocoupler driving circuit is connected with the input end of the switching circuit to control the on-off of the switching circuit, and the output end of the switching circuit is connected with the input end of the three-phase motor to form a forward rotation path or a reverse rotation path. The switch circuit has good anti-electromagnetic interference performance and anti-vibration and anti-impact capability, and when the switch circuit is in an over-high electromagnetic interference state or an over-high vibration and anti-impact state, the switch circuit is not mistakenly conducted.
Owner:XIAMEN KUDOM ELECTRONICS TECH CO LTD
FET device and a method for forming a FET device
According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device.
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
Low-noise transconductance amplifier, chip, receiver and electronic equipment
PendingCN119363049AAmplifier modifications to reduce non-linear distortionAmplifier modifications to reduce noise influenceLow noiseCascode
The invention relates to a low-noise transconductance amplifier, a chip, a receiver and electronic equipment, the low-noise transconductance amplifier comprises a first-stage amplification circuit and a second-stage amplification circuit, the first-stage amplification circuit comprises a first-stage input end, a cascode amplification module, a common-source module, a feedback resistor and a first-stage output end, and the second-stage amplification circuit comprises a second-stage input end and a second-stage output end; the cascode amplification module is used for carrying out input matching and amplification processing on an input signal and outputting an obtained first-stage output signal through a first-stage output end; the common source module is used for carrying out noise elimination on an input signal; the second-stage amplification circuit comprises a second-stage input end, a transconductance amplification module and a second-stage output end which are connected in sequence, and the transconductance amplification module is used for conducting transconductance amplification and linearity adjustment on the first-stage output signal and outputting the obtained second-stage output signal through the second-stage output end. According to the low-noise transconductance amplifier, the performance of high gain, high linearity and large bandwidth of the low-noise transconductance amplifier is achieved.
Owner:GUANGZHOU ANYKA MICROELECTRONICS CO LTD +1
Semiconductor device with memory string
A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure, the cell structure including gate electrodes spaced apart from each other in a vertical direction, a channel structure arranged within a channel hole extending in the vertical direction by passing through the gate electrodes, including a channel layer and a back gate electrode spaced apart from the channel layer, and including a first end portion arranged adjacent to the peripheral circuit structure and a second end portion opposite to the first end portion, a common source layer connected to the channel layer at the second end portion of the channel structure, an upper insulating layer on the common source layer, and a back gate contact arranged within a first backside contact hole passing through the upper insulating layer and the common source layer and connected to the back gate electrode.
Owner:SAMSUNG ELECTRONICS CO LTD
CMOS image sensors and manufacturing methods thereof
Various embodiments of the present disclosure are directed towards an integrated circuit on a semiconductor substrate. First and second gate electrode structures are disposed over the substrate and are spaced laterally from one another. A common source / drain region is disposed in the semiconductor substrate between the first and second gate electrode structures. An insulator layer overlies the first and second gate electrode structures. A source / drain contact extends through the insulator layer between the first and second gate electrode structures to contact the common source / drain region. First and second sidewall spacer structures are disposed along outer sidewalls of the first and second gate electrode structures, respectively, and have first and second outer sidewalls, respectively, adjacent to the source / drain contact. The first outer sidewall includes at least two indentations facing a first side of the source / drain contact, and the second outer sidewall includes at least two indentations facing a second side of the source / drain contact.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Improved cascode low-noise amplifier based on in-phase amplification
PendingCN119363047AAmplifier modifications to reduce noise influenceAmplifier modifications to raise efficiencyCapacitanceLow noise
The invention discloses an improved cascode low-noise amplifier based on in-phase amplification, which comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first transformer, a first inductor, a second inductor, a third inductor, a first resistor, a second resistor, a first transistor, a second transistor and a third transistor, wherein the first capacitor and the first transformer form an input matching network based on the transformer; the first transistor and the third transistor form a cascode low-noise amplifier; the first inductor is used as a source negative feedback inductor of the cascode low-noise amplifier; the first transistor, the second transistor and the third transistor form a current mirror structure; and the second inductor, the fourth capacitor, the third inductor and the fifth capacitor form an output matching network. According to the invention, the gain, the noise flatness, the application bandwidth and the input matching degree can be improved, and meanwhile, the chip area is reduced. The invention can be widely applied to the field of radio frequency integrated circuits.
Owner:GUANGDONG UNIV OF TECH
Semiconductor memory device and electronic system including the same
A semiconductor memory device and an electronic system including the same are provided. The semiconductor memory device includes a first cell array structure including a plurality of first cell strings, a plurality of first bonding pads, a first bit line, a first common source line, and a plurality of first word lines; and a second cell array structure including a plurality of second cell strings, a plurality of second bonding pads, a second bit line, a second common source line, and a plurality of second word lines, in which the plurality of first bonding pads are bonded to the plurality of second bonding pads, in which the plurality of first word lines are electrically connected to the plurality of second word lines, in which the plurality of first word lines are electrically connected to the plurality of second word lines. The first bit line is spaced apart from the second bit line, and wherein the first common source line is electrically separated from the second common source line.
Owner:SAMSUNG ELECTRONICS CO LTD
A voltage-stabilized starting circuit without operational amplifier for high voltage and a voltage-stabilized starting method thereof
The present invention discloses a high-voltage op-amp-free voltage-stabilizing startup circuit and a voltage-stabilizing startup method thereof. The circuit includes a voltage-stabilizing circuit and a startup circuit. The startup circuit generates a bias current Ibias2. In the voltage-stabilizing circuit, a transistor Q7 and a PMOS transistor PDM2 form a first common-emitter amplifier, an NMOS transistor NDM2 and a PMOS transistor PDM3 form a first common-source amplifier, and a PMOS transistor PDM4, a transistor Q6, a resistor R4, and a transistor Q5 form a second common-source amplifier. The present invention does not require the additional design of a pre-voltage-stabilizing circuit and a high-voltage operational amplifier, thereby saving chip area. Furthermore, after the voltage-stabilizing startup circuit is started, the startup circuit does not need to be shut down.
Owner:上海帝迪集成电路设计有限公司
Wideband amplifier with low balun error, high linearity and low noise
ActiveCN119696521AAmplifier modifications to reduce non-linear distortionAmplifier modifications to reduce noise influenceLow noiseLoad circuit
The invention discloses a broadband amplifier with low balun error, high linearity and low noise. The broadband amplifier comprises an input end, a common-source amplifier, a differential current balancer, an OTA, a load circuit and an enhanced source follower, an input signal enters from a P1 port and enters the first common source stage amplifier, one path of signal enters the differential current balancer, and the other path of signal enters the second common source stage amplifier and enters the differential current balancer; the two paths of signals are transmitted to ports P5 and P6 to output differential signals; the OTA adjusts the high-order nonlinearity of gds by detecting common-mode levels of P5 and P6 and feeding back a bias level of a control load circuit, compensates offset residues of distortion components of a source follower and a main common-source amplifier, realizes high linearity, and reduces Balun errors through a triple Balun error correction technology. According to the invention, the working frequency range is 0.2 GHz to 6GHz, and the low-Balun error, high-linearity and low-noise performances are realized.
Owner:PENGPAI MICRO (SHANGHAI) ELECTRONICS CO LTD
Comparator circuit with dynamic hysteresis
ActiveUS12316330B2Multiple input and output pulse circuitsElectric pulse generatorSoftware engineeringHemt circuits
A comparator circuit with dynamic hysteresis. A common source branch is configured to conduct a differential current at first and second intermediate outputs responsive to a differential input at first and second inputs, and a common gate branch is configured to generate a voltage at a third intermediate output responsive to the differential current at the first and second intermediate outputs. A hysteresis branch includes a hysteresis current generator including first and second replica transistors having source / drain paths coupled in parallel, and gates coupled to the first and second inputs, respectively. A hysteresis capacitor is coupled between the sources of the first and second replica transistors and the common terminal. Current mirror circuitry is coupled to the source / drain paths of the first and second replica transistors, to supply a hysteresis current responsive to the absence of current conducted by the parallel first and second replica transistors.
Owner:TEXAS INSTRUMENTS INC
Power amplifier, transformer and circuit module
The utility model discloses a power amplifier, a transformer and a circuit module. The power amplifier comprises a differential cascode amplifier, a first neutralizing capacitor, a second neutralizing capacitor and a harmonic suppression unit. A common source electrode of the differential cascode amplifier is connected with a common grid electrode of the differential cascode amplifier to form a first node and a second node, and the first neutralizing capacitor and the second neutralizing capacitor are cross-coupled between a differential input end of the differential cascode amplifier and the first node and the second node. The harmonic suppression unit is connected among the first node, the second node and the ground voltage. According to the power amplifier, the transformer and the circuit module, by introducing the harmonic suppression unit, the fundamental frequency impedance and the second harmonic impedance of the power amplifier are adjusted, suppression of second harmonics is achieved, and the linearity of the power amplifier is improved. Meanwhile, the output impedance Q value of the amplifier is reduced, and compromise among linearity, efficiency and other performance indexes of an output matching network is optimized.
Owner:ICLEGEND MICRO (NANJING) CO LTD
Memory device, manufacturing method of memory device and semiconductor device
The invention provides a memory device and a manufacturing method thereof, and a semiconductor device, and the memory device comprises a substrate which comprises an insulating surface; a memory cell array including a plurality of memory cells disposed on the insulating surface, the plurality of memory cells being repeatedly arranged in a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction intersecting the second horizontal direction; each memory cell comprises a transistor, the transistor comprises a gate insulating layer, a gate structure and an active layer parallel to the insulating surface, the gate structure comprises a gate main body part, the gate main body part comprises a first gate, the first gate extends along the side wall of the active layer, and the gate insulating layer is located between the first gate and the active layer; the bit line structure comprises a plurality of bit lines extending in the first horizontal direction, and the active layer comprises a source end connected to the common source electrode structure and a drain end connected to one bit line. The storage device is high in storage density and simple in preparation process.
Owner:SWAYSURE TECHNOLOGY CO LTD
Non-volatile memory with stacked transistor pairs
A bit cell (100) is disclosed that includes a non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal that switches a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source / drain terminal (121) of the transistor arrangement, and a second common source / drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor device includes a pair of stacked complementary transistors, where a gate (213) of an upper transistor is connected to a first word line (WLN), and where a gate (233) of a lower transistor is connected to a second word line (WLP). A memory device including an array of such bit cells, and a method for controlling bit cells are also disclosed.
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
Low-noise amplifier circuit capable of improving stability and bypass linearity
ActiveCN120934463AAmplifier modifications to reduce non-linear distortionAmplifier modifications to reduce noise influenceLow noiseNoise (radio)
The invention discloses a low-noise amplifier circuit capable of improving stability and bypass linearity, and relates to the technical field of radio frequency integrated circuits. The circuit comprises an input matching module, a low noise amplification module, an output matching module, a bypass module, a common source electrode switch module and a negative feedback virtual ground module. A leakage path is cut off according to cooperative control of an enable signal and an MOS switch tube through the common source electrode switch module so as to improve the linearity of a bypass mode, and a negative feedback loop network is generated by the negative feedback virtual ground module and the output matching module, so that a high-frequency signal is fed back from the negative feedback loop network, and the linearity of the bypass mode is improved. The problem of stability under high gain is solved.
Owner:CHENGDU GANIDE TECH
Semiconductor memory and method of making the same, electronic device
The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.
Owner:YANGTZE MEMORY TECH CO LTD
Bidirectional switch semiconductor packaging device, AC / DC converter and automobile
The utility model discloses a bidirectional switch semiconductor packaging device, an AC / DC converter and an automobile, and relates to the technical field of power supplies, the device comprises a first switch chip, a second switch chip, a plastic package shell and a heat dissipation substrate; the drain electrode or the source electrode of the first switch chip is electrically connected with the drain electrode or the source electrode corresponding to the second switch chip through the same heat dissipation substrate, so that a bidirectional switch structure with the common drain electrode or the common source electrode is formed, and heat dissipation can be carried out on the two switch chips at the same time by utilizing a single heat dissipation substrate. Meanwhile, on the surface of the plastic package shell, a creepage path extension part used for increasing the creepage distance is arranged between the heat dissipation substrate and any group of pins located on the two sides of the plastic package shell. Through the structure, the packaging size of the bidirectional switch semiconductor packaging device can be kept as small as possible, and meanwhile, the problems of power output control, heat dissipation, electrical safety and the like caused by the too small packaging size can be prevented.
Owner:SUZHOU INOSA UNITED POWER SYST CO LTD
Power overlay structure for multi-chip semiconductor package
ActiveJP2025028043ASemiconductor/solid-state device detailsSolid-state devicesDevice materialSemiconductor package
To provide a multi-chip semiconductor package having an interconnecting power overlay structure.SOLUTION: A multi-chip semiconductor package includes a dielectric interconnect layer having an upper surface and a bottom surface, at least one common source pad disposed on the upper surface of the interconnect layer, at least one common gate pad disposed on the upper surface of the interconnect layer, and a plurality of semiconductor devices each including a gate pad and at least one source pad that adhere onto the interconnect layer. The source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad. The source pads of the plurality of semiconductor devices are electrically connected in parallel with one another. The gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad. The gate pads of the plurality of semiconductor devices are electrically connected in parallel with one another.SELECTED DRAWING: Figure 5
Owner:GENERAL ELECTRIC CO
Asymmetric common source inductances to reduce turn-off overvoltage in mosfets
A circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) (110) having a gate, a source, and a drain. The circuit further includes a first inductor (140A) and a second inductor (140B). The first inductor has a small inductance value that is less than a larger inductance value of the second inductor. The circuit further includes a switch (130) configured to include the first inductor in a current path shared by a gate loop and a source loop of the MOSFET when the MOSFET is turning on, and to include the second inductor in the current path shared by the gate loop and the source loop when the MOSFET is turning off.
Owner:SEMICON COMPONENTS IND LLC