192 results about "Common gate" patented technology

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Provided is a semiconductor device including a two-dimensional semiconductor material. The semiconductor device includes a first channel including a first two-dimensional material layer, a second channel being apart from the first channel and including a second two-dimensional material layer, a common gate electrode between the first channel and the second channel, a first source electrode and a first drain electrode in contact with the first channel, and a second source electrode and a second drain electrode in contact with the second channel, wherein one of the first channel and the second channel is an N-type channel, and the other is a P-type channel, and the first channel and the second channel are U-shaped.

The invention relates to a folded cascode low noise amplifier. The disclosed low noise amplifiers (LNAs) include a common emitter amplifier (CE-A), a common gate amplifier (CG-A), and various passive devices located in CE-A and CG-A. The CE-A includes an NPN type bipolar junction transistor (BJT) having emitter and collector (E / C) regions, and a base region located between the E / C regions and connected to an input node. The CG-A includes a P-channel field effect transistor (PFET) having source and drain (S / D) regions, a channel region between the S / D regions, and a gate adjacent to the channel region. A drain region of the PFET is connected to the output node. Further, the common inductor, the collector region of the BJT, and the source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) in which the BJT and the FET are located on different chips and the passive device is located in a back-end-of-line region between the BJT and the FET.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

Disclosed is a device that decouples switching speed and gate delay time using an improved voltage-source gate driver. A shunt capacitor and a shunt resistor are connected in series to parallel across gate resistors of a voltage-source gate driver. The shunt capacitor and shunt resistor allow the gate delay and switching speed effect of the gate resistors to be decoupled. The shunt capacitor provides an initial high charge voltage and discharge gate current to reduce gate delay time. The shunt resistor modifies the effective gate resistance, which affects the gate current and the resulting switching speed. Shunt capacitor and shunt resistor values are determined to achieve the desired switching speed control with minimum gate delay time. When multiple power devices are paralleled, a common gate resistor, a shunt resistor and a capacitor combination is used. Each power device is also provided a respective split-gate resistor.

The utility model discloses a packaging structure of a quasi-monolithic power multiplication amplifier. The packaging structure comprises a frame base island, the lead frame is arranged on the periphery of the frame base island; the four tube core chips are respectively bonded on the front face of the frame base island through bonding materials, two of the tube core chips are connected through a lead to form a common-gate amplification structure, the other two tube core chips are connected through a lead to form a common-source amplification structure, and the four tube core chips are further connected with the lead frame through leads. The four tube core chips jointly form an amplifying circuit of a push-pull structure; and the frame base island, the lead frame, the four tube core chips and the leads are coated with the plastic package material to form a whole through plastic package. The heat dissipation of the power amplifier is facilitated.

A display device includes a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver configured to output a data voltage to the plurality of data lines; a gate driver configured to sequentially output gate signals to the plurality of gate lines; a common line configured to simultaneously apply a common gate signal to the plurality of gate lines; and a timing controller configured to generate the common gate signal.

A method includes forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A first dipole film and a second dipole film are formed on the first gate dielectric and the second gate dielectric, respectively. The Dipole dopants in the first dipole film and the second dipole film are driven into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are then removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form first transistor and a second transistor, respectively.

A display panel that may reduce a bezel area is provided. In the display panel, a scan driver includes an inverter that inverts a carry signal generated from an input signal to output a scan signal, and the inverter includes a first transistor including a polysilicon semiconductor layer; and a second transistor including an oxide semiconductor layer, disposed to overlap the first transistor in a thickness direction of the display panel, and a gate electrode of the first transistor and a gate electrode of the second transistor, which overlap each other in the thickness direction, are electrically connected to each other to constitute a common gate electrode that receives the carry signal.

An integrated circuit includes a first transistor and a second transistor. A first gate spacer is along a first portion of the common gate structure, the first gate spacer having a first width. A first inner spacer is between the first semiconductor channel layers and having a second width, the first width being greater than the second width. A second gate spacer is along a second portion of the common gate structure and having a third width. A second inner spacer is between the second semiconductor channel layers and having a fourth width, and the third width is greater than the fourth width, and the second width is greater than the fourth width. An isolation structure is in contact with one end of the common gate structure, the isolation structure having a fifth width, and the fifth width is greater than the first width and the third width.

The invention discloses a high-linearity medium-power amplifier based on cascode RC negative feedback and a composite matching network. The high-linearity medium-power amplifier comprises a common-source transistor M1, a common-gate transistor M2, a single power supply VDD with an active bias circuit, an input matching network, an output matching network and a negative feedback loop, the input matching network comprises an inductor Lb and an inductor Lg, the output skin matching network comprises an inductor Ld1 and an inductor Ld2, and the negative feedback loop comprises a resistor Rf and a capacitor Cf; the source electrode of the common source transistor M1 is connected with the drain electrode of the common gate transistor M2, one side of the active bias circuit is connected to the grid electrode of the common source transistor M1 through the inductor Lb and the inductor Lg in sequence, the common end of the inductor Lb and the inductor Lg is connected with the input end, and the resistor Rf and the capacitor Cf are connected in series and connected between the grid electrode of the common source transistor M1 and the output end. One side of the inductor Ld2 is connected with the source electrode of the common-gate transistor M2, the other side of the inductor Ld2 is connected with one side of the inductor Ld1, the other side of the inductor Ld1 is connected with the single power supply VDD, and the common end of the inductor Ld1 and the inductor Ld2 is connected with the capacitor Cf and the output end; the method is suitable for radar and communication systems in industrial application, and has important significance for developing high-performance, low-cost and high-integration-level multifunctional chips.

The invention belongs to the technical field of integrated circuits, and particularly relates to a radio frequency amplifier bandwidth expansion circuit based on resistor-capacitor series feedback. The bandwidth expansion circuit comprises a first-stage common-gate amplifier, a second-stage common-source amplifier, a transformer-based inter-stage matching network between the two stages of amplifiers, and two resistor-capacitor series feedback paths, and a resistor-capacitor series feedback path is bridged at two sides of the interstage matching network, and feedback is introduced from the output end of the common source amplifier to the output end of the common gate amplifier, so that the quality factors of two resonant cavities of the interstage matching transformer are adjusted, and the targets of adjusting the gain of the amplifier and expanding the bandwidth of the radio frequency amplifier are further realized.

According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.

A power semiconductor device is provided that includes paralleled transistor cells, and a common source, a common drain and a common gate operatively coupled to the paralleled transistor cells. The power semiconductor device also includes a plurality of common gate contact pads operatively coupled to the common gate, and one or more resistors coupled to respective one or more common gate contact pads of the plurality of common gate contact pads. The one or more resistors are also coupled between the respective one or more common gate contact pads and the common gate. The plurality of common gate contact pads provide a selectable resistive decoupling of the common gate by connection of one of the plurality of common gate contact pads.

According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

A comparator circuit with dynamic hysteresis. A common source branch is configured to conduct a differential current at first and second intermediate outputs responsive to a differential input at first and second inputs, and a common gate branch is configured to generate a voltage at a third intermediate output responsive to the differential current at the first and second intermediate outputs. A hysteresis branch includes a hysteresis current generator including first and second replica transistors having source / drain paths coupled in parallel, and gates coupled to the first and second inputs, respectively. A hysteresis capacitor is coupled between the sources of the first and second replica transistors and the common terminal. Current mirror circuitry is coupled to the source / drain paths of the first and second replica transistors, to supply a hysteresis current responsive to the absence of current conducted by the parallel first and second replica transistors.

The present application discloses a flip voltage follower with common gate stage feedback, including: a first to an eleventh transistor, and an adjustment resistor. The sources of the first to the third transistors are connected to a power supply terminal, the drain of the first transistor and the gates of the first to the third transistors are connected to a first bias current source; the drains of the second and fourth transistors, the source of the sixth transistor and one end of the adjustment resistor are connected together, the source of the fourth transistor is connected to the drain of the eighth transistor, the gates of the sixth and eighth transistors and the drain and gate of the tenth transistor are connected together; the drains of the third and fifth transistors, the source of the seventh transistor and the other end of the adjustment resistor are connected together, the source of the fifth transistor is connected to the drain of the ninth transistor, the drain of the seventh transistor, the gate of the ninth transistor and the drain and gate of the eleventh transistor are connected together; the gates of the sixth and seventh transistors are connected to a bias voltage. The present application provides more design freedom and robustness for the design of the DC bias point of the circuit.

The present disclosure relates to the technical field of microelectronics, and in particular to a capacitor-less dynamic random access memory structure and a manufacturing method therefor. The structure comprises: a low-leakage transistor and a vertical complementary field effect transistor, wherein a drain of the low-leakage transistor is connected to a common gate of the vertical complementary field effect transistor; and drains of P-type and N-type transistors of the vertical complementary field effect transistor are connected to each other, a source of the P-type transistor is connected to a power supply end, and a source of the N-type transistor is connected to a ground wire.

A noise elimination broadband low-noise amplifier without an auxiliary amplifier comprises an input matching network, a first-stage amplification module, an inter-stage matching network, a second-stage amplification module and an output matching module which are sequentially cascaded. The transformer is added to the gate end and the source end of the differential common-gate amplifier, so that noise elimination is realized without introducing an additional auxiliary amplifier. The influence of the parasitic capacitance of the transistor is weakened by introducing the neutralizing capacitor, so that the noise elimination technology can be realized at high frequency. By setting a proper inter-stage matching network and a load inductance value, the two-stage amplification module works at different center frequencies, so that a large bandwidth is kept while excessive gain is not lost. The two problems that firstly, noise generated by an auxiliary amplifier introduced for eliminating the noise of a main amplifier is difficult to eliminate, and secondly, the noise elimination technology is difficult to take effect under high frequency due to parasitic capacitance of a transistor are solved.

The application provides a transient response enhanced multi-loop low-dropout linear voltage regulator, comprising: a bias module for providing a bias voltage; a band gap reference module for providing a reference voltage; a power tube for providing an output voltage; a voltage follower for generating a control voltage and a driving current based on the bias voltage and the reference voltage; a source-coupled error amplifier for generating a gain voltage according to the output voltage and the control voltage; a common gate for generating a first voltage according to the reference voltage and the gain voltage; a pseudo-differential common gate for generating a second voltage according to the reference voltage and the gain voltage; and a dynamic super source follower for forming a push-pull structure at the gate of the power tube according to the first voltage and the second voltage. The application can effectively improve the transient response performance of the voltage regulator.

A turn-off power semiconductor device includes first and second thyristor cells, a common gate contact and a plurality of stripe-shaped electrically conductive first gate runners. Each first gate runner has a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion. The first end portion is directly connected to the common gate contact. The first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer. The second gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer. The first gate electrode layer is directly connected to the common gate contact. At least the first connecting portion of each first gate runner is separated from the first gate electrode layer.

The application provides an in-memory computing circuit and method and a resistance change type memory, the first transistor and the second transistor in the jth memory cell adopt a common gate and common source connection mode, so that the i bit line, the i complementary bit line and the i source line share charges, compared with the existing current convergence-based computing mode, the application provides no direct current in the computing process, solves the problem of excessive current convergence in the prior art, and reduces the power consumption of the in-memory computing circuit. The voltage on the i source line connected with the i voltage reading circuit is the result of the input value of the word line minus the positive and negative product of the memory cell, without the need to set more reading structures, thereby saving the occupied area and delay overhead of the in-memory computing circuit. Due to the connection mode of the memory cell and the bit line, the source line and the complementary bit line, the in-memory computing process is essentially equivalent to the calculation of a differential signal, thereby being able to suppress the influence of non-ideal factors such as process fluctuation on the calculation accuracy.

An RFA (radio frequency amplifier) includes an NCSA (N-type common-source amplifier) established upon a first source node and configured to receive a first signal and output a first internal current; a first NCGA (N-type common-gate amplifier) configured to receive the first internal current and output a second internal current; a second NCGA configured to receive the second internal current and output a first output current; a PCSA (P-type common-source amplifier) established upon a second source node and configured to receive a second signal and output a third internal current; a first PCGA (P-type common-gate amplifier) configured to receive the third internal current and output a fourth internal current; a second PCGA configured to receive the fourth internal current and output a second output current; and a load network comprising a parallel connection of a primary inductor and a tuning capacitor configured to establish an output signal.

The application discloses a GaN vertical complementary field effect transistor (VCFET) and an inverter, the VCFET comprising a substrate, a first transistor, a second transistor and a common gate electrode, the first transistor and the second transistor being vertically stacked on the substrate in sequence; the first transistor is an n-type transistor, and the second transistor is a p-type transistor, and an overall structure of a GaN buffer layer, an n-type transistor GaN channel layer, an AlGaN barrier layer, a p-type transistor GaN channel layer and a p-type transistor GaN doping layer is formed; the n-type channel and the p-type channel are simultaneously controlled through the common gate electrode. On the basis of the structure, the source electrode of the p-type transistor is connected to a high level, the source electrode of the n-type transistor is connected to a low level, the drain electrodes of the two transistors are connected together and simultaneously used as an output end, and the gate electrode is used as an input end, so that the inverter is realized. The VCFET realizes the electronic transmission characteristics of high efficiency and low power consumption, has a smaller footprint while maintaining high performance, and improves the integration degree.

The present application relates to the technical field of electrochemical devices, and provides an electrochemical device for simulating biological signals and a preparation method thereof.The electrochemical device for simulating biological signals is composed of N double-gate structure units, the correlation between the structure units is realized by forming a common gate between one of the lower gate and the upper gate of each double-gate structure unit and one of the lower gate and the upper gate of each other double-gate structure unit, the mutual influence and restriction between each structure unit are realized, and each double-gate structure unit is changed by adjusting the thickness of the electrolyte layer and other conditions, so that the electrochemical device can present the global regulation and mutual induction of nerve activity.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

The present disclosure relates to a frequency doubler circuit (100) comprising: first and second input terminals (101, 102) for receiving an input voltage signal (IN+, IN-) of a first frequency; a first pair of transistors (103a, 103b) connected between a supply line (104) and a first node (105); a second pair of transistors (106a, 106b) connected between a common line (107) and a second node (108), the first and second pairs of transistors (103a, 103b, 106a, 106b) having gates coupled to the respective first and second input terminals (101, 102); an output matching circuit (109) having first and second output terminals (110, 111) for providing an output voltage signal (OUT+, OUT-) of a second frequency; a first common gate transistor (112) connected between the first node (105) and a first input (113) of the output matching circuit (109); and a second common gate transistor (114) connected between the second node (108) and a second input (115) of the output matching circuit (109).

A symmetrical common gate direct current bias network for stacked field effect transmitter distributed high-power amplifier, related apparatus, and related method are provided. An apparatus includes a plurality of amplifier stages connected in parallel between an input port and an output port. The apparatus can also include a first common gate voltage generator operatively connected at a first side of the plurality of amplifier stages and a second common gate voltage generator operatively connected at a second side of the plurality of amplifier stages. The first common gate voltage generator can be operatively connected to the second common gate voltage generator in a symmetrical configuration.