87 results about "Common gate" patented technology

A display device includes a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver configured to output a data voltage to the plurality of data lines; a gate driver configured to sequentially output gate signals to the plurality of gate lines; a common line configured to simultaneously apply a common gate signal to the plurality of gate lines; and a timing controller configured to generate the common gate signal.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

The application provides a transient response enhanced multi-loop low-dropout linear voltage regulator, comprising: a bias module for providing a bias voltage; a band gap reference module for providing a reference voltage; a power tube for providing an output voltage; a voltage follower for generating a control voltage and a driving current based on the bias voltage and the reference voltage; a source-coupled error amplifier for generating a gain voltage according to the output voltage and the control voltage; a common gate for generating a first voltage according to the reference voltage and the gain voltage; a pseudo-differential common gate for generating a second voltage according to the reference voltage and the gain voltage; and a dynamic super source follower for forming a push-pull structure at the gate of the power tube according to the first voltage and the second voltage. The application can effectively improve the transient response performance of the voltage regulator.

The application provides an in-memory computing circuit and method and a resistance change type memory, the first transistor and the second transistor in the jth memory cell adopt a common gate and common source connection mode, so that the i bit line, the i complementary bit line and the i source line share charges, compared with the existing current convergence-based computing mode, the application provides no direct current in the computing process, solves the problem of excessive current convergence in the prior art, and reduces the power consumption of the in-memory computing circuit. The voltage on the i source line connected with the i voltage reading circuit is the result of the input value of the word line minus the positive and negative product of the memory cell, without the need to set more reading structures, thereby saving the occupied area and delay overhead of the in-memory computing circuit. Due to the connection mode of the memory cell and the bit line, the source line and the complementary bit line, the in-memory computing process is essentially equivalent to the calculation of a differential signal, thereby being able to suppress the influence of non-ideal factors such as process fluctuation on the calculation accuracy.

An RFA (radio frequency amplifier) includes an NCSA (N-type common-source amplifier) established upon a first source node and configured to receive a first signal and output a first internal current; a first NCGA (N-type common-gate amplifier) configured to receive the first internal current and output a second internal current; a second NCGA configured to receive the second internal current and output a first output current; a PCSA (P-type common-source amplifier) established upon a second source node and configured to receive a second signal and output a third internal current; a first PCGA (P-type common-gate amplifier) configured to receive the third internal current and output a fourth internal current; a second PCGA configured to receive the fourth internal current and output a second output current; and a load network comprising a parallel connection of a primary inductor and a tuning capacitor configured to establish an output signal.

The present application relates to the technical field of electrochemical devices, and provides an electrochemical device for simulating biological signals and a preparation method thereof.The electrochemical device for simulating biological signals is composed of N double-gate structure units, the correlation between the structure units is realized by forming a common gate between one of the lower gate and the upper gate of each double-gate structure unit and one of the lower gate and the upper gate of each other double-gate structure unit, the mutual influence and restriction between each structure unit are realized, and each double-gate structure unit is changed by adjusting the thickness of the electrolyte layer and other conditions, so that the electrochemical device can present the global regulation and mutual induction of nerve activity.

The present disclosure relates to a frequency doubler circuit (100) comprising: first and second input terminals (101, 102) for receiving an input voltage signal (IN+, IN-) of a first frequency; a first pair of transistors (103a, 103b) connected between a supply line (104) and a first node (105); a second pair of transistors (106a, 106b) connected between a common line (107) and a second node (108), the first and second pairs of transistors (103a, 103b, 106a, 106b) having gates coupled to the respective first and second input terminals (101, 102); an output matching circuit (109) having first and second output terminals (110, 111) for providing an output voltage signal (OUT+, OUT-) of a second frequency; a first common gate transistor (112) connected between the first node (105) and a first input (113) of the output matching circuit (109); and a second common gate transistor (114) connected between the second node (108) and a second input (115) of the output matching circuit (109).

A symmetrical common gate direct current bias network for stacked field effect transmitter distributed high-power amplifier, related apparatus, and related method are provided. An apparatus includes a plurality of amplifier stages connected in parallel between an input port and an output port. The apparatus can also include a first common gate voltage generator operatively connected at a first side of the plurality of amplifier stages and a second common gate voltage generator operatively connected at a second side of the plurality of amplifier stages. The first common gate voltage generator can be operatively connected to the second common gate voltage generator in a symmetrical configuration.

Three-terminal, multi-level non-volatile memory cells having a FeFET in the BEOL are provided. In one aspect, a memory cell includes: a cascade of elements all sharing a common gate terminal and, via the common gate terminal, a common VG, where the cascade of elements includes: an nMOS FET; an ox-FeFET located in the BEOL that is connected to the nMOS FET; and a pMOS FET that is connected to the ox-FeFET. Multi-cell memory implementations thereof, and methods for operating the present memory cells are also provided.

The application discloses a high linearity low noise amplifier based on a post-distortion technology, which comprises a common source and common gate structure circuit, an input matching circuit, an output matching circuit, an auxiliary amplification circuit and a neutralizing inductor; the common source and common gate structure circuit comprises a first common source tube and a second common gate tube; the auxiliary amplification circuit comprises a first common gate tube; the gate and the source of the first common source tube are connected with the input matching circuit; the drain of the first common source tube is connected with the output end of the neutralizing inductor and the source of the first common gate tube; the source of the second common gate tube is connected with the input end of the neutralizing inductor; the drain and the gate of the second common gate tube are connected with the output matching circuit; the source and the gate of the first common gate tube are connected with the auxiliary amplification circuit. The application can realize the balance of multiple indexes such as linearity, power consumption, gain and matching. The application can be widely applied in the field of radio frequency integrated circuit technology.

The application discloses a Fuse correction judgment circuit, a method and an E-Fuse read-write circuit. The circuit comprises a current source unit, a Fuse unit and a signal output unit. The current source unit comprises a first current source for providing a first current and a second current source for providing a second current. The Fuse unit comprises a first Fuse for correction and a second Fuse with a fixed resistance. The current source unit comprises a first MOS tube electrically connected between the first current source and the first Fuse and a second MOS tube electrically connected between the second current source and the second Fuse. The first MOS tube and the second MOS tube are connected in common gate. The signal output unit is used for outputting a correction signal according to the voltage of a node between the second current source and the second MOS tube. The application can provide more adjustment space compared with direct comparison with the Fuse through the high-gain current mirror and the Fuse resistance. The gain is improved to reduce the possibility of misjudgment, reduce the sensitivity to the power supply or noise, and greatly improve the success rate of read-write judgment.

A semiconductor device comprises a first transistor including at least one first nanosheet channel region and a source region and a drain region opposite to the ends of at least one first nanosheet channel region, a second transistor including at least one second nanosheet channel region and a source region and a drain region opposite to the ends of at least one second nanosheet channel region, a common gate on at least one first nanosheet channel region and at least one second nanosheet channel region, and a dielectric layer embedded in the common gate.

According to an embodiment, a radio frequency front end (RFFE) device included in an electronic device in a communication system may comprise a power amplifier, and at least one antenna connected to the power amplifier. The power amplifier includes: a drive stage configured of a first common source amplifier in a differential mode; a main stage including the structure in which a first common gate amplifier is stacked on a second common source amplifier; and a stack stage including a second common gate amplifier stacked on an output stage of the power amplifier.

The invention discloses a multi-stage feedback broadband low-noise amplifier which comprises a first-stage amplifier, a second-stage amplifier and an output-stage buffer amplifier. The first-stage amplifier is composed of a cascode structure and a current multiplexing structure; the second-stage amplification electric appliance is composed of a complementary common-source structure and a current multiplexing structure. The output stage buffer amplification circuit is composed of a common source buffer structure and a current multiplexing structure. According to the invention, the cascade structure and the complementary common-source structure are connected in parallel, and inter-stage capacitance offset, source inductance and current multiplexing are adopted. By means of the mode, the use efficiency of current in the circuit is improved, the circuit gain and noise performance and the like are improved, on the other hand, the Miller effect is effectively restrained, a dominant pole is pushed to high frequency, and therefore the circuit bandwidth is greatly expanded.

The application relates to a silicon-based millimeter wave broadband compact double-drive high-efficiency Doherty power amplifier, belonging to the technical field of radio frequency integrated circuits, comprising an input quadrature coupler, a main and auxiliary two power amplifier paths and a broadband load modulation output network; wherein the power amplifier path adopts a differential common source and common gate unit with cross-coupling capacitance and a double-mode drive topology to improve the gain and efficiency of the millimeter wave frequency band; the output network adopts a slow wave transmission line structure combined with a cascade coupling line pair to realize broadband active load modulation and absorb transistor parasitic capacitance, and simultaneously optimize the chip area. Thus, the problem that the efficiency and bandwidth are difficult to be considered simultaneously due to the limited load modulation bandwidth and the decreased transistor gain of the traditional silicon-based millimeter wave Doherty power amplifier is solved.

Cross-coupled structures are provided. Cross-coupled structures may include a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor, the second transistor, and the fourth transistor may be spaced apart from each other in a first direction, and the third transistor and the second transistor may be stacked in a second direction that is perpendicular to the first direction. The third transistor and the second transistor may include a common gate structure, a first portion of the common gate structure may be a gate structure of the second transistor, and a second portion of the common gate structure may be a gate structure of the third transistor.

The invention is suitable for the technical field of communication, and particularly relates to a low-noise amplifier and a radio frequency chip. The low noise amplifier comprises an input matching circuit, a first amplifying circuit, a second amplifying circuit, a third amplifying circuit, a control circuit, an output matching circuit and an output attenuation circuit. Compared with the prior art, according to the low-noise amplifier, the number of switches needed in a circuit is reduced to the maximum extent, the area of the low-noise amplifier is saved, the first MOS tube and the second MOS tube serve as common source tubes, the third MOS tube serves as a common gate tube, the first MOS tube and the second MOS tube are controlled to be turned on and turned off through an external logic control circuit, and therefore the low-noise amplifier is high in reliability. When the low noise amplifier works at the highest gain gear, the first MOS tube and the second MOS tube are opened at the same time, and when the gain is reduced, the first MOS tube or the second MOS tube is opened according to requirements, so that the power consumption of the low noise amplifier is lower, the area is smaller, and the return loss of a band-pass mode is better.

This invention discloses an operational amplifier circuit for improving slew rate in the field of integrated circuit technology. It includes a basic op-amp unit, a positive-phase slew rate enhancement circuit, and a negative-phase slew rate enhancement circuit. The basic op-amp unit includes an input stage, a common-source common-gate stage, and a Class AB output stage. The output terminal of the input stage is connected to the first input terminal of the common-source common-gate stage, and the output terminal of the common-source common-gate stage is connected to the input terminal of the Class AB output stage. By introducing positive-phase and negative-phase slew rate enhancement circuits and their respective bias circuits, this invention can dynamically adjust the charging and discharging current of the frequency compensation capacitor according to the input voltage. This does not affect the normal operation of the circuit when the op-amp is operating stably. When a large signal step occurs at the input, the slew rate enhancement circuit is rapidly activated, increasing the current of the common-source common-gate stage, accelerating the charging and discharging process of the compensation capacitor, and improving the slew rate of the circuit.

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

The invention relates to the technical field of semiconductors, and discloses a gallium nitride MOS device for improving joint load of a quadruped robot and a packaging method thereof, and the gallium nitride MOS device comprises a substrate, a gallium nitride structure and an MOS structure; the gallium nitride structure sequentially comprises a buffer layer, a gallium nitride layer, an aluminum gallium nitride layer, a P-type gallium nitride layer and a gallium nitride grid electrode from bottom to top, and the left side and the right side of the upper portion of the aluminum gallium nitride layer further comprise a gallium nitride source electrode and a gallium nitride drain electrode; the MOS structure sequentially comprises an N diffusion layer and an MOS grid electrode from bottom to top. The gallium nitride structure and the MOS structure are integrated on the same substrate, common-gate control is achieved through the main control gate, function fusion of the two devices is achieved, the current control capacity is enhanced while the high-frequency and high-voltage advantages of gallium nitride are reserved, voltage overshoot and current sudden change in the high-load shutdown process are effectively restrained, and the reliability of the device is improved. And the dynamic response and the stability of the device are obviously improved.

The invention provides a phase inverter based on a carbon nanotube transistor and an electronic device, relates to the technical field of circuits, and can effectively avoid physical size limitation caused by a silicon-based CMOS (complementary metal oxide semiconductor) due to the adoption of the carbon nanotube transistor. Moreover, the PMOS and the NMOS in the inverter both adopt common-gate structures as gate regions, so that the area of the inverter can be greatly reduced, and the integration level of the inverter is increased.

The application belongs to the technical field of semiconductor, and particularly discloses a GaN bidirectional device with a common gate structure, which comprises a main body structure, a common gate structure and an outer ring structure, the outer ring structure is arranged around the inner circle of the cutting path, the main body structure comprises alternately arranged first main body units and second main body units, the first main body unit comprises a first source electrode and a first gate structure, and the second main body unit comprises a second source electrode and a second gate structure; the common gate structure comprises two drain electrodes, two third source electrodes and two resistors, the two resistors are connected in series, each third source electrode is connected with one resistor, and the two drain electrodes are connected with the first source electrode and the second source electrode, or the first gate structure and the second gate structure; one connection node between the two resistors is set as a low potential end, and the low potential end is connected with the outer ring structure and / or a substrate. The GaN bidirectional device can always extract a low potential during the working process of the device, and effectively improves the reliability of the device.

The application relates to a circuit structure and a radio frequency amplifier circuit, characterized by comprising a common-source MOS transistor, a common-gate MOS transistor and a control circuit; the common-source MOS transistor is used for amplifying an input signal to form a drain current proportional to the input signal; the drain of the common-source MOS transistor is connected with the source of the common-gate MOS transistor, the common-gate MOS transistor transmits the drain current to the drain of the common-gate MOS transistor for output; the output of the drain of the common-gate MOS transistor is connected with the control circuit; and the control circuit is used for controlling the circuit structure to work in different states. Through the design, the third-order intermodulation point of the amplifier can be obviously improved by only adding a control circuit without increasing the main amplifier path current; in addition, the control circuit can also make the whole circuit be turned off, so that the power consumption is reduced without disconnecting the power supply.

The invention discloses a floating power domain circuit. The circuit comprises an anti-impact output unit, a first voltage correlation unit, a second voltage correlation unit and a bias power supply unit, the anti-impact output unit comprises a common gate amplification structure and is used for receiving external high-voltage input and outputting the external high-voltage input to a floating power supply end, and the impact of external high-voltage input jump on the floating power supply end is inhibited through the common gate amplification structure; the first voltage association unit is electrically connected between the floating power supply end and an external reference voltage and is used for establishing a voltage corresponding relation that the floating power supply end is synchronously adjusted along with the external reference voltage; the second voltage correlation unit is electrically connected between the floating power supply end and the floating ground end and is used for establishing a voltage corresponding relation between the floating power supply end and the floating ground end, so that a voltage difference between the floating power supply end and the floating ground end is formed by overlapping threshold voltages or gate source voltages of at least two active devices; and the bias power supply unit is used for providing stable bias current for each unit.

The invention discloses a millimeter wave frequency multiplier based on a broadband transformer matching network and a radar system, and the millimeter wave frequency multiplier comprises an input matching circuit, a frequency multiplier circuit, an inter-stage matching circuit, an output buffer amplification circuit and an output matching circuit which are connected in sequence. The input matching circuit and the output matching circuit adopt a matching network formed by a voltage device and a capacitor; the frequency multiplier circuit uses a common-gate stage as an input stage, and meanwhile an input signal is coupled to a gate through a cross coupling capacitor to be input. The antenna has the advantages that good broadband input and output matching performance and good broadband gain are achieved at the same time.

This document discloses a high-voltage isolation device and associated system for a semiconductor device. The isolation device can support the operation of a 3D NAND memory array of the semiconductor device. In some embodiments, during high-voltage operation (e.g., erase operation), the isolation device can provide a high voltage to the memory array while isolating other circuitry supporting low-voltage operation of the memory array from the high voltage. The isolation device may include a set of narrow active regions separating the low-voltage circuitry from the high voltage, and a gate over the narrow active regions. In another embodiment, the isolation device includes interdigitated narrow active regions and a common gate over the interdigitated narrow active regions for reducing the area occupied by the isolation device.

The invention discloses a semiconductor device and a manufacturing method thereof, electronic equipment and a working method, and the semiconductor device comprises a plurality of storage units, and each storage unit comprises a first storage subunit and a second storage subunit which are distributed at different layers; a plurality of word lines, one column of storage units arranged along a second direction is respectively connected with two word lines, one word line is connected with one column of first storage subunits, and the other word line is connected with one column of second storage subunits; the plurality of common word lines extend along a second direction and are connected with the first storage subunits and the second storage subunits at the same time; wherein the word lines and the common word lines are alternately distributed in the direction perpendicular to the substrate, and the common word lines are located between the two word lines. According to the semiconductor device, common gate control of the storage subunits can be achieved through the common word line, the space in the vertical direction is saved, the stacking number of the storage units is increased, and the manufacturing cost is saved.

A voltage balancing circuit for capacitor banks or voltage cells connected in series. The circuit includes a DC-link with at least two capacitors or voltage cells connected in series and at least two emitter follower balancing circuits connected in parallel. At least one emitter resistor is provided between the emitter of each emitter follower balancing circuit and the mid-point of the DC-link. The gate emitter voltage applied to each emitter follower balancing circuit may be equal to its common gate voltage minus the voltage drop on the corresponding emitter resistor. The invention is also directed at a variable frequency drive for driving an electric motor or a power converter, having a corresponding voltage balancing circuit.

An electronic device may include wireless circuitry with light sources, a set of photodiodes, a resonating element, and a common gate amplifier (CGA). In a transmit mode, the photodiodes may use optical local oscillators to generate equal portions of an antenna current amplified by the CGA for transmission by the resonating element. In a receive mode, the resonating element may generate an antenna current which is amplified by the amplifier and passed to the photodiodes. Including multiple photodiodes coupled to the amplifier in a current sharing configuration may serve to boost power. The amplifier may exhibit a wide bandwidth, may perform impedance matching between the resonating element and the photodiodes, and may isolate the photodiodes from antenna mismatch. The antenna may be integrated into a phased antenna array to further boost power.

This invention provides a switching circuit that prevents damage to integrated circuits caused by electrostatic discharge (ESD). [Solution] The switching circuit 300 includes a body switch 320 and a plurality of switching transistors M3_1 to M3_n. The switching transistors are connected in series between a first signal transmission port SP31 and a second signal transmission port SP32. The control terminal of each switching transistor is connected to a common gate node Ng3. The body terminal of each switching transistor is connected to a common body node Nb3. The control terminal of the body switch is connected to the body terminal or control terminal of one of the switching transistors. The first terminal of the body switch is connected to a common body node. The second terminal of the body switch is connected to a reference voltage rail REF3. When an electrostatic discharge event occurs, the body switch turns on, increasing the voltage at the common body node, which turns on the switching transistors and forms an electrostatic discharge path.