251 results about "Common gate" patented technology

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Provided is a semiconductor device including a two-dimensional semiconductor material. The semiconductor device includes a first channel including a first two-dimensional material layer, a second channel being apart from the first channel and including a second two-dimensional material layer, a common gate electrode between the first channel and the second channel, a first source electrode and a first drain electrode in contact with the first channel, and a second source electrode and a second drain electrode in contact with the second channel, wherein one of the first channel and the second channel is an N-type channel, and the other is a P-type channel, and the first channel and the second channel are U-shaped.

The invention relates to a folded cascode low noise amplifier. The disclosed low noise amplifiers (LNAs) include a common emitter amplifier (CE-A), a common gate amplifier (CG-A), and various passive devices located in CE-A and CG-A. The CE-A includes an NPN type bipolar junction transistor (BJT) having emitter and collector (E / C) regions, and a base region located between the E / C regions and connected to an input node. The CG-A includes a P-channel field effect transistor (PFET) having source and drain (S / D) regions, a channel region between the S / D regions, and a gate adjacent to the channel region. A drain region of the PFET is connected to the output node. Further, the common inductor, the collector region of the BJT, and the source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) in which the BJT and the FET are located on different chips and the passive device is located in a back-end-of-line region between the BJT and the FET.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

The invention relates to a power cover structure for a multi-chip semiconductor package. A multi-chip semiconductor package, the multi-chip semiconductor package comprising: a dielectric interconnect layer having an upper surface and a bottom surface; at least one common source pad disposed on an upper surface of the interconnect layer; at least one common gate pad disposed on an upper surface of the interconnect layer; and a plurality of semiconductor devices each including a gate pad and at least one source pad bonded to the interconnect layer, where the source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad, and where the source pads of the plurality of semiconductor devices are electrically connected in parallel with each other, and wherein the gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad, and wherein the gate pads of the plurality of semiconductor devices are electrically connected in parallel with each other.

The invention provides a boost converter controlled in a PFM mode and a zero cross detection circuit thereof. The zero-cross detection circuit is composed of a biasing circuit and a three-stage comparator. In the three-stage comparator, the first stage adopts a common-gate circuit, receives zero-cross detection two-end input, and adapts to a wide input range; the second stage is a push-pull amplifier, receives the output of the first stage, and accelerates the overturning speed through push-pull input and output; and the third stage is responsible for outputting a zero-cross detection comparison result. The boost converter system comprises a mode switching unit, a switch logic control unit, a driving control unit and a main circuit. The mode switching unit judges whether to enter a PFM mode or not according to the zero-cross detection circuit signal; the switch logic control unit outputs a logic control instruction according to the signal; the driving control unit controls the on and off of the N-type power tube and the P-type power tube in the main circuit according to the instructions. The control mode is combined with high-precision and high-speed zero-cross detection, so that the stability and the response speed of the system are remarkably improved.

Disclosed is a device that decouples switching speed and gate delay time using an improved voltage-source gate driver. A shunt capacitor and a shunt resistor are connected in series to parallel across gate resistors of a voltage-source gate driver. The shunt capacitor and shunt resistor allow the gate delay and switching speed effect of the gate resistors to be decoupled. The shunt capacitor provides an initial high charge voltage and discharge gate current to reduce gate delay time. The shunt resistor modifies the effective gate resistance, which affects the gate current and the resulting switching speed. Shunt capacitor and shunt resistor values are determined to achieve the desired switching speed control with minimum gate delay time. When multiple power devices are paralleled, a common gate resistor, a shunt resistor and a capacitor combination is used. Each power device is also provided a respective split-gate resistor.

The utility model discloses a packaging structure of a quasi-monolithic power multiplication amplifier. The packaging structure comprises a frame base island, the lead frame is arranged on the periphery of the frame base island; the four tube core chips are respectively bonded on the front face of the frame base island through bonding materials, two of the tube core chips are connected through a lead to form a common-gate amplification structure, the other two tube core chips are connected through a lead to form a common-source amplification structure, and the four tube core chips are further connected with the lead frame through leads. The four tube core chips jointly form an amplifying circuit of a push-pull structure; and the frame base island, the lead frame, the four tube core chips and the leads are coated with the plastic package material to form a whole through plastic package. The heat dissipation of the power amplifier is facilitated.

A display device includes a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver configured to output a data voltage to the plurality of data lines; a gate driver configured to sequentially output gate signals to the plurality of gate lines; a common line configured to simultaneously apply a common gate signal to the plurality of gate lines; and a timing controller configured to generate the common gate signal.

A method includes forming a first semiconductor channel region and a second semiconductor channel region, wherein the second semiconductor channel region overlaps the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A first dipole film and a second dipole film are formed on the first gate dielectric and the second gate dielectric, respectively. The Dipole dopants in the first dipole film and the second dipole film are driven into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are then removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form first transistor and a second transistor, respectively.

The invention discloses a CMOS power amplifier which comprises a transconductance tube and a common gate tube, the transconductance tube comprises a first CMOS transistor and a second CMOS transistor, the common gate tube comprises a third CMOS transistor and a fourth CMOS transistor, and sources of the first CMOS transistor and the second CMOS transistor are grounded respectively to form a pseudo differential pair; the drain electrode of the first CMOS transistor and the drain electrode of the second CMOS transistor are connected with the source electrode of the third CMOS transistor and the source electrode of the fourth CMOS transistor respectively to form a common-gate structure. A pre-stage driving amplifier of the CMOS power amplifier outputs a main path and an auxiliary path, the main path is connected with the grid electrode of the first CMOS transistor and the grid electrode of the second CMOS transistor through AC double capacitors, and the auxiliary path outputs direct current bias voltage through an envelope detection circuit to be connected to the grid electrode of the third CMOS transistor and the grid electrode of the fourth CMOS transistor.

A display panel that may reduce a bezel area is provided. In the display panel, a scan driver includes an inverter that inverts a carry signal generated from an input signal to output a scan signal, and the inverter includes a first transistor including a polysilicon semiconductor layer; and a second transistor including an oxide semiconductor layer, disposed to overlap the first transistor in a thickness direction of the display panel, and a gate electrode of the first transistor and a gate electrode of the second transistor, which overlap each other in the thickness direction, are electrically connected to each other to constitute a common gate electrode that receives the carry signal.

An integrated circuit includes a first transistor and a second transistor. A first gate spacer is along a first portion of the common gate structure, the first gate spacer having a first width. A first inner spacer is between the first semiconductor channel layers and having a second width, the first width being greater than the second width. A second gate spacer is along a second portion of the common gate structure and having a third width. A second inner spacer is between the second semiconductor channel layers and having a fourth width, and the third width is greater than the fourth width, and the second width is greater than the fourth width. An isolation structure is in contact with one end of the common gate structure, the isolation structure having a fifth width, and the fifth width is greater than the first width and the third width.

The invention provides a field effect transistor structure integrated with a synchronous current sampling function, which comprises a first plane structure, a second plane structure and a third plane structure, and is characterized in that the first plane structure comprises a first source electrode, a common grid electrode and a second source electrode; the second plane structure comprises a working field effect transistor and a sampling field effect transistor, the working field effect transistor comprises a first source region, a first gate region and a first drain region, the sampling field effect transistor comprises a second source region, a second gate region and a second drain region, the first source region is electrically connected with the first source electrode, and the second source region is electrically connected with the second source electrode; the first gate region and the second gate region are electrically connected with the common gate; the third planar structure comprises a common drain, and the first drain region and the second drain region are electrically connected with the common drain. The working field effect transistor and the sampling field effect transistor are compatible in process, and the working field effect transistor and the sampling field effect transistor share a grid electrode and a terminal, so that synchronous current sampling is realized, and the chip area is reduced.

The invention discloses a high-linearity medium-power amplifier based on cascode RC negative feedback and a composite matching network. The high-linearity medium-power amplifier comprises a common-source transistor M1, a common-gate transistor M2, a single power supply VDD with an active bias circuit, an input matching network, an output matching network and a negative feedback loop, the input matching network comprises an inductor Lb and an inductor Lg, the output skin matching network comprises an inductor Ld1 and an inductor Ld2, and the negative feedback loop comprises a resistor Rf and a capacitor Cf; the source electrode of the common source transistor M1 is connected with the drain electrode of the common gate transistor M2, one side of the active bias circuit is connected to the grid electrode of the common source transistor M1 through the inductor Lb and the inductor Lg in sequence, the common end of the inductor Lb and the inductor Lg is connected with the input end, and the resistor Rf and the capacitor Cf are connected in series and connected between the grid electrode of the common source transistor M1 and the output end. One side of the inductor Ld2 is connected with the source electrode of the common-gate transistor M2, the other side of the inductor Ld2 is connected with one side of the inductor Ld1, the other side of the inductor Ld1 is connected with the single power supply VDD, and the common end of the inductor Ld1 and the inductor Ld2 is connected with the capacitor Cf and the output end; the method is suitable for radar and communication systems in industrial application, and has important significance for developing high-performance, low-cost and high-integration-level multifunctional chips.

The invention belongs to the technical field of integrated circuits, and particularly relates to a radio frequency amplifier bandwidth expansion circuit based on resistor-capacitor series feedback. The bandwidth expansion circuit comprises a first-stage common-gate amplifier, a second-stage common-source amplifier, a transformer-based inter-stage matching network between the two stages of amplifiers, and two resistor-capacitor series feedback paths, and a resistor-capacitor series feedback path is bridged at two sides of the interstage matching network, and feedback is introduced from the output end of the common source amplifier to the output end of the common gate amplifier, so that the quality factors of two resonant cavities of the interstage matching transformer are adjusted, and the targets of adjusting the gain of the amplifier and expanding the bandwidth of the radio frequency amplifier are further realized.

According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.

A power semiconductor device is provided that includes paralleled transistor cells, and a common source, a common drain and a common gate operatively coupled to the paralleled transistor cells. The power semiconductor device also includes a plurality of common gate contact pads operatively coupled to the common gate, and one or more resistors coupled to respective one or more common gate contact pads of the plurality of common gate contact pads. The one or more resistors are also coupled between the respective one or more common gate contact pads and the common gate. The plurality of common gate contact pads provide a selectable resistive decoupling of the common gate by connection of one of the plurality of common gate contact pads.

According to an aspect there is provided a FET device. The FET device comprises a common source body portion and a set of source layer prongs protruding therefrom in a first lateral direction. First dielectric layer portions are arranged in spaces between the source layer prongs. The device further comprises a common drain body portion and a set of drain layer prongs protruding in the first lateral direction. Second dielectric layer portions are arranged in spaces between the drain layer prongs. The device further comprises a gate body comprising a common gate body portion and a set of gate prongs protruding therefrom in a second lateral direction opposite the first lateral direction. Each gate prong is formed intermediate a respective pair of first and second dielectric layer portions. The device further comprises a channel region comprising a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer prongs. The channel layer portions are arranged in spaces between the gate prongs. There is also provided a method for forming a FET device.

The invention provides a complementary field effect transistor, a manufacturing method of the complementary field effect transistor, a memory device and electronic equipment. The complementary field effect transistor comprises an N-type field effect transistor, a P-type field effect transistor and a first isolation layer, wherein the N-type field effect transistor and the P-type field effect transistor are distributed in a stacked mode, and the first isolation layer is located between the N-type field effect transistor and the P-type field effect transistor and extends horizontally. The N-type field effect transistor and the P-type field effect transistor share a common grid electrode extending in the vertical direction. The N-type field effect transistor comprises a first channel layer surrounding the common grid electrode, and a first source electrode and a first drain electrode which surround the common grid electrode and are connected with the first channel layer; the P-type field effect transistor comprises a second channel layer surrounding the common grid electrode and a second source electrode and a second drain electrode which surround the common grid electrode and are connected with the second channel layer, the first isolation layer comprises a silicon oxide isolation layer or at least two groups of pn junction isolation layers, and each group of pn junction isolation layers comprises one N-type doping layer and one P-type doping layer. The device architecture provided by the invention can effectively inhibit current leakage.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

A method includes forming a first semiconductor channel region and a second semiconductor channel region, with the second semiconductor channel region overlapping the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A dipole dopant is incorporated into a first one of the first gate dielectric and the second gate dielectric to a higher atomic percentage, and a second one of the first gate dielectric and the second gate dielectric has a lower atomic percentage of the dipole dopant. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric. The gate electrode and the first gate dielectric form parts of a first transistor, and the gate electrode and the second gate dielectric form parts of a second transistor.

A power semiconductor module may comprise a common drain pad, a first power semiconductor device on a first region of the common drain pad, a second power semiconductor device on a second region of the common drain pad, a molding layer surrounding lateral parts of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad, a common gate pad on the first power semiconductor device and the second power semiconductor device, and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral parts of the common gate pad.

A comparator circuit with dynamic hysteresis. A common source branch is configured to conduct a differential current at first and second intermediate outputs responsive to a differential input at first and second inputs, and a common gate branch is configured to generate a voltage at a third intermediate output responsive to the differential current at the first and second intermediate outputs. A hysteresis branch includes a hysteresis current generator including first and second replica transistors having source / drain paths coupled in parallel, and gates coupled to the first and second inputs, respectively. A hysteresis capacitor is coupled between the sources of the first and second replica transistors and the common terminal. Current mirror circuitry is coupled to the source / drain paths of the first and second replica transistors, to supply a hysteresis current responsive to the absence of current conducted by the parallel first and second replica transistors.

The utility model discloses a power amplifier, a transformer and a circuit module. The power amplifier comprises a differential cascode amplifier, a first neutralizing capacitor, a second neutralizing capacitor and a harmonic suppression unit. A common source electrode of the differential cascode amplifier is connected with a common grid electrode of the differential cascode amplifier to form a first node and a second node, and the first neutralizing capacitor and the second neutralizing capacitor are cross-coupled between a differential input end of the differential cascode amplifier and the first node and the second node. The harmonic suppression unit is connected among the first node, the second node and the ground voltage. According to the power amplifier, the transformer and the circuit module, by introducing the harmonic suppression unit, the fundamental frequency impedance and the second harmonic impedance of the power amplifier are adjusted, suppression of second harmonics is achieved, and the linearity of the power amplifier is improved. Meanwhile, the output impedance Q value of the amplifier is reduced, and compromise among linearity, efficiency and other performance indexes of an output matching network is optimized.

The present application discloses a flip voltage follower with common gate stage feedback, including: a first to an eleventh transistor, and an adjustment resistor. The sources of the first to the third transistors are connected to a power supply terminal, the drain of the first transistor and the gates of the first to the third transistors are connected to a first bias current source; the drains of the second and fourth transistors, the source of the sixth transistor and one end of the adjustment resistor are connected together, the source of the fourth transistor is connected to the drain of the eighth transistor, the gates of the sixth and eighth transistors and the drain and gate of the tenth transistor are connected together; the drains of the third and fifth transistors, the source of the seventh transistor and the other end of the adjustment resistor are connected together, the source of the fifth transistor is connected to the drain of the ninth transistor, the drain of the seventh transistor, the gate of the ninth transistor and the drain and gate of the eleventh transistor are connected together; the gates of the sixth and seventh transistors are connected to a bias voltage. The present application provides more design freedom and robustness for the design of the DC bias point of the circuit.

The present disclosure relates to the technical field of microelectronics, and in particular to a capacitor-less dynamic random access memory structure and a manufacturing method therefor. The structure comprises: a low-leakage transistor and a vertical complementary field effect transistor, wherein a drain of the low-leakage transistor is connected to a common gate of the vertical complementary field effect transistor; and drains of P-type and N-type transistors of the vertical complementary field effect transistor are connected to each other, a source of the P-type transistor is connected to a power supply end, and a source of the N-type transistor is connected to a ground wire.

To provide a multi-chip semiconductor package having an interconnecting power overlay structure.SOLUTION: A multi-chip semiconductor package includes a dielectric interconnect layer having an upper surface and a bottom surface, at least one common source pad disposed on the upper surface of the interconnect layer, at least one common gate pad disposed on the upper surface of the interconnect layer, and a plurality of semiconductor devices each including a gate pad and at least one source pad that adhere onto the interconnect layer. The source pads of the plurality of semiconductor devices are electrically connected to the at least one common source pad. The source pads of the plurality of semiconductor devices are electrically connected in parallel with one another. The gate pads of the plurality of semiconductor devices are electrically connected to the common gate pad. The gate pads of the plurality of semiconductor devices are electrically connected in parallel with one another.SELECTED DRAWING: Figure 5

Semiconductor nanowire devices with cavity spacers and methods of making cavity spacers for semiconductor nanowire devices are described. For example, the semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers are on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions are on either side of the pair of dielectric spacers.