84 results about "Memory cycle" patented technology

An improved computer memory subsystem determines the most efficient memory command to execute. The physical location and any address dependency of each incoming memory command to a memory controller is ascertained and that information accompanies the command for categorization into types of command. For each type of memory command, there exists a command FIFO and associated logic in which a programmable number of the memory commands are selected for comparison with each other, with the memory command currently executing, and with the memory command previously chosen for execution. The memory command having the least memory cycle performance penalty is selected for execution unless that memory command has an address dependency. If more than one memory command of that type has the least memory cycle performance penalty, then the oldest is selected for execution. Memory commands of that type are selected for execution each subsequent cycle until a valid memory command of that type is no longer available, or until a predetermined number has been executed, or until a memory command of another type has higher priority. If an address dependency exists between memory commands of different types, then memory commands of the same type of the oldest memory command is executed to avoid deadlock.

A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a write cycle to the memory device before all of the write data has been stored in the queue and available to the memory device. By beginning the memory cycle as early as possible, the total amount of time required to store all of the write data in the queue and then de-queue the data from the queue is reduced. Consequently, many CPU to memory write transactions are performed more efficiently and generally with less latency than previously possible.

An embedded memory system (10) uses an MRAM core (12) and error correction code (ECC) corrector circuitry (20). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correctly programmed. The errors are identified and corrected during a read or a write cycle and not necessarily when the memory is in a special test mode. As errors are corrected, the error corrections are counted by an error counter (24) to create a count value. The count value is stored in the MRAM core itself and can later be retrieved and read during a test mode for an indication of how many bit corrections are required for the MRAM core over a period of time. The count value is stored by using an unused portion of a write memory cycle during a read operation.

The invention discloses a face expression identification method and device. The method comprises steps that a to-be-identified face image sequence is acquired, and the face image sequence comprises one or more than two face images; each face image of the face image sequence is pre-processed; the pre-processed face images are inputted to a trained training model to carry out expression identification to acquire expression identification results of the face image sequence; a convolutional neural network model, a long-time short-time memory cycle neural network model, a first pooling layer and a logic regression model are sequentially constructed from an input end to an output end of the training model, and the training model is acquired through training a continuous-image set marked with expression categories. The method is advantaged in that face expression identification performance can be effectively improved.

The invention belongs to the medical data analysis and intelligent processing technical field, and specifically relates to a multi-modal nuclear magnetic resonance image case report automatic generation method employing a deep learning model; the method comprises the following steps: importing an attention matrix on the basis of using a convolution nerve network to extract image characteristics; giving different weights on characteristics of different positions via point multiplication operation, thus obtaining image characteristics under different attentions; using a long-short period memorycycle nerve network to form a subject vector of each sentence in a case report according to the image characteristics under different attentions; using another long-short period memory cycle nerve network to form each word according to the subject vector of the sentence; connecting the words so as to obtain the final case report. The method can automatically form a description text of a magnetic resonance image case without using a case template, thus providing deep meanings for mitigating works of radiology department doctors and building an intelligent computer auxiliary diagnosis system.

A write-bank selecting unit selects different memory banks in response to N+1 consecutive write requests, respectively. In each memory cycle, a data writing unit inputs N or less write commands to a data access unit. On the other hand, a primary read-bank selecting unit selects readable memory banks in each memory cycle. A secondary read-bank selecting unit selects memory banks corresponding to read requests for which data blocks could not be read out in the preceding memory cycle. A data reading unit generates read commands for those read banks and inputs the generated read commands to a data access unit. With this configuration, a packet buffer capable of satisfying both of short processing cycles and high memory use efficiency can be provided by using memory devices at a relatively low price.

A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.

The invention discloses a learning behavior dynamic prediction method and device, equipment and a storage medium. The prediction method comprises the following steps: based on the learning behavior data of a user in a historical period, adopting a long-short-time memory cycle neural network as a prediction model for training to obtain an optimal model; and acquiring learning behavior data of the user in the first time period, and outputting a prediction result based on the optimal model. The invention adopts LSTM-RNN as a prediction model to predict the output results, can improve the accuracyof the prediction, and uses an interactive visual analysis mode to display user information data, facilitates viewing and analysis of user data information at the background of the system, so as to help teachers to timely and intuitively know the results of data analysis, and then achieve the ''closed loop'' of the teaching process. The invention can be widely applied to various learning behaviorprediction systems.

An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.

The invention relates to a method of saving memory and constructing a green data warehouse, comprising procedures as follows: (1) Saving memory of a base layer using method of data compression; (2) Saving memory of a collection layer using method of granularity memory such as user class-fine-grained class-coarse-grained class; establishing automatic, configurable and regular data cleaning mechanism for business data which exceeds memory cycle; (3) Adjusting memory cycle according to life cycle of application analysis for application layer; establishing automatic, configurable and regular data cleaning mechanism for business data which exceeds memory cycle. The invention has the advantage of effectively saving memory, automatically cleaning data garbage in time, and enabling clean and neat green data warehouse.

A memory controller includes a circuit to generate a strobe signal for write operations to a DDR SDRAM. The circuit efficiently generates a glitch free strobe signal for a group of data lines. In one implementation, the memory controller includes a write data generation circuits to each transmit a data signal to the memory on a data line, the write data generation circuits being controlled by write enable signals. A write strobe generation circuit generates the strobe signal and the write enable signals, the strobe signal including a preamble window to signal the beginning of the data burst, a data transfer window, and a postamble window to signal the end of the data burst, the write strobe generation circuit generating the write enable signals a half memory cycle early and terminating the write enable signals a half memory cycle late with respect to the data signals generated by the write data generation circuits.

The present invention discloses a magnetic suspension rotor harmonic current inhibition method of a digital controller based on dual parallel structure digital second-order repetitive control (DPSORC). The method comprises: establishing a magnetic suspension rotor kinetic model including quality unbalance and sensor harmonic wave, and employing the magnetic suspension rotor harmonic current inhibition method of the digital controller based on DPSORC. The digital controller employs parallel dual memory cycle and one weighting factor to connect into a magnetic suspension rotor closed loop system so as to improve the robustness of rotating speed nondeterminacy. A traditional first-order repetitive controller phase compensation link can be completely planted into the DPSORC to provide convenience for the actual usage of the DPSORC and allow the controller to have good versatility. The method provided by the invention can perform inhibition of the harmonic wave components of the magnetic bearing coil current in the magnetic suspension rotor, and is suitable for the magnetic suspension rotor system harmonic wave current inhibition including quality unbalance and sensor harmonic wave.