10 results about "Soft error" patented technology

Transformer neural network based decoder for decoding Quantum Error Correction Codes (QECC), comprising, an input layer, a plurality of decoding layers, and an output layer. The input layer is adapted to receive initial noise estimation computed by a noise estimator for noise injected to syndrome bits of codewords encoded using QECC and transmitted over transmission channel(s) subject to interference, and create embeddings for the syndrome bits. The decoding layers adapted to compute an estimated logical operator matrix of each codeword, each comprises a self-attention layer constructed according to a mask indicative of a relation between the embeddings derived from a parity-check matrix of the error correction code. The plurality of decoding layers are trained using a combined loss function directed to minimize LER, BER, and error rate of the noise estimator. The output layer is adapted to produce a vector representing predicted soft error of the codeword's logical operator matrix.

The invention relates to a single-particle selective reinforcement method based on machine learning. The method comprises the steps of reading basic information and structural information of a trigger in a target circuit; part of triggers are randomly extracted for fault injection, and the soft error rate and the function masking rate of the triggers are counted to obtain a gold model; respectively training weight factors of different features for the soft error rate and the function masking rate through a golden model; clustering all triggers in the circuit by using a feature weighted K-Means classifier for the soft error rate and the function masking rate respectively; sensitive triggers in the circuit are determined and selectively reinforced by arranging the product of the soft error rate and the function masking rate. According to the method, the frequency of fault injection required by the circuit is reduced, so that the efficiency is improved, and the method can be used for selective design reinforcement for coping with single-particle soft errors in integrated circuit design.

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding and an apparatus performing the method are provided. The method includes receiving a code word x, wherein the received code word x has t = t + r errors for some r ≥ 1; calculating a minimal monomial basis of an affine space V = {λ(x) ∈ F[x]: λ(x) · S(x) = λ'(x) (mod x 2t ), λ(0) = 1, deg(λ(x) ≤ t + r} where λ(x) is an error locator polynomial and S(x) is a syndrome; calculating a matrix A ≡ (λ j (β i )) i∈[w],j∈[r+1] , where W = {β1,..., β w} is a set of weak bits in x; constructing an r + 1 row submatrix from r + 1 rows of a subset of A such that the last column is a linear combination of the other columns; forming a candidate error locator polynomial using coefficients of the minimal monomial basis resulting from the constructed submatrix; performing a fast Chien search to verify the candidate error locator polynomial; flipping channel hard decisions at error locations found in the candidate error locator polynomial.

The application provides an apparatus, method, and storage medium for evaluation and mitigation of soft-errors in parallel and distributed training and inference of transformers. The apparatus includes two or more processing units capable to communicate with each other and operating collectively as a transformer for deep learning. Each processing unit is configured to perform a matrix multiplication on a first matrix with a first column summation vector added after a last row of the first matrix and a first parameter matrix with a first row summation vector added after a last column of the first parameter matrix, to obtain a second matrix; perform an all-reduce operation on second matrices obtained by the two or more processing units to obtain a third matrix; and determine whether a soft error has occurred by performing a checksum verification on the third matrix.

A processor includes an instruction pipeline that sequentially processes an original instruction and a duplicate instruction, which is generated by duplicating the original instruction. An original register file stores a result obtained by processing the original instruction in the instruction pipeline within a register of a nth index thereof. A duplicate register file stores a result obtained by processing the duplicate instruction in the instruction pipeline within a register of a nth index thereof. A comparing unit compares the register of the nth index in the original register file with the register of nth index in the duplicate register file and outputs an error detection signal, in response to a control signal.

The invention provides a nuclear power plant 6.6 kV medium voltage system relay protection device memory soft error prevention method and device, and the method comprises the steps: calculating an error correction code of constant data written into a static random access memory when a relay protection device is initialized based on an error correction code verification technology, taking the first calculation result as a standard value and storing the standard value in a static random access memory or a dynamic random access memory; in the normal operation process of the relay protection device, the error correction code of constant data in the same static random access memory is calculated in the idle time of each protection interruption task, and a second calculation result is used as a comparison value to be compared with the standard value; if so, refreshing data in the static random access memory; and if the comparison value and the standard value are different and 1-bit overturning exists, error correction is carried out by an error correction code, otherwise, the comparison value is assigned to the standard value for storage. Through real-time detection, comparison and error correction of the error correction codes, the problem of how to prevent the occurrence of memory soft errors is solved.

To reduce countermeasures to an alarm of a soft error factor.SOLUTION: A control device 10 collects data from a field device 30 constituting a plant, detects an abnormality occurring in at least one of a processor module and an input / output module on the basis of the collected data, executes an action for an alarm indicating the abnormality when there is a possibility that the detected abnormality is a soft error factor, and notifies an engineer E of the alarm for which the action has been executed.SELECTED DRAWING: Figure 1

An equivalent fault injection method for simulating single-event soft errors (SEE) in integrated circuits is proposed. Based on the analysis of particle injection location distribution and fault introduction mechanism in ground accelerator tests, the analysis of the proportion of single-event sensitive areas in each unit circuit of the chip integration, and the quantity proportion analysis, the method provides support for determining the input conditions for chip-level SEE simulation through an equivalent fault injection sample set sampling method, thereby more accurately simulating the cross-section of SEE in integrated circuits caused by ground test particles.

The application relates to the technical field of data processing, and discloses a chip memory data fault-tolerant processing method and system. The method comprises the following steps: performing space-time alignment on error events, memory access instruction stream segments and system state parameters of a chip to obtain error characteristic sequences of the chip; performing dependence relationship mining on the error characteristic sequences, and constructing a soft error prediction framework of the chip; performing dynamic risk marking on the memory access instruction stream segments, and performing resource collaborative pre-allocation on the marked instructions to obtain a fault-tolerant scheduling strategy set of the chip; performing redirection testing on the fault-tolerant scheduling strategy set to obtain fault-tolerant scheduling tracks and resource occupation portraits of the chip; performing compilation binding on the fault-tolerant scheduling strategy set to obtain endogenous safe memory access microinstructions of the chip; and performing incremental learning on the soft error prediction framework to obtain a fault-tolerant strategy library of the chip. The application can improve the efficiency of chip memory data fault-tolerant processing.

The invention discloses a single-particle soft error simulation method, a single-particle soft error simulation system and single-particle soft error simulation equipment, belongs to the technical field of integrated circuits, and is used for solving the problems of low fault injection simulation efficiency and poor accuracy of a single-particle soft error simulation method in the prior art. Comprising the steps of receiving system design parameters of a to-be-tested system; on the basis of the parameters, compiling design codes through a simulation tool, executing segmented storage operation, and establishing a plurality of simulation state snapshots; calculating the sampling weight according to the relative proportion of the overturning cross section of the time sequence unit, carrying out the random sampling of the position and time dimensions, and generating an overturning sample for fault injection; based on a plurality of simulation state snapshots, starting simulation from the initialized snapshot, injecting a flipping sample according to a predetermined sequence, integrating an error detection mechanism, and when an output error is detected, gradually reducing the range in a flipping injection sequence by adopting a binary search algorithm, and determining a flipping event causing the error; and calculating the whole single-particle soft error section of the chip and generating a sensitive unit list.