31 results about "Soft error" patented technology

The invention discloses a low-cost soft error reinforcement method based on an approximate triple modular redundancy unit. The method comprises the following steps: establishing an approximate library: establishing an approximate gate unit for a basic gate unit of a to-be-reinforced circuit, and integrally establishing an approximate gate unit library; software modeling: acquiring basic information of each standard gate unit in the circuit, and evaluating the performance of the circuit according to a soft error propagation physical model so as to perform software modeling; and approximate reinforcement: selecting a gate unit in a to-be-reinforced circuit in a semi-directional manner based on improved dynamic adjustment NSGA-II to replace the gate unit with an approximate gate unit in an approximate library, simulating circuit performance indexes through an estimator, performing multi-target optimization solution, obtaining an optimal compromise of area, power consumption and soft error rate through iteration, and giving an approximate reinforcement scheme. The method has high efficiency, practicability and universality, can be used for guiding low-cost soft-error-tolerant approximate reinforcement of various high-reliability structures such as triple modular redundancy (TMR) and the like, and can adapt to multi-scene and multi-requirement circuit reinforcement design.

An apparatus, method, and storage medium for evaluating and mitigating soft errors in parallel and distributed training and reasoning of a transformer are provided. The apparatus comprises two or more processing units (220) capable of communicating with each other and operating together as a transformer for deep learning. Each processing unit (220) is configured to: perform a matrix multiplication on a first matrix and a first parametric matrix to obtain a second matrix, a first column summation vector being added after a last row of the first matrix, a first row summation vector being added after a last column of the first parametric matrix; performing a full reduction operation on the second matrix obtained by the two or more processing units (220) to obtain a third matrix; and determining whether a soft error has occurred by performing a checksum verification on the third matrix.

Transformer neural network based decoder for decoding Quantum Error Correction Codes (QECC), comprising, an input layer, a plurality of decoding layers, and an output layer. The input layer is adapted to receive initial noise estimation computed by a noise estimator for noise injected to syndrome bits of codewords encoded using QECC and transmitted over transmission channel(s) subject to interference, and create embeddings for the syndrome bits. The decoding layers adapted to compute an estimated logical operator matrix of each codeword, each comprises a self-attention layer constructed according to a mask indicative of a relation between the embeddings derived from a parity-check matrix of the error correction code. The plurality of decoding layers are trained using a combined loss function directed to minimize LER, BER, and error rate of the noise estimator. The output layer is adapted to produce a vector representing predicted soft error of the codeword's logical operator matrix.

The invention relates to a single-particle selective reinforcement method based on machine learning. The method comprises the steps of reading basic information and structural information of a trigger in a target circuit; part of triggers are randomly extracted for fault injection, and the soft error rate and the function masking rate of the triggers are counted to obtain a gold model; respectively training weight factors of different features for the soft error rate and the function masking rate through a golden model; clustering all triggers in the circuit by using a feature weighted K-Means classifier for the soft error rate and the function masking rate respectively; sensitive triggers in the circuit are determined and selectively reinforced by arranging the product of the soft error rate and the function masking rate. According to the method, the frequency of fault injection required by the circuit is reduced, so that the efficiency is improved, and the method can be used for selective design reinforcement for coping with single-particle soft errors in integrated circuit design.

The invention discloses a static soft error sensitive bit rapid identification method. The method comprises the following steps: establishing a signal topological relation of each module of a circuit and storing related information of each module; establishing a complex network model of each module from top to bottom; obtaining a complex network circuit and numbering each node; the adjacent signal ratio, the shortest path ratio and the signal connection ratio of each node are obtained and serve as evaluation indexes; constructing an evaluation matrix; constructing a weighted normalized matrix; and obtaining a key signal which has a great influence on the circuit, and the like. The method can be applied to circuit design of aircraft airborne equipment and the like in a complex environment, and reference can be provided for the initial stage of reliability design of a digital circuit of the aircraft airborne equipment. The method can accurately identify the soft error sensitive bit during subsequent reliability analysis of the digital circuit, and can be used for subsequently judging the influence of fault injection of the soft error sensitive bit on the function and performance of the digital circuit. The method is high in sensitive position identification applicability, and can be suitable for accurately identifying sensitive positions under various architectures.

The invention provides a four-node flip self-recovery latch. The four-node flip self-recovery latch comprises an output soft error interception module, a node soft error interception module and a transmission gate module, the output soft error interception module comprises eight input ends and one output end, the eight input ends are N1, N2, N3, N4, N5, N6, N7 and N8 respectively, and the output end is Q; the output soft error interception module is used for ensuring that an output value is kept unchanged when multi-node overturning is caused by a soft error; the node soft error interception module comprises eight node soft error interception circuits with the same structure, and each node soft error interception circuit comprises eight input ends and one output end; the input of the eight-node soft error interception circuit is Q and seven bits of N1, N2, N3, N4, N5, N6, N7 and N8, and the output of the eight-node soft error interception circuit is the other bit of N1, N2, N3, N4, N5, N6, N7 and N8; the node soft error interception module is used for ensuring that respective output values remain unchanged when multiple nodes are flipped due to soft errors; the transmission gate module comprises nine input ends and nine output ends, the nine input ends are used for inputting data, and the output ends are Q, N1, N2, N3, N4, N5, N6, N7 and N8 respectively; and the transmission gate module is used for transmitting data to N1, N2, N3, N4, N5, N6, N7 and N8 in a data transmission mode.

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding and an apparatus performing the method are provided. The method includes receiving a code word x, wherein the received code word x has t = t + r errors for some r ≥ 1; calculating a minimal monomial basis of an affine space V = {λ(x) ∈ F[x]: λ(x) · S(x) = λ'(x) (mod x 2t ), λ(0) = 1, deg(λ(x) ≤ t + r} where λ(x) is an error locator polynomial and S(x) is a syndrome; calculating a matrix A ≡ (λ j (β i )) i∈[w],j∈[r+1] , where W = {β1,..., β w} is a set of weak bits in x; constructing an r + 1 row submatrix from r + 1 rows of a subset of A such that the last column is a linear combination of the other columns; forming a candidate error locator polynomial using coefficients of the minimal monomial basis resulting from the constructed submatrix; performing a fast Chien search to verify the candidate error locator polynomial; flipping channel hard decisions at error locations found in the candidate error locator polynomial.

A controller includes a processor configured to collect data from a device that is included in a system, detect an anomaly that has occurred in at least one of a processor module and an input output module based on the collected data, execute an action on an alarm that indicates the anomaly when the detected anomaly is likely to be caused by a soft error, and notify a user of the alarm on which the action is executed.

The present invention discloses a collaborative verification and reliable operation method and system for protecting control device soft error prevention and error. The system forms a multi-level verification and self-repair mechanism through the mutual cooperation among three CPUs. Specifically, the system performs data self-verification by the startup CPU and the protection CPU respectively, and transmits the verification results to the co-processing CPU. The co-verification module executes the partition round-robin transmission and snapshot comparison of the program to achieve real-time monitoring of the operating state and program co-verification. When an exception occurs in the system, arbitration decisions are made through the consistency judgment module and the arbitration module. If a soft error or data inconsistency occurs, the system automatically calls the backup program or data for recovery through the self-repair module to ensure that the system can quickly return to the normal state. This method significantly improves the soft error resistance of the relay protection control device through multi-level data and program verification and combines with an automatic self-repair mechanism, ensuring the high reliability and security of the system.

The application provides an apparatus, method, and storage medium for evaluation and mitigation of soft-errors in parallel and distributed training and inference of transformers. The apparatus includes two or more processing units capable to communicate with each other and operating collectively as a transformer for deep learning. Each processing unit is configured to perform a matrix multiplication on a first matrix with a first column summation vector added after a last row of the first matrix and a first parameter matrix with a first row summation vector added after a last column of the first parameter matrix, to obtain a second matrix; perform an all-reduce operation on second matrices obtained by the two or more processing units to obtain a third matrix; and determine whether a soft error has occurred by performing a checksum verification on the third matrix.

A controller (10) collects data from each of field devices (20) constituting a plant via each of input / output modules (M), detects, based on the collected data, the input / output module (M) in which abnormality has occurred from among the input / output modules (M), and determines, based on the number of input / output modules (M) in each of which the occurrence of the abnormality has been detected, whether or not a soft error has occurred in the controller (10).

The invention discloses a multi-objective optimization method for relieving a single-particle soft error of a large-scale integrated circuit, and the method achieves the soft error prediction of the large-scale integrated circuit based on a graph neural network algorithm, and obtains a circuit soft error rate and a failure type. Based on a soft error prediction result and a genetic algorithm, a multi-objective optimized Pareto optimal solution set under various reinforcement measures (such as TMR and reinforcement FF unit replacement) is realized, so that the soft error of a large-scale integrated circuit is relieved, and the overhead of extra area and power consumption caused by reinforcement design is balanced. The optimization strategy of the large-scale integrated circuit is formulated through the combination of the two algorithms, and the comprehensive performance of the large-scale integrated circuit for resisting the single-particle soft error, the area and the power consumption is improved through the optimal strategy of the combination of multiple reinforcing measures on the premise of ensuring that the circuit avoids serious harm caused by the single-particle effect. The method can be used for providing guidance for radiation hardening design and optimization of a large-scale integrated circuit.

The invention relates to the technical field of semiconductor device reliability evaluation, and discloses an atmospheric environment thermal neutron soft error rate evaluation method, which comprises the steps of chip microstructure reverse analysis, Monte Carlo simulation, accelerator test and LET spectrum correlation and error rate calculation. According to the method for evaluating the soft error rate of the thermal neutrons in the atmospheric environment, LET spectrums in the atmospheric environment and in the ground accelerator environment are generated through Monte Carlo simulation, and by taking a chip critical linear energy transfer value as a correlation factor, the soft error rate of the thermal neutrons in the atmospheric environment is evaluated according to the overlapping ratio of the LET spectrums in the atmospheric environment and in the ground accelerator environment. According to the method, the soft error rate in the actual atmospheric environment is obtained by combining test data in an accelerator test, large errors caused by LET spectrum differences are avoided, the accuracy of the soft error in the actual atmospheric environment is improved, and a quantifiable and verifiable evaluation technology is provided for the anti-radiation design of a chip.

To construct a soft error rate evaluation system which quickly evaluates a change in soft error rate due to a program change. The soft error rate evaluation system which evaluates the radiation resistance of electronic equipment includes: (a) a procedure of extracting a first feature amount at the time of execution of each of a plurality of irradiation evaluation programs from the plurality of irradiation evaluation programs and their program input conditions; (b) a statistical analysis modeling procedure of performing statistical analysis modeling from the first feature amount of each of the plurality of irradiation evaluation programs and a soft error rate for each of the plurality of irradiation evaluation programs obtained in a neutron irradiation test conducted in advance, to generate a statistical analysis model; (c) a procedure of extracting a second feature amount at the time of execution of an evaluation target program from the evaluation target program and its program input conditions; and (d) a soft error rate calculation procedure of calculating a soft error rate of the evaluation target program from the second feature amount of the evaluation target program by using the statistical analysis model.

The invention discloses an internal single-particle fault transmission testing method for a SiP microsystem chip, and belongs to the technical field of integrated circuit single-particle effect testing. According to the method disclosed by the invention, the influence of single-particle faults generated by the FPGA in different working modes on the working state of the SiP device is obtained by analyzing each key node of the SiP core processing chip FPGA and a SiP single-particle soft error transmission path and performing single-particle detection on an FPGA sensitive module through simulation; the single-particle cross section of each sensitive module of the FPGA is calculated according to the test data of the single-particle upset and the single-particle function interruption of each sensitive module of the FPGA chip, so that the problems that the SiP single-particle effect ground test is inaccurate and the fault transmission path and the data are difficult to obtain are solved, and a basis is provided for the SiP single-particle ground simulation test.

The invention provides an atmospheric neutron radiation test soft error rate determination method, system and device and a medium, and relates to the technical field of electronic device radiation effects, and the method comprises the steps: configuring test parameters for carrying out an atmospheric neutron radiation test on a digital-to-analog conversion circuit DAC device, the test parameters comprise energy values of at least one type of atmospheric neutrons, DAC device parameters and test equipment parameters; acquiring a digital input signal, a digital output signal and an analog output waveform of the DAC device in the test process; according to the digital input signal, the digital output signal and the analog output waveform, whether the DAC device generates a single event effect in the test process is judged, and the soft error rate of the DAC device is determined according to the occurrence frequency of the single event effect. According to the invention, by arranging the ADC device, attenuation and distortion of long-distance transmission of the analog signal are avoided, so that the soft error rate can be evaluated more accurately.

The present invention relates to a control device, a control method, and a computer-readable recording medium, the control device (10) collecting data from each field device (20) constituting a workshop via each input / output module, detecting, on the basis of the collected data, an input / output module in which an abnormality has occurred among the input / output modules, and storing the detected input / output module in the workshop. Whether or not a soft error has occurred in the control device (10) is determined on the basis of the number of input / output modules for which the occurrence of the abnormality has been detected.

To construct a soft error rate evaluation system for quickly evaluating changes in a soft error rate due to program changes.SOLUTION: Provided is a soft error rate evaluation system for evaluating radiation resistance of electronic devices, comprising: (a) a procedure for extracting a first feature quantity during execution of each of a plurality of irradiation evaluation programs from the plurality of irradiation evaluation programs and their program input conditions; (b) a statistical analysis modeling procedure for performing statistical analysis modeling from the first feature quantity of each of the plurality of irradiation evaluation programs and soft error rates for each of the plurality of irradiation evaluation programs obtained in a previously conducted neutron irradiation test to generate a statistical analysis model; (c) a procedure for extracting a second feature quantity during execution of an evaluation target program from the evaluation target program and its program input conditions; and (d) a soft error rate calculation procedure for calculating the soft error rate of the evaluation target program by using the statistical analysis model from the second feature quantity of the evaluation target program.SELECTED DRAWING: Figure 1

To appropriately determine occurrence of a soft error.SOLUTION: The control device 10 collects data from each field device 20 constituting the plant via each input / output module, detects an input / output module in which an abnormality has occurred among the input / output modules based on the collected data, and determines the presence or absence of occurrence of a soft error in the control device 10 based on the number of input / output modules in which the occurrence of the abnormality has been detected.SELECTED DRAWING: Figure 2

A control device includes an arithmetic processing part, a programmable circuit part, and an abnormality notification part. The programmable circuit part includes a storage part, an abnormality detection part, and an abnormality recording part. The storage part stores a configuration data. The abnormality detection part detects a soft error of the storage part. The abnormality recording part records information of the soft error detected by the abnormality detection part. The abnormality notification part determines whether information of a new soft error is recorded in the abnormality recording part, and when determining that information of a new soft error is recorded, notifies the arithmetic processing part of occurrence of the new soft error.

A processor includes an instruction pipeline that sequentially processes an original instruction and a duplicate instruction, which is generated by duplicating the original instruction. An original register file stores a result obtained by processing the original instruction in the instruction pipeline within a register of a nth index thereof. A duplicate register file stores a result obtained by processing the duplicate instruction in the instruction pipeline within a register of a nth index thereof. A comparing unit compares the register of the nth index in the original register file with the register of nth index in the duplicate register file and outputs an error detection signal, in response to a control signal.

The invention provides a nuclear power plant 6.6 kV medium voltage system relay protection device memory soft error prevention method and device, and the method comprises the steps: calculating an error correction code of constant data written into a static random access memory when a relay protection device is initialized based on an error correction code verification technology, taking the first calculation result as a standard value and storing the standard value in a static random access memory or a dynamic random access memory; in the normal operation process of the relay protection device, the error correction code of constant data in the same static random access memory is calculated in the idle time of each protection interruption task, and a second calculation result is used as a comparison value to be compared with the standard value; if so, refreshing data in the static random access memory; and if the comparison value and the standard value are different and 1-bit overturning exists, error correction is carried out by an error correction code, otherwise, the comparison value is assigned to the standard value for storage. Through real-time detection, comparison and error correction of the error correction codes, the problem of how to prevent the occurrence of memory soft errors is solved.

To reduce countermeasures to an alarm of a soft error factor.SOLUTION: A control device 10 collects data from a field device 30 constituting a plant, detects an abnormality occurring in at least one of a processor module and an input / output module on the basis of the collected data, executes an action for an alarm indicating the abnormality when there is a possibility that the detected abnormality is a soft error factor, and notifies an engineer E of the alarm for which the action has been executed.SELECTED DRAWING: Figure 1

The present invention provides a memory error discrimination device and a computer program for memory error discrimination, which can discriminate whether an error occurring in a three-dimensionally stacked memory is a soft error caused by radiation incident on the memory. The memory error discrimination device includes: an error detection unit (22) that detects memory elements in each of multiple layers included in a three-dimensionally stacked memory (2) in which an error has occurred; an error position determination unit (23) that determines the positions of the memory elements in which errors have occurred in the multiple layers; and a determination unit (24) that, when the positions of the memory elements in which errors have occurred are arranged in a straight line across two or more predetermined numbers of layers among the multiple layers, determines that the error occurring in the memory is a soft error caused by radiation incident on the memory.

An equivalent fault injection method for simulating single-event soft errors (SEE) in integrated circuits is proposed. Based on the analysis of particle injection location distribution and fault introduction mechanism in ground accelerator tests, the analysis of the proportion of single-event sensitive areas in each unit circuit of the chip integration, and the quantity proportion analysis, the method provides support for determining the input conditions for chip-level SEE simulation through an equivalent fault injection sample set sampling method, thereby more accurately simulating the cross-section of SEE in integrated circuits caused by ground test particles.

Methods, systems, and devices for radiation monitoring using accumulated parity of non-protected latches are described. An array of non-protected latches store data over time and may be monitored using one or more latches to determine whether one or more errors occur. In some cases, the array may include multiple lanes of latches, where each lane may include a lane latch for parity testing and an output latch. During a parity scan, parity may be periodically generated for the data of each lane and compared to previous parity results to keep track of any soft error events that occur. The parity results for each lane may be combined to output an error flag. In some examples, the error flag may be output to a mode register, and parity testing may be performed based on one or more commands, modes, one or more counters, or with error correction operations.

The application relates to the technical field of data processing, and discloses a chip memory data fault-tolerant processing method and system. The method comprises the following steps: performing space-time alignment on error events, memory access instruction stream segments and system state parameters of a chip to obtain error characteristic sequences of the chip; performing dependence relationship mining on the error characteristic sequences, and constructing a soft error prediction framework of the chip; performing dynamic risk marking on the memory access instruction stream segments, and performing resource collaborative pre-allocation on the marked instructions to obtain a fault-tolerant scheduling strategy set of the chip; performing redirection testing on the fault-tolerant scheduling strategy set to obtain fault-tolerant scheduling tracks and resource occupation portraits of the chip; performing compilation binding on the fault-tolerant scheduling strategy set to obtain endogenous safe memory access microinstructions of the chip; and performing incremental learning on the soft error prediction framework to obtain a fault-tolerant strategy library of the chip. The application can improve the efficiency of chip memory data fault-tolerant processing.

The invention discloses a single-particle soft error simulation method, a single-particle soft error simulation system and single-particle soft error simulation equipment, belongs to the technical field of integrated circuits, and is used for solving the problems of low fault injection simulation efficiency and poor accuracy of a single-particle soft error simulation method in the prior art. Comprising the steps of receiving system design parameters of a to-be-tested system; on the basis of the parameters, compiling design codes through a simulation tool, executing segmented storage operation, and establishing a plurality of simulation state snapshots; calculating the sampling weight according to the relative proportion of the overturning cross section of the time sequence unit, carrying out the random sampling of the position and time dimensions, and generating an overturning sample for fault injection; based on a plurality of simulation state snapshots, starting simulation from the initialized snapshot, injecting a flipping sample according to a predetermined sequence, integrating an error detection mechanism, and when an output error is detected, gradually reducing the range in a flipping injection sequence by adopting a binary search algorithm, and determining a flipping event causing the error; and calculating the whole single-particle soft error section of the chip and generating a sensitive unit list.

The invention discloses a control or / and protection system memory soft error processing method and system, and belongs to the technical field of industry, and the processing method comprises the following steps: when detecting that a control or / and protection system generates a memory soft error, locking a data transmission outlet of the control or / and protection system; restarting and recovering the state of the control or / and protection system to a test state; detecting whether the control or / and protection system works normally, if so, opening a data transmission outlet of the control or / and protection system, and switching the operation state of the control or / and protection system to a set state; and if not, uploading an abnormal signal to the terminal. According to the processing method, the memory soft error can be detected in time, system restart recovery can be carried out, the system running state can be switched in time, and the influence of the memory soft error on an application layer is reduced.

A controller includes a first processor that performs a process of collecting data from each device constituting a system via each input / output module, detecting, based on the collected data, the input / output module in which abnormality has occurred from among the input / output modules, and determining, based on the number of the input / output modules in each of which the occurrence of the abnormality has been detected, whether or not a soft error has occurred in the own controller.