2369results about "Redundant data error correction" patented technology

Apparatuses, systems, and methods for bounded fault compliant metadata storage. Memory devices include a first data terminal and a second data terminal. As part of an access operation a first set of data and a first set of metadata may be sent / received across the first terminal and a second set of data and a second set of metadata may be sent / received across the second terminal. The first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. The two locations may be remote from each other.

The invention discloses a computer memory bank fault prediction method and system based on deep learning, and relates to the technical field of computer hardware fault diagnosis, and the system comprises a multi-source time sequence data collection module which is used for obtaining memory bank operation state data in real time; the dynamic feature enhancement module is based on a composite architecture of a generative adversarial network and transfer learning, comprises a fault mode generator, and generates synthetic data consistent with real fault distribution by using an LSTM network; aligning feature spaces of different hardware platforms through a maximum mean difference loss function; the multi-modal fusion deep learning model comprises a space-time convolutional network, a graph attention network and an adaptive weight adjustment mechanism; and the fault early warning analysis module is used for analyzing a fault probability predicted value, an interpretable thermodynamic diagram and a maintenance suggestion. According to the invention, passive maintenance is changed into active prevention and control, and preposition and precision of fault management are realized through dual mechanisms of long-term trend prediction and short-term risk early warning.

The invention discloses a large model generation content traceability technology based on model copyright ID watermark embedding, which comprises the following steps that: firstly, a large model content generator compiles a dynamic watermark embedding process into an arithmetic circuit, and generates a watermark text and a proof by using a zero-knowledge proof algorithm; then the large model content generator publishes the text with the watermark and the proof together, and hides the copyright ID and the secret key; a large model content user verifies the proof and the watermarked text through a smart contract by adopting a zero-knowledge verification algorithm; after verification is passed, an adversarial sample corresponding to the text with the watermark is generated, an adversarial training method is used for optimizing the text with the watermark, and parameters of the Viterbi balance algorithm are dynamically adjusted and improved. According to the method, the concealment and the generation quality are balanced, high-capacity watermark embedding is realized, the tamper resistance and the accurate traceability of multi-model copyright disputes are improved, and the privacy protection intensity is improved.

Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses, systems, and methods for per row error correct and scrub (pRECS) information. There may be pRECS information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ECS) operations. The memory may store the pRECS information in the memory array, for example, each row may store the pRECS information associated with that row.

A bank of a memory device may be divided into column planes. Each column plane may be associated with column selects. In some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. In some examples, the metadata may be mapped to the data based on a portion of a column address. In some examples, whether the memory device provides metadata responsive to a column address may be based on a value stored in a mode register. In some examples, the portion of the column plane associated with the one column select associated with metadata may also store error correction code data associated with the data of the remaining column selects.

A bank of a memory device is divided into column planes. Each column plane is associated with column selects. A portion of a column plane associated with one column select used to store metadata associated with data of the remaining column selects. Both the metadata and the data are provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

The invention provides a large model retrieval enhancement generation method fused with a multi-source knowledge base, and relates to the technical field of large model retrieval enhancement generation. The method comprises the steps that firstly, user query is analyzed, multiple implied independent retrieval intentions are recognized and separated, and a knowledge source identifier is distributed to each retrieval intention subtask based on a mapping rule; according to the method, related evidence fragments are acquired in parallel from a heterogeneous knowledge source library in a targeted manner, multi-level relation analysis is further performed on the original evidence fragments by introducing a cross validation engine, so that a structured evidence conflict graph is constructed, and then the evidence conflict graph is intelligently processed by applying a game theory excitation algorithm. The method comprises the following steps: obtaining an evidence set with internal consistency, forming a guide signal through structured analysis, and finally, inputting original user query, the synthesized evidence set and the guide signal into a large language model in combination with a pre-constructed cue word template to generate a final answer under constraint, so as to realize retrieval enhancement generation fused with multi-source knowledge base retrieval.

The invention provides a decoder, a decoding method, a memory system, an operation method of the memory system and a controller. The decoder comprises a first processing circuit, a second processing circuit, a processor and a bit flipping circuit, the first processing circuit is configured to obtain a check formula and a check formula weight based on a to-be-decoded code word and a check matrix in a current iteration; the second processing circuit is configured to obtain the energy of the to-be-decoded codeword in the current iteration based on the check matrix, the check formula and the overturning state of the to-be-decoded codeword in the current iteration; the processor is configured to: determine a flipping threshold in a current iteration based on a change state of the checkout weight; and the bit flipping circuit is configured to output the to-be-decoded code word in the next round of iteration based on a comparison result of the energy of the to-be-decoded code word in the current iteration and the flipping threshold value in the current iteration determined by the processor.

The invention belongs to the technical field of automobile electronic manufacturing / chip burning, relates to an automobile PMIC chip burner, a burner system and a burning method, and aims to solve the problems of high system complexity and cost, low burning efficiency, insufficient reliability, insufficient safety, low production line automation degree and the like in the existing chip burning technology. The whole burning process is directly coordinated / controlled through the main control unit, an intermediate conversion link is eliminated, and the system complexity and the equipment cost are reduced; instruction conversion is carried out through the interface conversion module so as to be compatible with various types of chips; the power supply management module adopts dual-power input, the target connection interface ensures reliable physical electrical connection with the PMIC chip, the state indication module feeds back the burning state and error information in real time, and the man-machine interaction experience is improved. The device universality and the automation degree of a production line are remarkably improved, cost is low, compatibility is high, burning efficiency is high, the device is suitable for a burning system deployed on site, and the harsh requirement for zero defect of the vehicle gauge level is met.

The invention relates to a BMC firmware mirror image recovery method and device and terminal device.The method comprises the steps that a storage area of a preset storage chip is divided into multiple areas, and the multiple areas comprise a first area and a second area; a first file in the firmware mirror image file is coded through a forward error correction algorithm, redundant recovery data is obtained, backup files of second files except the first file in the firmware mirror image file are obtained, and the first file comprises a root file system; the first file and the redundancy recovery data are stored in the first area, and the second file and a backup file of the second file are stored in the second area; when it is detected that the first file is abnormal, the first file is recovered based on the redundant recovery data through a forward error correction algorithm; and when detecting that the second file is abnormal, recovering the second file through the backup file of the second file. According to the method and the device, the problem that the reliability of recovering the firmware mirror image file through out-of-band network transmission is relatively low is solved.

A method and associated memory system for randomizing memory storage data. The method and system receive at a data inverter user data and meta data sequence having an inversion seed bit, determine a value for the inversion seed bit from a look up table specifying inversion seeds for different pages of data to be stored in a memory, depending on the value of the inversion seed bit, bit-flip the user data and meta data sequence except for the inversion seed bit; and regardless of bit-flipping, exclusive OR (XOR) the user data and meta data sequence with a random sequence to produce an XORed sequence for storage in the memory as randomized data.

Techniques for optimizing distillation tile layouts for distillation tiles in a magic state factory of a quantum computer and a scheduling of distilled magic state production (e.g., using temporally encoded lattice surgery based (TELS-based) magic state distillation) using said distillation tiles are disclosed. Customized designs for distillation tile layouts that reduce space-time costs when executing a given quantum algorithm are presented, wherein the designs may be customized based, at least in part, on a selected classical error-correcting code and distillation circuit, on a decision whether to perform parallelized TELS-based magic state distillation, etc. Production of distilled magic states may then be configured using a round robin scheduling design in order to minimize potential time in which a processing core of the quantum computer is waiting for another newly distilled magic state from the magic state factory to use for logical computation related to the given quantum algorithm being executed.

The invention discloses a distributed file backup method for a sonar database system, which belongs to the technical field of sonar data processing and comprises the following steps: acquiring file data containing underwater acoustic signal data from the sonar database system; fragmenting the file data to generate data blocks and dynamically adjusting the sizes of the data blocks; generating a unique identifier for the data block based on the content hash value and the metadata; selecting distributed storage nodes based on availability, storage capacity, network delay and geographical distribution factors; the transmission data block uses an encryption protocol; updating the storage position and state of the backup metadata record; periodically verifying the integrity and availability of the backup data; executing a data recovery process to recover the original file data; the dynamically adjusted backup policy is based on real-time operation requirements and data importance levels. According to the method, through distributed storage and dynamic optimization, the backup efficiency, the data security and the system reliability are improved, and the method is suitable for sonar data management in an underwater detection system.

The invention discloses a data processing method and device, electronic equipment and a computer storage medium, and relates to the technical field of data acquisition, the method comprises the following steps: acquiring an acquisition data packet sent by each data acquisition module, and analyzing according to the acquisition data packet to obtain successfully analyzed data, the successfully analyzed data at least comprising an acquisition node identifier; determining a memory address identifier of the successfully analyzed data according to the acquisition node identifier and a preset Hash mapping table, and after the successfully analyzed data is stored in a memory buffer area mapped by the memory address identifier, performing data quality verification according to the successfully analyzed data to obtain a quality verification result; after the data quality verification is completed, data reorganization is carried out according to the successfully analyzed data to obtain reorganized data, data restoration is carried out on the reorganized data according to the quality verification result to obtain final output data, and the method and device aim at improving the processing capacity of large-scale data collection so as to ensure the accuracy and timeliness of data collection.

The invention discloses a data management system based on unmanned aerial vehicle surveying and mapping, and particularly relates to the technical field of data management. The method comprises the steps of collecting unmanned aerial vehicle surveying and mapping data, and performing space coordinate registration and unified coding; performing spatial region division according to the terrain elevation variable coefficient and the obstacle projection coverage rate to obtain a high-density verification region and a low-density verification region; for the high-density verification area, calculating the feature matching degree of an overlapping area of adjacent frames through a local feature matching algorithm, and outputting first correction data; performing data compensation on the low-density verification region by adopting spatial interpolation and cubic spline interpolation to generate second correction data; generating a full-scene reconstruction data frame based on the first correction data and the second correction data; based on full-scene data frame reconstruction, region weight factor distribution, differential error correction coding execution and unmanned aerial vehicle surveying and mapping result data output, the spatial adaptability of data verification is effectively improved, and the overall accuracy and integrity of unmanned aerial vehicle surveying and mapping data are improved.

In memory reads, an increase in a number of correctable errors increases a likelihood that an uncorrectable error will occur. Thus, tracking of correctable errors per memory page is one technique that can be used and if the number of errors on a memory page exceeds a threshold then the memory page can be replaced through dynamic memory re-mapping. However, having a counter per memory page to track the errors is costly due to the number of memory pages. Accordingly, a system is proposed wherein a group of counters is used that acts as a cache of counters that track memory pages of interest due to a variety of factors. Additionally, an eviction policy can control which memory pages are tracked so that only the most interesting candidate pages can be tracked in accordance with a policy.

The invention relates to the field of computer peripherals and display control. The screen direction switching and picture transmission system based on the USB channel comprises a host end processing module, a screen end display module, a USB control module, a host-display bidirectional feedback module and a direction sensing module, the host end processing module is connected with the screen end display module through a USB channel, the direction sensing module is used for sensing the real-time direction of the screen end display module, and the USB control module is used for direction parameter interaction between the host end processing module and the screen end display module; the host end processing module is used for collecting original picture data and obtaining preprocessed original picture data according to the original picture data; and the screen end display module is used for receiving the preprocessed original picture data transmitted by the USB control module. Through multi-sensor fusion and hardware acceleration, high-precision real-time sensing and low-delay direction switching of the screen posture are achieved, and the problem that manual adjustment delay is high in a traditional scheme is solved.

Predictive block health assessment of a non-volatile memory can be performed by storing a pre-trained neural network for this purpose on the memory device itself. As operational errors occur during operation of the memory device, this defect data is saved by the non-volatile memory and used as input data for the neural network to identify and retire potential bad blocks before data loss occurs.

The invention relates to the technical field of PCIe (Peripheral Component Interconnect Express), in particular to a PCIe dynamic degradation type link resetting method and system. Comprising the following steps: S1, continuously reading the LTSSM state of a PCIe link, recording the duration of an abnormal state, and when the duration exceeds a preset threshold value, judging that timeout abnormity exists; s2, after the abnormal early warning is received, a dynamic degradation reset instruction for the NVMe controller is initiated; s3, the state machine control unit takes over the reset link initialization process and follows the physical layer priority gt; the link layer is preferentially gt; a priority strategy is simplified by a transaction layer, and a centralized resource guide link rapidly completes training and enters an L0 state. Compared with the prior art, the method has strict protocol compliance, the reset efficiency is improved, and the overall stability and performance of the system are optimized.

The invention relates to the field of distributed storage, and discloses a distributed memory system based on erasure codes and a dynamic repair mechanism. Comprising a data node cluster, a metadata management cluster, a bandwidth token management module, a dynamic repair composer and a repair agent node. And the data node cluster divides the object into strip generation data fragments and verification fragments and dispersedly stores the data fragments and the verification fragments according to a placement rule. And the metadata management cluster maintains object stripe mapping, a fragment position set, erasure code protection configuration and a version epoch, and records a repair intention log. And the bandwidth token management module grants repair execution permission according to the fault domain budget. The dynamic repair composer generates availability repair and durability repair tasks, the temporary check fragments are written in when the number of the available check fragments is lower than a threshold value in the availability stage, and the configuration fragments are recovered and the temporary fragments are recovered in the durability stage. And the consistency of version epochs is verified before the agent node is repaired and written back, and if not, recalculation is carried out.

The invention provides a processing method for resisting single event upset for avionics equipment. The processing method comprises the following steps: step 1, defining and initializing a configurable hierarchical verification data structure body; step 2, entering a loop task and obtaining to-be-written data; 3, writing to-be-written data and a correction mode into the data structure body; and 4, when data needs to be read, reading the to-be-read data from the data structure body in groups. Compared with a traditional triple modular redundancy scheme, the method has the advantages that the storage occupation is reduced by more than 60%, meanwhile, the problem that the cost of real-time error correction and detection of memory data by directly using Hamming codes in aviation equipment is high can be solved, the error correction and detection capability can be achieved, the resource overhead of coding and decoding is reduced, and the error correction and detection efficiency is improved. And the high requirements of aviation equipment on real-time performance and resource efficiency are met.

A data protection method and system are provided. At least one computing device provides information representing failure of a drive that is assigned to a RAID group. Available storage on each of a plurality of drives in use in the RAID group is identified and at least one virtual drive is built using at least the available storage. Data associated with the failed drive is provided to the virtual drive(s). The virtual drive(s) is / are assigned to the RAID group, and appears to be the failed drive in a non-failed state. Information representing the failed drive having been replaced is received and data from the at least one virtual drive is provided to the replacement drive. The replacement drive is assigned to the RAID group. The replacement drive appears to the RAID controller to be the failed drive. The virtual drive(s) are released.

A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

A plurality of failure domains are communicatively coupled to each other via a network, and each of the plurality of failure domains is coupled to one or more storage devices. A failure resilient stripe is distributed across the plurality of storage devices, such that two or more blocks of the failure resilient stripe are located in each failure domain.

The invention belongs to the technical field of data processing, and particularly discloses a memory chip ECC module adaptive verification method and device, and the method comprises the steps: perceiving the multi-source information of physics, environment and the like in real time through a multi-mode sensor array, generating a dynamic parameter fusion matrix, and analyzing the matrix data through a hybrid intelligent prediction model, prospectively predicting an error trend and generating a pre-selected error correction strategy; according to the prediction result and the environmental parameters, the storage array topology reconstruction is triggered to avoid the risk, and in combination with a digital twin model and a historical error pattern library, graded early warning is generated, the system risk is evaluated, and a differential response strategy is executed, so that the system can utilize system resources to the maximum extent while ensuring the security of core services; by using the block chain evidence storage and incremental federated learning technology, the verification system is endowed with reliable self-evolution ability, so that the whole verification system can adapt to a new threat mode and a continuously evolved application environment.

The invention discloses a traffic information real-time path planning system and method for vehicle-road cooperation. Comprising a vehicle-road cooperative perception and information fusion module, a vehicle-road cooperative communication and information interaction module, a dynamic traffic state analysis and prediction module, a multi-target real-time path planning module, a path dynamic correction and obstacle avoidance decision module and a vehicle control and execution feedback module. According to the method, vehicle-mounted and roadside data are fused through vehicle-road collaborative sensing, a non-line-of-sight blind area is covered, the limitation of single vehicle sensing is solved, and the integrity of environment information is improved; based on a short-term traffic prediction and real-time correction mechanism, path planning can be dynamically adjusted along with traffic state changes, and the problem that a planned path is disjointed from the reality is avoided.