71 results about "Solid state memory" patented technology

The embodiment of the invention provides a solid-state memory and a memory management method, and the solid-state memory comprises a computing interconnection interface, a nonvolatile memory interface controller, a cache controller, a dynamic random access memory, a flash memory controller and a flash memory medium, the dynamic random access memory comprises a controller memory buffer area and a plurality of persistent memory areas, and instructions and data can be separated through the controller memory buffer area and the persistent memory areas to realize effective isolation of the data and the instructions.

In solid state memory devices, garbage collection can be a bottleneck in meeting stringent performance requirements of certain hosts that generate a relatively-large amount of data (e.g., hosts that generate video data). With such hosts, the performance drop caused by background garbage collection can result in video recording failures. The memory device and method presented herein performs background operations in such a way as to enhance sustained performance. In general, a counter is maintained that reflects an amount of memory written to by a host, as well as an amount of memory freed by garbage collection operations. Each step of a garbage collection operation can be performed in response to a value of the counter being greater than a threshold for the step such that there is a balance between memory written and memory freed.

The embodiment of the invention provides a data reading method and device for a solid-state memory, a storage medium and electronic equipment, and the data reading method for the solid-state memory comprises the steps: obtaining a data reading instruction carrying data attribute information; wherein the data reading instruction is used for reading matched data matched with the data attribute information from a storage unit of the solid-state memory; reading matched data matched with the data attribute information from the storage unit based on a set initial reference voltage; carrying out correction processing on the matched data; and in the process of correcting the matched data, adjusting the initial reference voltage, reading the matched data matched with the data attribute information from the storage unit again based on the adjusted initial reference voltage, and correcting the reread matched data to obtain the corrected matched data. And stopping reading the matched data until a correction result obtained by performing correction processing on the matched data meets a data error rate condition. And the data reading efficiency is improved.

A bridge receives a first memory access command from a host computer, the first memory access command including an indication of one or more blocks of memory locations in a host memory of the host computer. The bridge device stores the first memory access command in a queue of the bridge device and determines one or more virtual addresses to be used by the solid state memory for the first memory access command. The bridge generates a second memory access command that is a revised copy of the first memory access command so that the indication of the one or more blocks of memory locations in the host memory is replaced with an indication of the one or more virtual addresses. The bridge sends the second memory access command to the solid state memory while keeping the first memory access command in the queue.

Disclosed are a solid-state memory, a medium module, a substrate assembly, a solid-state drive, and a storage system, which relate to the technical field of storage. In the solid-state memory, a controller module is detachably connected to the medium module, and when a connecting part in the controller module and a connecting part in the medium module are in a connected state, a controller can manage a storage medium in the medium module. When either the controller module or the medium module is damaged or fails, it is possible to only replace the damaged or failed module, and it is not necessary to replace the non-failed or non-damaged module, so that it is not necessary to replace the entire solid-state memory, and the replacement frequency is reduced, thereby facilitating a reduction in the usage cost of solid-state memories and also facilitating a reduction in the maintenance cost of hard drives including the solid-state memories.

The invention discloses a multi-track audio synthesis and processing method and system, and relates to the technical field of intelligent audio production, and the method comprises the steps: reading audio data from an SD NAND solid-state memory through an SDIO protocol, sending the data to a ring buffer, and carrying out the ECC mechanism for data verification and error correction; analyzing the audio data in the buffer area by using a deep learning algorithm, and dynamically distributing and managing a plurality of audio tracks; based on the synthesized and compressed audio data, fusing a neural network model to generate multi-track audio data; and returning the synthesized audio and carrying out further processing. By integrating efficient data management, intelligent audio processing driven by deep learning, context awareness editing, dynamic audio optimization and user feedback circulation, automation, individuation and high-quality standards of the whole process from data transmission to audio creation are realized, and the audio production efficiency and artistic expressive force are greatly improved.

The invention discloses a remote storage access method and device, a medium and equipment. The method comprises the following steps: a computing server sends a remote memory access request through an internet access; the remote memory access request reaches the network switch through the network link; the network switch sends the remote memory access request to a specified storage server; and the storage server bypasses a central processing unit of the storage server to directly read and write the solid-state memory according to the remote memory access request.

A storage system has zones in solid-state storage memory, with power loss protection. The system identifies portions of data for processes that utilize power loss protection. The system determines to activate or deactivate power loss protection for the portions of data for the processes. The system tracks activation and deactivation of power loss protection in zones in the solid-state storage memory, in accordance with the portions of data having power loss protection activated or deactivated.

The invention relates to the field of electric digital data processing, and provides an electric vehicle charging and discharging safety monitoring and tracing method and device and a computer storage medium. The method comprises the following steps: collecting multi-dimensional dynamic parameters of a charging and discharging process in real time and detecting and recording control instruction interaction data between the electric vehicle and charging and discharging equipment through a composite sensor array deployed on the electric vehicle and the charging and discharging equipment; performing timestamp alignment and protocol analysis on the acquired multi-dimensional dynamic parameters and control instruction interaction data to form a data sequence with a unified time sequence; a self-adaptive multi-layer data compression technology is adopted to compress a data sequence with a unified time sequence, and then the compressed data sequence is synchronously written into a local solid-state memory and a cloud server for double-backup encrypted storage; and performing online fault analysis based on the encrypted and stored data sequence. According to the technical scheme, multi-source data fusion intelligent monitoring and accurate traceability of the whole charging and discharging process of the electric vehicle can be achieved.

The invention discloses a solid-state memory, a medium module, a substrate assembly, a solid-state disk and a storage system, and relates to the technical field of storage. A controller module and a medium module in the solid-state memory are detachably connected, and when a connecting part in the controller module and a connecting part in the medium module are in a connected state, a controller can manage a storage medium in the medium module. When one of the controller module or the medium module is damaged or invalid, only the damaged or invalid module can be replaced, the non-invalid and non-damaged module does not need to be replaced, the solid-state memory does not need to be integrally replaced, the replacement frequency is reduced, and the replacement efficiency is improved. The use cost of the solid-state memory is reduced, and the maintenance cost of the hard disk comprising the solid-state memory is also reduced.

The application discloses a kind of support in-orbit program reconfiguration's satellite-borne solid-state memory, belong to electronic information field.Satellite-borne solid-state memory includes control core, data storage array, cache unit, refresh loading circuit, interface unit, program storage unit, control core realizes the control of storage array, parse host computer instruction, bad block management, wear leveling and address management, cache unit effectively prevents single event upset error.Storage array avoids the timing violation of FPGA that can appear under high main frequency and other difficult problems.Load refresh circuit uses refresh loading circuit to refresh FPGA internal program regularly, reduces the influence of single event upset.Interface unit realizes the control management of host computer to satellite-borne solid-state memory.Program storage unit selects storage carrier according to function, storage capacity size, read-write bandwidth requirement.The whole hardware design is with FPGA soft core to realize the control management function of satellite-borne solid-state memory, and special CPU hardware does not have to be designed.

A solid state storage system includes a pressure-sealed storage unit defining an interior and having an outlet, an upper manifold and a lower manifold separated by a dividing plane having a set of ports, a set of chambers, and a solid state storage, wherein at least some gas is supplied to the outlet.

The invention provides an equipment debugging method and system based on an FPGA serial interface. The method comprises the steps that first data output by the output end of a computer host is analyzed through a first serial interface analysis device and then enters an information scheduling device; under the condition that the first data does not meet the interface protocol content in the external solid-state memory, a fixed serial port protocol of the information scheduling device changes the interface protocol content; under the condition that the first data meets the interface protocol content, the first information data analysis unit caches the first data into a first data cache unit; and after the first data is received, the information scheduling device takes out the first data in the first data cache unit and sends the first data of the corresponding type of interface protocol to the sub-equipment so as to debug the sub-equipment. According to the invention, a computer universal serial interface is converted into a specified serial interface, and equipment debugging of a computer serial interface protocol and various test interactive interface protocols is completed.

A method of applying a data format in a direct memory access transfer is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis that couples the storage nodes as a cluster, each of the plurality of storage nodes having nonvolatile solid-state memory for user data storage. The method includes reading a self-describing data portion from a first memory of the nonvolatile solid-state memory and extracting a destination from the self-describing data portion. The method includes writing data, from the self-describing data portion, to a second memory of the nonvolatile solid-state memory according to the destination.

In solid state memory devices, garbage collection can be a bottleneck in meeting stringent performance requirements of certain hosts that generate a relatively-large amount of data (e.g., hosts that generate video data). With such hosts, the performance drop caused by background garbage collection can result in video recording failures. The memory device and method presented herein performs background operations in such a way as to enhance sustained performance. In general, a counter is maintained that reflects an amount of memory written to by a host, as well as an amount of memory freed by garbage collection operations. Each step of a garbage collection operation can be performed in response to a value of the counter being greater than a threshold for the step such that there is a balance between memory written and memory freed.

The invention discloses an electronic equipment maintenance management system and management method, and relates to the technical field of electronic equipment maintenance management, the system comprises an analysis module used for analyzing the decline degree of storage performance based on historical write-in frequency data of a solid-state memory, and a parameter determination module used for determining parameters of the solid-state memory according to the decline degree of the storage performance. The control module is used for determining control parameters of a garbage collection mechanism, the control module is used for applying the control parameters to garbage collection operation of the solid-state memory so as to optimize storage performance, and the recording module is used for recording optimized storage performance data and taking the optimized storage performance data as an input basis for subsequent analysis; according to the electronic equipment maintenance management system and management method, the garbage collection mechanism is regulated and controlled according to the write-in frequency of the solid-state memory, so that the problem of storage performance degradation caused by long-term use is solved.

The application relates to the technical field of solid-state memory data processing, and discloses a solid-state memory data processing method and system. The method comprises the following steps: collecting a real-time operation sequence, performing semantic analysis on the operation sequence, and obtaining an operation semantic representation; performing statistical analysis and priority sorting according to the operation semantic representation, and obtaining a hierarchical task queue; dynamically adjusting a storage resource of the hierarchical task queue, and obtaining a resource distribution structure; determining a potential resource bottleneck position according to the resource distribution structure, and obtaining a storage space mapping; determining a data access channel according to the storage space mapping; detecting multi-thread conflicts in the data access channel and adjusting the multi-thread conflicts, and obtaining a response time distribution; dynamically updating semantic parameters and limiting an adjustment range according to the response time distribution, and obtaining a data processing instruction. The method can solve the problem that the overall system performance bottleneck is prominent under a complex dynamic workload in the prior art.

The invention discloses a satellite-borne solid-state memory capable of performing instruction control, and belongs to the field of space navigation data storage. The memory comprises a bad block management module, a file management module, a FLASH control module, a framing module, a cache module and a remote control and telemetering module which are combined to complete two working functions of the memory, namely a storage function and a data processing function. According to the storage function, a storage capacity configuration scheme controlled by an instruction is adopted, and when a storage unit or a storage chip in the satellite-borne solid-state storage is damaged or a satellite is in a special working condition, and the number of storage power sources or storage chips in the storage has a special requirement, the storage capacity configuration scheme is controlled by the instruction. And eliminating a certain storage unit and a certain storage chip through a storage unit reconstruction instruction. Storage capacity configuration controlled by instructions is achieved, and reliability and flexibility of the system are improved.

The application relates to the technical field of data storage, and discloses a data storage integrity verification method and system for a solid-state memory. The method comprises the following steps: collecting read-write instructions, programming and erasing cycle times, and charge retention times; performing voltage drift analysis based on the read-write instructions to obtain drift grouping data, and counting flip frequency distribution; performing storage block degradation analysis by combining the flip frequency distribution, the programming and erasing cycle times, and the charge retention times, to obtain a high-risk area; extracting a risk voltage drift amount, counting read-write interference amounts, and combining the risk voltage drift amount and the read-write interference amounts into an error feature vector; identifying a hard error type through a support vector machine model; performing reliability determination based on the hard error type and the flip frequency distribution, generating a check trigger signal, and positioning an accurate bit flip address; combining a data importance degree library to evaluate a repair priority sequence; performing data repair, periodically checking a repaired successful area, and obtaining an integrity verification report. The method improves the reliability of a storage system.

A method of applying a data format in a direct memory access transfer is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis that couples the storage nodes as a cluster, each of the plurality of storage nodes having nonvolatile solid-state memory for user data storage. The method includes reading a self-describing data portion from a first memory of the nonvolatile solid-state memory and extracting a destination from the self-describing data portion. The method includes writing data, from the self-describing data portion, to a second memory of the nonvolatile solid-state memory according to the destination.

The application belongs to the technical field of satellite data transmission, and provides a kind of on-board solid-state memory read-write rate dynamic allocation design device and method thereof, including storage module, high-capacity high-speed DDR and FPGA for storing read-write control;High-capacity high-speed DDR cooperates with read-write control FPGA, according to the rate of load writing into storage module, and the priority sorting processing strategy of read-write cache data stream, dynamically controls the read-write of storage module.This application realizes the current data writing while reading under the high peak rate of satellite load, and also can realize non-overflow real-time data processing and transmission to the earth under the high-speed condition of writing rate close to throughput rate;Through the priority sorting processing strategy of read-write cache data stream, ensure that the load data of high peak rate is completely written into the storage module, and realize dynamic allocation of read rate resource according to the remaining processing capacity of throughput rate.

A segment height corresponding to a least common multiple (LCM) of at least two different erase block sizes of solid-state storage devices is selected. A determination as to whether the LCM exceeds a segment height threshold is made. In response to determining that the LCM exceeds the segment height threshold, one or more calculations are performed to determine corresponding pinned space values for different segment heights. A particular segment height from the different segment heights is selected based on the corresponding pinned space values.

The invention provides an airborne high-speed image storage control method and system based on an FPGA, and relates to the technical field of aeronautical data chain transmission, the transmission capability of a downlink between an aircraft and a ground station is monitored through the FPGA, image data to be transmitted are dynamically adjusted according to the transmission capability, and the image data are divided into key frames and non-key frames; the data are respectively stored in a ferroelectric memory and a solid-state memory; when the power supply is abnormal, starting a protection program to convert the key frame into a persistent format, and preferentially transmitting the key frame when the bandwidth is sufficient; meanwhile, non-key frame selective retransmission is started when the link state is continuously improved, complete and reliable transmission of airborne image data under an unstable link is achieved in combination with link self-adaptive adjustment, and through a collaborative mechanism of key frame protection and priority transmission, non-key frame self-adaptive retransmission and link state dynamic scheduling, the transmission efficiency of the airborne image data under the unstable link can be improved. And the integrity and reliability of image data transmission in a complex airborne environment are ensured.

The invention provides a spaceborne intelligent image data processing platform based on a spacecraft operating system. The spaceborne intelligent image data processing platform comprises a spaceborne high-performance CPU processor, a high-performance DSP processor, an FPGA processor, a high-density integrated solid-state memory and a spaceborne operating system. And the high-performance DSP processor, the FPGA processor and the high-density integrated solid-state memory are all connected with the satellite-borne high-performance CPU. The satellite-borne operating system is used for uniformly managing data of the intelligent data processing platform, and multiple APP programs run in the environment of the satellite-borne operating system. According to the invention, the on-satellite data processing capability, especially the image processing capability, of the satellite is remarkably improved, the satellite optical remote sensing data processing performed on the satellite in a preposed manner is enabled to have higher flexibility by configuring the intelligent image data processing APP, and only the processed effective information is downloaded through the satellite-ground data transmission channel, so that the data processing efficiency is improved. Therefore, the processing and application efficiency of the satellite data is effectively improved.

A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

The invention discloses a method for processing data loss caused by frequency offset in request-system satellite data transmission, and belongs to the technical field of satellite communication. The two-channel modulator of the dual-channel request system satellite respectively sends request frames to the data processor, and the request frames are combined and then output to the solid-state memory; the solid-state memory sends playback data of a corresponding data frame number of a single path to the data processor according to the frame number of the received request frames; the data processor averagely divides the received single-path playback data into two paths, respectively performs data processing, and generates a full identification signal; after data processing is completed, the data are output to a two-channel modulator according to the number of request frames of the path; when the full identification signal of any one of the two channels is 1, request frame combination is stopped, and at the moment, the solid-state memory pauses data playback. By detecting the capacity of the cached data in the caches in the two coding processing units in real time, the problem of data loss caused by frequency offset of a modulator clock crystal oscillator in satellite request system data transmission is reliably solved in real time.

An extension portion of a solid state memory device printed circuit board provides additional ground shielding. In one example, the printed circuit board includes a main body and a connector contact portion at a first end of the main body. The connector contact portion includes pins and an extension portion that provides ground shielding to the pins. Ground pins may be connected to the extension portion by through hole vias. The connector contact portion may be connected to an SFF-8639 port.

This application discloses a primary-backup fault-tolerant storage architecture for spaceborne computers, relating to the field of spaceborne solid-state memory technology. It includes a physical storage module and a fault-tolerant management module. The physical storage module comprises: a primary boot partition for storing the computer system's bootloader; a primary system root partition for storing system files; a backup partition comprising three independent sub-storage areas—a first sub-storage area, a second sub-storage area, and a third sub-storage area—each storing a mirrored data packet formed by combining data from the primary boot partition and data from the primary system root partition; and a data partition for storing user data. This architecture enables the primary boot partition and primary system root partition to operate in single-copy mode during normal task execution, completely avoiding the additional latency, bandwidth consumption, and CPU overhead caused by real-time data synchronization and online voting, thereby maximizing the core performance and efficiency of spaceborne task processing.

The invention discloses a solid-state memory, a medium module, a substrate assembly, a solid-state disk and a storage system, and relates to the technical field of storage. A controller module and a medium module in the solid-state memory are detachably connected, and when a connecting part in the controller module and a connecting part in the medium module are in a connected state, a controller can manage a storage medium in the medium module. When one of the controller module or the medium module is damaged or invalid, only the damaged or invalid module can be replaced, the non-invalid and non-damaged module does not need to be replaced, the solid-state memory does not need to be integrally replaced, the replacement frequency is reduced, and the replacement efficiency is improved. The use cost of the solid-state memory is reduced, and the maintenance cost of the hard disk comprising the solid-state memory is also reduced.

The invention relates to a digital regeneration-based static orbit satellite broadcast forwarding system, which is characterized in that a demodulation receiver receives uplink data of a ground station through a receiving antenna, completes data demodulation and transmits the data to a rear-end data processor; the data processor judges whether the uplink data needs to be fused with the real-time remote sensing data or not according to the identifier of the uplink data, and if the uplink data is the data needing to be fused, fusion processing of the uplink data and the remote sensing data is completed in the data processor; if the uplink data does not need to be fused, directly storing the uplink data into the solid-state memory; reading broadcast distribution data from the solid-state memory, and forwarding the broadcast distribution data to the broadcast modulator through the data processor; the broadcast modulator encodes and modulates broadcast downlink data into a radio frequency signal, and the radio frequency signal is broadcast and distributed to a designated area through the transmitting antenna after being subjected to filtering and power amplification. And the use efficiency of broadcast distribution of the geostationary orbit remote sensing satellite is effectively expanded.