28 results about "Solid state memory" patented technology

A bridge receives a first memory access command from a host computer, the first memory access command including an indication of one or more blocks of memory locations in a host memory of the host computer. The bridge device stores the first memory access command in a queue of the bridge device and determines one or more virtual addresses to be used by the solid state memory for the first memory access command. The bridge generates a second memory access command that is a revised copy of the first memory access command so that the indication of the one or more blocks of memory locations in the host memory is replaced with an indication of the one or more virtual addresses. The bridge sends the second memory access command to the solid state memory while keeping the first memory access command in the queue.

A storage system has zones in solid-state storage memory, with power loss protection. The system identifies portions of data for processes that utilize power loss protection. The system determines to activate or deactivate power loss protection for the portions of data for the processes. The system tracks activation and deactivation of power loss protection in zones in the solid-state storage memory, in accordance with the portions of data having power loss protection activated or deactivated.

The invention relates to the field of electric digital data processing, and provides an electric vehicle charging and discharging safety monitoring and tracing method and device and a computer storage medium. The method comprises the following steps: collecting multi-dimensional dynamic parameters of a charging and discharging process in real time and detecting and recording control instruction interaction data between the electric vehicle and charging and discharging equipment through a composite sensor array deployed on the electric vehicle and the charging and discharging equipment; performing timestamp alignment and protocol analysis on the acquired multi-dimensional dynamic parameters and control instruction interaction data to form a data sequence with a unified time sequence; a self-adaptive multi-layer data compression technology is adopted to compress a data sequence with a unified time sequence, and then the compressed data sequence is synchronously written into a local solid-state memory and a cloud server for double-backup encrypted storage; and performing online fault analysis based on the encrypted and stored data sequence. According to the technical scheme, multi-source data fusion intelligent monitoring and accurate traceability of the whole charging and discharging process of the electric vehicle can be achieved.

The application discloses a kind of support in-orbit program reconfiguration's satellite-borne solid-state memory, belong to electronic information field.Satellite-borne solid-state memory includes control core, data storage array, cache unit, refresh loading circuit, interface unit, program storage unit, control core realizes the control of storage array, parse host computer instruction, bad block management, wear leveling and address management, cache unit effectively prevents single event upset error.Storage array avoids the timing violation of FPGA that can appear under high main frequency and other difficult problems.Load refresh circuit uses refresh loading circuit to refresh FPGA internal program regularly, reduces the influence of single event upset.Interface unit realizes the control management of host computer to satellite-borne solid-state memory.Program storage unit selects storage carrier according to function, storage capacity size, read-write bandwidth requirement.The whole hardware design is with FPGA soft core to realize the control management function of satellite-borne solid-state memory, and special CPU hardware does not have to be designed.

A method of applying a data format in a direct memory access transfer is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis that couples the storage nodes as a cluster, each of the plurality of storage nodes having nonvolatile solid-state memory for user data storage. The method includes reading a self-describing data portion from a first memory of the nonvolatile solid-state memory and extracting a destination from the self-describing data portion. The method includes writing data, from the self-describing data portion, to a second memory of the nonvolatile solid-state memory according to the destination.

The application relates to the technical field of solid-state memory data processing, and discloses a solid-state memory data processing method and system. The method comprises the following steps: collecting a real-time operation sequence, performing semantic analysis on the operation sequence, and obtaining an operation semantic representation; performing statistical analysis and priority sorting according to the operation semantic representation, and obtaining a hierarchical task queue; dynamically adjusting a storage resource of the hierarchical task queue, and obtaining a resource distribution structure; determining a potential resource bottleneck position according to the resource distribution structure, and obtaining a storage space mapping; determining a data access channel according to the storage space mapping; detecting multi-thread conflicts in the data access channel and adjusting the multi-thread conflicts, and obtaining a response time distribution; dynamically updating semantic parameters and limiting an adjustment range according to the response time distribution, and obtaining a data processing instruction. The method can solve the problem that the overall system performance bottleneck is prominent under a complex dynamic workload in the prior art.

The invention discloses a satellite-borne solid-state memory capable of performing instruction control, and belongs to the field of space navigation data storage. The memory comprises a bad block management module, a file management module, a FLASH control module, a framing module, a cache module and a remote control and telemetering module which are combined to complete two working functions of the memory, namely a storage function and a data processing function. According to the storage function, a storage capacity configuration scheme controlled by an instruction is adopted, and when a storage unit or a storage chip in the satellite-borne solid-state storage is damaged or a satellite is in a special working condition, and the number of storage power sources or storage chips in the storage has a special requirement, the storage capacity configuration scheme is controlled by the instruction. And eliminating a certain storage unit and a certain storage chip through a storage unit reconstruction instruction. Storage capacity configuration controlled by instructions is achieved, and reliability and flexibility of the system are improved.

The application relates to the technical field of data storage, and discloses a data storage integrity verification method and system for a solid-state memory. The method comprises the following steps: collecting read-write instructions, programming and erasing cycle times, and charge retention times; performing voltage drift analysis based on the read-write instructions to obtain drift grouping data, and counting flip frequency distribution; performing storage block degradation analysis by combining the flip frequency distribution, the programming and erasing cycle times, and the charge retention times, to obtain a high-risk area; extracting a risk voltage drift amount, counting read-write interference amounts, and combining the risk voltage drift amount and the read-write interference amounts into an error feature vector; identifying a hard error type through a support vector machine model; performing reliability determination based on the hard error type and the flip frequency distribution, generating a check trigger signal, and positioning an accurate bit flip address; combining a data importance degree library to evaluate a repair priority sequence; performing data repair, periodically checking a repaired successful area, and obtaining an integrity verification report. The method improves the reliability of a storage system.

A segment height corresponding to a least common multiple (LCM) of at least two different erase block sizes of solid-state storage devices is selected. A determination as to whether the LCM exceeds a segment height threshold is made. In response to determining that the LCM exceeds the segment height threshold, one or more calculations are performed to determine corresponding pinned space values for different segment heights. A particular segment height from the different segment heights is selected based on the corresponding pinned space values.

The invention provides an airborne high-speed image storage control method and system based on an FPGA, and relates to the technical field of aeronautical data chain transmission, the transmission capability of a downlink between an aircraft and a ground station is monitored through the FPGA, image data to be transmitted are dynamically adjusted according to the transmission capability, and the image data are divided into key frames and non-key frames; the data are respectively stored in a ferroelectric memory and a solid-state memory; when the power supply is abnormal, starting a protection program to convert the key frame into a persistent format, and preferentially transmitting the key frame when the bandwidth is sufficient; meanwhile, non-key frame selective retransmission is started when the link state is continuously improved, complete and reliable transmission of airborne image data under an unstable link is achieved in combination with link self-adaptive adjustment, and through a collaborative mechanism of key frame protection and priority transmission, non-key frame self-adaptive retransmission and link state dynamic scheduling, the transmission efficiency of the airborne image data under the unstable link can be improved. And the integrity and reliability of image data transmission in a complex airborne environment are ensured.

An extension portion of a solid state memory device printed circuit board provides additional ground shielding. In one example, the printed circuit board includes a main body and a connector contact portion at a first end of the main body. The connector contact portion includes pins and an extension portion that provides ground shielding to the pins. Ground pins may be connected to the extension portion by through hole vias. The connector contact portion may be connected to an SFF-8639 port.

This application discloses a primary-backup fault-tolerant storage architecture for spaceborne computers, relating to the field of spaceborne solid-state memory technology. It includes a physical storage module and a fault-tolerant management module. The physical storage module comprises: a primary boot partition for storing the computer system's bootloader; a primary system root partition for storing system files; a backup partition comprising three independent sub-storage areas—a first sub-storage area, a second sub-storage area, and a third sub-storage area—each storing a mirrored data packet formed by combining data from the primary boot partition and data from the primary system root partition; and a data partition for storing user data. This architecture enables the primary boot partition and primary system root partition to operate in single-copy mode during normal task execution, completely avoiding the additional latency, bandwidth consumption, and CPU overhead caused by real-time data synchronization and online voting, thereby maximizing the core performance and efficiency of spaceborne task processing.

The invention relates to a digital regeneration-based static orbit satellite broadcast forwarding system, which is characterized in that a demodulation receiver receives uplink data of a ground station through a receiving antenna, completes data demodulation and transmits the data to a rear-end data processor; the data processor judges whether the uplink data needs to be fused with the real-time remote sensing data or not according to the identifier of the uplink data, and if the uplink data is the data needing to be fused, fusion processing of the uplink data and the remote sensing data is completed in the data processor; if the uplink data does not need to be fused, directly storing the uplink data into the solid-state memory; reading broadcast distribution data from the solid-state memory, and forwarding the broadcast distribution data to the broadcast modulator through the data processor; the broadcast modulator encodes and modulates broadcast downlink data into a radio frequency signal, and the radio frequency signal is broadcast and distributed to a designated area through the transmitting antenna after being subjected to filtering and power amplification. And the use efficiency of broadcast distribution of the geostationary orbit remote sensing satellite is effectively expanded.

The application provides a long-term working satellite-borne solid-state memory data stream management method, which encodes data received from an interface, covers the whole data stream from DDR to FLASH, protects data outside the FLASH link, and further improves the data reliability of the long-term working satellite-borne solid-state memory; the RS encoding and twice data interleaving encoding are combined, the RS encoding parameter is selected according to the number of FLASH chips, the fixed bytes in the code group exist in the fixed physical space of the FLASH chips, the fault position can be accurately located according to the abnormal data distribution law when the data is abnormal due to the FLASH chip failure; the RS encoding is combined with twice data interleaving, the code words in the same RS code group are distributed in different physical spaces, when the FLASH chip fails, a large amount of data abnormality caused by the centralized storage of the data in the same physical space can be avoided, and the error code number can be corrected within the error correction capability of the RS encoding.

The invention discloses a method for improving the capacity and performance of a modular mobile solid-state memory, and relates to the field of mobile storage, and the method comprises the steps: in a data collection scene, closing an SLC cache, reducing an OP space, and setting a flash memory to be in a'capacity mode '; in a data distribution scene, an SLC cache is closed, a passive GC mode is started, and a flash memory is set to be in a stable write mode; in a data sharing editing scene, an SLC cache is added, an active GC mode is started, and a flash memory is set to be in a hotspot read-write performance mode. The working mode is flexibly adjusted according to different application scenes, and the available capacity and the stable performance of the modular mobile solid-state memory can be effectively improved.

The application relates to a log management method, device, system, equipment and storage medium, wherein a current driving scene label of an automatic driving system is first determined; then, in response to the current driving scene label, a target scene template corresponding to the current driving scene label is matched from a pre-defined scene template library; then, adaptive layout reconstruction is performed on a memory pool of a log according to the target scene template; in a log recording process, an operating system kernel IO stack is bypassed, an NVMe command is constructed through a user state drive, and log data is written into an NVMe solid state memory through a high-speed bus. The application can realize deterministic log disk landing and scene adaptive memory management.

The invention relates to the field of solid-state storage, in particular to a back-end loopback test method for a solid-state storage. According to the method, the implementation of the loopback test interface is separated from the main business logic of the upper layer, so that the normal firmware operation mode can be switched to the loopback test mode only by properly modifying the initialization step and replacing the callback function of the related register operation of the flash memory controller on the basis of reserving the back-end processing flow architecture; the reusability and compatibility of codes are improved, and the code maintenance difficulty and cost in the subsequent firmware development process are reduced. A round-robin queue and a bitmap mapping table which are realized by software are used as containers for simulating idle, trigger and completion of register behaviors of a flash memory controller, the time for calling the operation interfaces is fixed and predictable, and the upper limit of the computing power of a CPU (Central Processing Unit) in an SSD (Solid State Disk) main control chip can be estimated, so that a relatively strong guiding effect is achieved on analysis and improvement of performance indexes such as 4K random read command IOPS (Input / Output Operations Per Second) and the like.

The utility model discloses an image data analysis and storage system, which comprises an image input interface, a feature extraction module, a decision module, a data buffer module and a storage control module, the image input interface is connected with the video processor of the feature extraction module; the feature extraction module extracts image features through a feature detection circuit based on a comparator, and generates a control signal through the decision module; and the control signal controls an address decoder in the storage control module, so that a data stream is automatically guided to a solid-state memory or a disk memory through a data gating switch. According to the utility model, analysis and shunt storage of image data are realized through a hardware circuit, and the system has the advantages of determined delay, high efficiency and no need of software intervention.

The embodiments provide for a method and system for dynamic configuration of a storage system to facilitate independent scaling of resources. The method and system include detecting a change to a topology of a storage system consisting of different sets of storage nodes, where at least one of the different sets of storage nodes has solid-state memory having differing storage capacities. Responsive to detecting the change, the storage system reconfigures to change an allocation of resources to one or more authorities that control a range of identifiers.

The invention relates to the technical field of solid-state storage and data security, and discloses a data security verification method and system for a solid-state memory, and the method comprises the steps: obtaining an access frequency statistical value and a read-write operation counter, carrying out grouping processing, and determining a high-frequency data group and a low-frequency data group; according to the high-frequency data set, data priority analysis is carried out, and a fine protection configuration item is generated; according to the fine protection configuration item, generating a protection strength improvement parameter, and determining a resource allocation optimization path; according to the resource allocation optimization path, evaluating calculation overhead, and determining a protection granularity adjustment strategy of the low-frequency data set; and based on the resource allocation optimization path and the protection granularity adjustment strategy, generating and applying balanced resource distribution configuration. According to the method, the protection intensity of the high-frequency data and the resource overhead of the low-frequency data are dynamically balanced, so that the problems of unbalanced protection resource distribution and overhigh calculation overhead in the prior art are solved.

This application discloses a fault-tolerant storage architecture for spaceborne computers based on multi-disk cross-backup, relating to the field of spaceborne solid-state memory technology. It includes a fault-tolerant management module, a switching middleware, and at least two physical storage modules. The first physical storage module and the second physical storage module have the same partition structure. The first physical storage module backs up and stores a first image data formed by combining local EFI partition data and local Root partition data, and a second image data formed by combining EFI partition data and Root partition data from the second physical storage module. The second physical storage module backs up and stores both the first and second image data. The input terminal of the switching middleware is electrically connected to the fault-tolerant management module, and its output terminal is electrically connected to at least two of the physical storage modules, respectively. This middleware is used to switch the boot channel to the corresponding physical storage module in response to instructions issued by the fault-tolerant management module, fundamentally solving the problem of system paralysis caused by overall device failure in single-disk architectures.

An approach is provided for protecting data stored by a non-volatile solid-state memory from an unauthorized access. In response to a trigger event indicating an increased probability of the unauthorized access, the memory is destroyed by directing through the memory an electric current exceeding a rated current of the memory, and testing an operability of the memory, where the destruction is completed when the test indicates lacking operability of the memory.

The invention provides a data stream management method for a long-term working satellite-borne solid-state memory, which comprises the following steps of: receiving data from an interface, coding, covering the whole data stream from DDR (Double Data Rate) to FLASH, protecting data except a FLASH link, and further improving the data reliability of the long-term working satellite-borne solid-state memory; rS coding and two-time data interleaving coding are combined, RS coding parameter selection is determined according to the number of FLASH chips, it is guaranteed that fixed bytes in a code block exist in a fixed physical space of the FLASH chips, and when data abnormity is caused by FLASH chip faults, the fault position can be accurately located according to the abnormal data distribution rule; after RS coding, two times of data interleaving are combined, it is guaranteed that code words in the same RS code block are distributed in different physical spaces, when a FLASH chip breaks down, it can be avoided that when data are stored in the same physical space in a concentrated mode, a large amount of data is abnormal, and the number of error codes can be corrected within the RS coding error correction capacity.

A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.

The invention relates to the technical field of solid-state memory data processing, and discloses a solid-state memory data processing method and system.The method comprises the steps that a real-time operation sequence is collected and subjected to semantic analysis, and operation semantic representation is obtained; performing statistical analysis and priority ranking according to the operation semantic representation to obtain a hierarchical task queue; dynamically adjusting storage resources of the hierarchical task queue to obtain a resource distribution structure; determining a potential resource bottleneck position according to the resource distribution structure to obtain storage space mapping; determining a data access channel according to the storage space mapping; detecting a multi-thread conflict in the data access channel and adjusting the multi-thread conflict to obtain response time distribution; according to the response time distribution, semantic parameters are dynamically updated, the adjustment amplitude is limited, and a data processing instruction is obtained. The method can solve the problem that the bottleneck of the overall performance of the system is prominent under the complex dynamic working load in the prior art.

A storage system has zones in solid-state storage memory, with power loss protection. The system identifies portions of data for processes that utilize power loss protection. The system determines to activate or deactivate power loss protection for the portions of data for the processes. The system tracks activation and deactivation of power loss protection in zones in the solid-state storage memory, in accordance with the portions of data having power loss protection activated or deactivated.

The invention relates to the technical field of space navigation data storage, and discloses a space-borne solid-state memory control method and system based on dynamic power consumption management, and the method comprises the steps: receiving external load data and an instruction, and generating a partition instruction according to the instruction and the operation state of each storage partition in a storage module; controlling power-on, power-off, data storage, data playback or data erasing operation of the corresponding storage partitions through the partition instructions; in the data storage or playback process, a pre-starting mechanism is triggered according to the use state of the current storage partition, and power-on preparation is conducted on the next storage partition in advance; running state information of each storage partition is collected, and overall telemetering is generated and output; meanwhile, the invention provides a satellite-borne solid-state memory architecture to realize the method, the whole memory architecture is divided into a plurality of parallel storage partitions, and the storage partitions are used as minimum action storage scheduling units to dynamically match the actual use condition, so that the power consumption is reduced.

This invention discloses a controller with an FPGA chip and its operating method, as well as rail transit equipment. It relates to the field of rail transit on-board equipment technology. The controller with an FPGA chip includes: a DSP chip, an FPGA chip, a solid-state memory (SSD), and a dynamic memory (DRAM). The DSP chip and DRAM are communicatively connected, and the I / O pins of the DSP chip are electrically connected to the PROB pin of the FPGA chip. The SSD includes FLASH memory. The DSP chip and FPGA chip are electrically connected to the SSD via SPI or QSPI interfaces, respectively. The DSP chip also has a data input interface. The DSP chip receives programs through the data input interface and stores the programs in the DRAM, and also controls the potential of the PROB pin of the FPGA chip. The DSP chip writes the program from the DRAM into the SSD when the PROB pin of the FPGA chip is at a low potential; etc. This application enables remote updating of the FPGA program and decoupled startup of the FPGA and DSP.