178 results about "Massively parallel" patented technology

The invention discloses a large model calculation acceleration chip architecture, and relates to the field of large models. Comprising a normalized network-on-chip, an interconnection transmission system, a storage control system and a calculation acceleration core, the storage control system is connected with the Memory video memory group and the external SSD memory based on different built-in storage controllers; the normalized network-on-chip reads on-chip model parameters of a target position based on the storage control system, sends the on-chip model parameters to the calculation acceleration core for calculation, restores on-chip model data, carries out off-chip interaction with an external management server based on the interconnection transmission system, receives an instruction task, reads and restores external model parameters, and sends the external model parameters to the calculation acceleration core for calculation. And performing inter-chip interaction with other computing acceleration chips based on an interconnection transmission system, and reading and restoring inter-chip model parameters. According to the scheme, the hybrid video memory computing chip architecture supports multi-parallel SSD direct connection access, the capacity is expanded at low cost under the condition of keeping the bandwidth, and high cost performance is kept for both large-scale parallel tasks and small-sized low-cost all-in-one machines.

Vectorization requests are received via active connections for a hybrid time-series vector database that include input including information associated with an event and temporal information. The inputs are processed with a machine-learned vector embedding model to generate vector representations. The vector representations are mapped to corresponding locations within an embedding portion of the hybrid time-series vector database. A query is received for the hybrid time-series vector database via an active connection of the plurality of active connections. Responsive to the query, a first vector representation is retrieved based at least in part on the location to which the first vector representation is mapped.

Disclosed are various approaches for bit-serial computing embedded in the DRAM subarray, leveraging the massive parallelism of DRAM row operations. The present disclosure discloses digital techniques that can outperform analog charge-sharing techniques. Digital techniques can use more area but support a wider range of computing primitives, and allow a sequence of logic operations to be performed at higher clock speeds, be-tween slower subarray row reads / writes. The present disclosure describes a range of bit-serial architectures, and evaluate raw performance as well as area and energy efficiency. Results show that the digital architecture demonstrates 20× speedup over CPU, 5× over GPU, and 1.7× over SIMDRAM, an analog architecture.

The invention discloses an intelligent water operation management and control system based on the Internet of Things, and relates to the technical field of industrial Internet of Things crossing, and the system comprises the steps: collecting multi-dimensional operation data in a water supply network, carrying out the preliminary time mark alignment and preprocessing, and generating a multi-source synchronous perception data set; importing the comprehensive risk list into a digital twinborn body, dynamically injecting corresponding fault and abnormal scene parameters in a digital twinborn environment, and performing large-scale parallel deduction through a Monte Carlo simulation algorithm to generate a rehearsal consequence data set; and carrying out multi-objective decision analysis on the rehearsal consequence data set, carrying out prediction comprehensive plan utility scoring based on a preset safety weight and an economic weight, and calculating an optimized management and control plan through iterative optimization. According to the invention, the multi-source heterogeneous data is deeply fused through the graph neural network of the risk identification module, the dynamic impedance characteristics of the pipe network are accurately extracted, the early abnormality is identified, and advanced diagnosis of the multi-modal coupling risk is realized.

In order to enable applications such as artificial intelligence (AI) and machine learning in a large scale, a large amount of information needs to be processed very fast. To improve the speed of the computation, not only faster graphical and central processors are required, but also the communication between processors and high bandwidth memories should be fast enough to reduce the latency. Optical interconnect can be a replacement for copper interconnect which is providing larger bandwidth and lower latency. As an efficient light source, micro-LEDs can be used as light source for chip-to-chip optical interconnect. Using a massively parallel memory-processor interconnect using low-power micro-LED, the computation speed will increase dramatically, and less amount of energy will be wasted through copper self-heating.

The invention discloses an inspection data processing method and system, relates to the technical field of data processing, and ensures the accuracy and stability of authentication scheduling in a multi-interface cluster environment by responding to concurrent tasks and dynamically selecting authentication tokens according to interface features. The acquisition request is constructed based on the interface characteristics, so that the adaptive access to the heterogeneous interface path is realized, and the compatibility of large-scale parallel acquisition is guaranteed; by uniformly converting original data into a structured format and carrying out anomaly detection and linked list storage, the problems that multi-source heterogeneous data is difficult to process and an abnormal state is difficult to systematically track are solved; and finally, a standardized report is automatically generated according to a preset rule, and accurate marking of abnormal information is realized, so that full-process automation from data acquisition to report output is completed, and the reliability, the processing efficiency and the intelligent level of inspection operation are remarkably improved.

The invention relates to deep learning large-scale model parallel training communication optimization, in particular to a large-scale parallel communication optimization method based on lossy compression, and the method comprises the steps: dividing original data into N * N pieces of block data; each process receives the block data from the previous process in a non-blocking manner, compresses the block data received in the previous round of the process based on an SZX algorithm, sends the compressed block data to the next process in a non-blocking manner, decompresses the received block data and performs protocol operation until each process holds a protocol sub-block result; each process is in parallel communication in an annular mode until each process holds a protocol sub-block result after compression of all the processes; and each process starts to decompress all received compressed protocol sub-block results and stores data. According to the method, the communication overhead in large model tensor parallel training is reduced, mutual masking of sending and receiving as well as compression and decompression time overhead is realized, and the time cost is saved.

The present disclosure relates to systems and methods for live gaming, remote gaming, and video stream switching. Various embodiments may stream a live video output of a gaming event to a plurality of remote user devices. The gaming event may be associated with a player machine being played by a live, local player. At least one remote user device may provide a wager corresponding to an outcome of a gaming event. Remote user devices may independently update the live video output to customize gameplay experience. The outcome of the gaming event may be provided, in real-time to the plurality of remote user devices, and wagers are resolved based on the outcome.

The invention discloses a rapid data segmentation method for large-scale parallel graph neural network calculation, and relates to the field of data segmentation. The method comprises the steps that when streaming graph processing is carried out on vertexes, a super adjacency list of k-Hop is constructed, and therefore the complex dependency relationship in the GNN calculation process can be better captured. The influence of different types of neighbors on vertex distribution is particularly concerned, in the GNN training process, nodes are usually divided into training points, test points and verification points, and the influences of different types of neighbors on vertexes are different. Due to the fact that multiple rounds of iteration are usually carried out in the training stage and only one round is carried out in the testing stage, for a certain node, the node and a training neighbor are more expected to be located in the same partition, and communication overhead is reduced. Through partition information of the distributed nodes, expected values of neighbors in the partitions are increased. Namely, through the combined action of the distribution information of the inner neighbors of each node and the distribution information of the out neighbors in the k-Hop adjacency list, the effectiveness of division is enhanced.

In order to enable applications such as artificial intelligence (AI) and machine learning in a large scale, a large amount of information needs to be processed very fast. To improve the speed of the computation, not only faster graphical and central processors are required, but also the communication between processors and high bandwidth memories should be fast enough to reduce the latency. Optical interconnect can be a replacement for copper interconnect which is providing larger bandwidth and lower latency. As an efficient light source, micro-LEDs can be used as light source for chip-to- chip optical interconnect. Using a massively parallel memory-processor interconnect using low-power micro-LED, the computation speed will increase dramatically, and less amount of energy will be wasted through copper self-heating.

The invention provides a structured grid-based unstructured grid division method and electronic equipment, and the method comprises the steps: determining a computational domain range of a combustion detonation simulation task, carrying out the surface grid division of a geometric model, obtaining a geometric representation surface grid, generating a structured grid according to the geometric representation surface grid and the computational domain range, and carrying out the calculation of a combustion detonation simulation task. The method comprises the following steps: constructing a structured grid, performing simulation calculation on the structured grid, and determining a grid encryption parameter according to a simulation calculation result of the structured grid, so that an unstructured grid is generated according to the grid encryption parameter, a calculation domain range and a geometric representation surface grid, and unstructured grid division based on the structured grid is realized. The method can replace the trial-and-error iterative optimization or complex dynamic adaptive process of the unstructured grid, improves the generation efficiency of the unstructured grid, guarantees the generation quality of the unstructured grid, balances the calculation efficiency while meeting the high-precision requirement, and is suitable for a large-scale parallel environment.

Disclosed is a network and method for creating and searching a graph in a massively parallel manner. The network includes a plurality of graph storage instances that collectively store a graph formed from a plurality of entities and comprising a vertex for each entity, edges connecting pairs of vertices, and adjacency relations. Each graph storage instance stores a subgraph of the graph and comprises a partition with a non-overlapping vertex set of all the vertices in the respective subgraph, an edge set of all the edges between vertices in the respective vertex set, and the adjacency relations for the edge set and to any edges outside the partition, to which the edge set connects. Each graph storage instance also includes an executor for executing one or more of the actions over the respective subgraph, and an action monitor for supplying actions to the respective executor.

Efficient scaling of in-network compute operations to large numbers of compute nodes is disclosed. Each compute node is connected to a same plurality of network compute nodes, such as compute-enabled network switches. Compute processes at the compute nodes generate local gradients or other vectors by, for instance, performing a forward pass on a neural network. Each vector comprises values for a same set of vector elements. Each network compute node is assigned to, based on the local vectors, reduce vector data for a different a subset of the vector elements. Each network compute node returns a result chunk for the elements it processed back to each of the compute nodes, whereby each compute node receives the full result vector. This configuration may, in some embodiments, reduce buffering, processing, and / or other resource requirements for the network compute node or network at large.

A processor or other device, such as a programmable and / or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range ("LPHDR arithmetic"). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

The application provides a structure grid-based unstructured grid division method and an electronic device. The method determines a calculation domain range of a combustion detonation simulation task, performs surface grid division on a geometric model to obtain a geometric surface representation grid, generates a structure grid according to the geometric surface representation grid and the calculation domain range, performs simulation calculation on the structure grid, determines a grid encryption parameter according to a simulation calculation result of the structure grid, generates an unstructured grid through the grid encryption parameter, the calculation domain range and the geometric surface representation grid, realizes the structure grid-based unstructured grid division, can replace a trial-and-error iterative optimization or a complex dynamic self-adaptive process of the unstructured grid, improves the generation efficiency of the unstructured grid and guarantees the generation quality of the unstructured grid, balances the calculation efficiency while meeting the high-precision requirement, and is suitable for a large-scale parallel environment.

The invention discloses a key switching method and system based on a graphics processor, and belongs to the technical field of information security, and the key switching method comprises the following steps: setting a corresponding sequence for assembling a number-theory transformation kernel function, a precise basis transformation kernel function and an inner product kernel function which are realized on the graphics processor according to key switching requirements, therefore, the key switching in the high-throughput fully homomorphic encryption technology based on the graphics processor is realized. On one hand, large-scale parallelism of three kernel functions among coefficients and moduli of fully homomorphic encryption ciphertext polynomials is realized on a graphics processor, so that large-scale parallelism and high-throughput design of fully homomorphic encryption key switching kernel functions are realized, and the calculation efficiency is improved; and on the other hand, flexible parameter selection is supported, and the user is allowed to realize high-throughput key switching of any password parameter under the condition that no code modification is needed.

Embodiments of this specification provide a method and apparatus for large-scale parallel database processing, wherein the method comprises: receiving a search instruction, wherein the search instruction includes a vector to be searched corresponding to the item data to be searched; using an approximate nearest neighbor search method to determine at least one search feature vector corresponding to the vector to be searched in a pre-generated feature vector index table, and obtaining a search computation node corresponding to each search feature vector, wherein the feature vector index table records multiple feature vectors and the computation node corresponding to each feature vector; searching for an approximate vector corresponding to the vector to be searched in each search computation node; and determining a target vector corresponding to the vector to be searched from at least one approximate vector. This method significantly reduces computational overhead while ensuring search accuracy.

The present application relates to the technical field of GPU computing optimization, and in particular to a sparse attention computing method, device and medium for GPU, wherein the method realizes the high efficiency of long context reasoning through the geometric perception sparse attention framework of ball hashing, and combines a large-scale parallel hashing optimization algorithm and a load adaptive computing kernel. Compared with the existing sparse attention methods based on heuristics or gradient learning, the present application realizes higher retrieval recall rate, lower preprocessing overhead and efficient hardware adaptation to irregular sparse patterns.

The invention provides a heterogeneous symmetric matrix eigenvalue decomposition method, system and device based on GPU parallel acceleration, and belongs to the technical field of high-performance computing. According to the method, the design that five sub-processes can only be strictly and serially executed in the traditional symmetric matrix eigenvalue decomposition process is broken through, the problem that CPU and GPU computing resources are idle in a serial algorithm is solved, and the computing efficiency is greatly improved. Meanwhile, aiming at the BC-Backk stage, the invention provides a novel BC-Backk method realized based on a GPU (Graphics Processing Unit), the BC-Backk process is transferred from a CPU (Central Processing Unit) with limited parallel capability to a GPU capable of realizing large-scale parallel, and the parallel efficiency of the BC-Backk stage is greatly improved. According to the method, heterogeneous architecture characteristics and GPU parallelism are fully utilized, parallel between symmetric matrix eigenvalue solving sub-processes and internal parallel of BC-Back are achieved, CPU and GPU resources are fully utilized, and the calculation performance of the interior of a computer for the symmetric matrix eigenvalue solving process is greatly improved.

Systems, methods, and compositions for generating a high-resolution spatial map of a distribution of targets of a sample are described. Systems and methods can further include features configured to reduce observation of smearing artifacts in generated spatial maps. Processes for generating the spatial map can include: receiving the sample at a substrate having a distribution of functionalized particles, each having a stochastic barcode sequence paired with a position on the substrate; promoting interactions between the distribution of targets of the sample and the distribution of functionalized particles; applying a set of reactions to the sample at the substrate; and obtaining a set of sequences of a population of molecules generated from the set of reactions.

This invention discloses a parallel situational gravity calculation chip and method based on in-memory computing, belonging to the field of artificial intelligence chips and analog in-memory computing technology. The chip includes: an event polarity input unit, which converts externally input event information loads (six-dimensional polarity vectors) into analog voltage signals; a situational reference storage array, employing a memristor cross-switch array, with each row storing a six-dimensional binary encoded vector of a reference situational type (such as the 64 hexagrams); a parallel gravity calculation unit, which performs large-scale parallel multiply-accumulate operations simultaneously in the analog domain, following the gravity calculation rule of "like lines cooperate, dissimilar lines repel," generating a multi-dimensional gravity intensity distribution; and a gravity readout and post-processing unit, which converts the gravity distribution into situational awareness results and outputs them. This invention adopts an in-memory computing architecture, eliminating the "memory wall" bottleneck of the traditional von Neumann architecture, achieving nanosecond-level fully parallel gravity calculation and ultra-low power consumption operation. It can be deployed as an independent situational awareness processor at sensor terminals, IoT terminals, and wearable devices.

Embodiments disclosed herein are directed to microfluidic devices that allow for scalable on-chip screening of combinatorial libraries and methods of use thereof. Droplets comprising individual molecular species to be screened are loaded onto the microfluidic device. The droplets are labeled by methods known in the art, including but not limited to barcoding, such that the molecular species in each droplet can be uniquely identified. The device randomly sorts the droplets into individual microwells of an array of microwells designed to hold a certain number of individual droplets in order to derive combinations of the various molecular species. The paired droplets are then merged in parallel to form merged droplets in each microwell, thereby avoiding issues associated with single stream merging. Each microwell is then scanned, e.g., using microscopy, such as high content imaging microscopy, to detect the optical labels, thereby identifying the combination of molecular species in each microwell.

The application provides a tokamak plasma density profile inversion method and device, which adopts a CPU-GPU heterogeneous collaborative computing architecture, takes three-frequency band IQ original data measured by a microwave reflectometer as input, and constructs a collaborative working mechanism of a GPU parallel computing pipeline and a CPU serial processing pipeline. The GPU end is responsible for large-scale parallel spectrum analysis and beat frequency extraction tasks, and adopts a sliding window method and a weighted centroid algorithm to realize batch parallel processing. The CPU end is responsible for data screening, iterative inversion and post-processing tasks, adopts a three-strategy consistency voting mechanism to automatically determine an effective frequency range, and recursively solves refractive index and radial position by an iterative phase integral method. Through GPU acceleration, the time consumption of single time point calculation is reduced to less than 4 milliseconds, full-process automatic data inversion is realized, the processing timeliness is high, the processing procedure is simple, and the engineering requirements of tokamak experiment real-time feedback control are met.

The present invention discloses a parallelized finite element mesh stitching method for flow channels of reactor unit assemblies, belonging to the field of finite element mesh technology; the present invention classifies cavities according to their characteristics, and then stitches cavities of different categories using different methods. In addition to the original point stitching algorithm, the algorithm also adaptively applies a variety of algorithms such as particle swarm optimization, shortest path problem, and advancing wavefront method, and achieves high-efficiency stitching of large-scale meshes while ensuring the overall mesh quality through parallel processing of the algorithm and tetrahedron quality detection optimization algorithm. The present invention helps to optimize mesh quality, promote the application scenarios of large-scale parallel mesh division algorithms, fill the gap in three-dimensional mesh stitching technology, and further promote the application and development of mesh technology in the field of numerical calculation.

A cache architecture for an array of identical cores arranged in a grid. Each of the cores include interconnections to neighboring cores in the grid, a memory, and an algorithmic logic unit. A first core of the array is configured to receive a memory access request for data from at least one core of the array of cores configured to perform a computational operation. A second core of the array is configured to determine whether the requested data is present in a cache memory via a cache index including addresses in the cache memory. A third core of the array is configured as the cache memory. The memory of the third core is used as the cache memory. An address of the requested data from the cache index is passed to the third core to output the requested data.

The invention provides a Cartesian grid wall distance calculation method for load balance under a parallel framework, a medium and equipment, and the method comprises the steps: predicting the number of iterations of each Cartesian grid unit in an object plane data index structure through combining the characteristics of newly generated Cartesian grid units and old Cartesian grid units before and after grid encryption; according to the method, the partition weight is set to be in direct proportion to the number of iterations, and partition considering the weight is performed before the wall distance is calculated, so that the situation that inter-process calculation loads are unbalanced when the wall distance is calculated is relieved, the time needed by wall distance calculation in the process of generating the adaptive Cartesian grid in a large-scale parallel mode is remarkably shortened, and the calculation efficiency of the adaptive Cartesian grid is improved. And the self-adaptive Cartesian grid generation efficiency and the parallel expandability are improved.

The invention discloses a Paillier homomorphic encryption acceleration board card system supporting multi-chip cooperative computing. The Paillier homomorphic encryption acceleration board card system comprises a central scheduling control module, a plurality of isomorphic encryption computing chips, an inter-chip communication module, a host interface module and an auxiliary function module. And the central scheduling control module is used for analyzing a ciphertext structure and dynamically scheduling chip resources according to a task scale, and supports multiple cooperative computing modes such as ciphertext shunting, task fragmentation and pipeline processing. And the inter-chip communication module adopts AXI interconnection or an NoC structure to realize high-speed data exchange. Parallel calculation of modular exponent operation is completed among the slave chips in a master-slave cooperation mode, and dynamic modular basis configuration, chip activation control and a thermal management mechanism are supported. The system is suitable for being deployed on a cloud server, an edge device and a multi-card cluster platform, large-scale parallel acceleration processing of the Paillier encryption algorithm is achieved, and the system has high expansibility and high reliability.

The invention discloses a dense matrix and sparse matrix efficient coupling parallel method. The method comprises the following steps: S1, carrying out feature analysis on an input dense matrix and sparse matrix; s2, carrying out adaptive partitioning on the dense matrix and the sparse matrix; s3, creating a uniform matrix descriptor for each matrix block; s4, constructing a calculation dependency graph; s5, executing parallel computing; according to the dense matrix and sparse matrix efficient coupling parallel method, through data rearrangement of self-adaptive hybrid storage and cache perception, the cache hit rate is greatly increased, the bottleneck of memory access mode conflicts in hybrid calculation is overcome, and meanwhile, based on an accurate prediction model and dynamic scheduling, the performance data in the running process are collected. The method has the advantages that combined optimization of computing load and communication is achieved, high load balance and resource utilization rate under large-scale parallel are guaranteed, redundant format conversion overhead is almost eliminated by the aid of unified descriptors and inert conversion strategies, a computing pipeline is smoother, and overall performance is improved remarkably.

According to the sinusoidal signal generation method and device and the cosine signal generation method and device provided by the invention, based on triangle and angle formula expansion, a sinusoidal signal is generated in a manner of generating an iterative value through preconfiguration of a basic value and pipeline multiplication and addition iteration, and complex logics such as data cache management of a DDS and multi-round iterative calculation of Cordic are avoided. Moreover, the multiply-add operation module of the m-level assembly line splits the logic combination of multiplication and addition operation in multiply-add operation into m clock periods, so that the operation frequency of the FPGA is optimized. The method only depends on common logic operations such as accumulative counting, data selection and basic multiplication and addition, a large number of BRAMs for storing sine wave complete data in a DDS scheme are not needed, large-scale parallel iterative logic needed by a Cordic scheme for guaranteeing precision and throughput rate is also avoided, only a small number of LUT tables and DSP resources are needed in actual implementation, and hardware resource occupation of an FPGA is greatly reduced.