173 results about "Massively parallel" patented technology

The present methods are exemplified by a process in which maternal blood containing fetal DNA is diluted to a nominal value of approximately 0.5 genome equivalent of DNA per reaction sample. Digital PCR is then be used to detect aneuploidy, such as the trisomy that causes Down Syndrome. Since aneuploidies do not present a mutational change in sequence, and are merely a change in the number of chromosomes, it has not been possible to detect them in a fetus without resorting to invasive techniques such as amniocentesis or chorionic villi sampling. Digital amplification allows the detection of aneuploidy using massively parallel amplification and detection methods, examining, e.g., 10,000 genome equivalents.

Methods and systems are provided for massively parallel genetic analysis of single cells in emulsion droplets or reaction containers. Genetic loci of interest are targeted in a single cell using a set of probes, and a fusion complex is formed by molecular linkage and amplification techniques. Methods are provided for high-throughput, massively parallel analysis of the fusion complex in a single cell in a population of at least 10,000 cells. Also provided are methods for tracing genetic information back to a cell using barcode sequences.

Contiguity information is important to achieving high-quality de novo assembly of mammalian genomes and the haplotype-resolved resequencing of human genomes. The methods described herein pursue cost-effective, massively parallel capture of contiguity information at different scales.

A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 [log_b N] stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and [log_b N] indicates a ceiling function providing the smallest integer not less than log_b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

Example embodiments include a method for massive parallel stress testing of resistive type memories. The method can include, for example, disabling one or more internal analog voltage generators, configuring memory circuitry to use a common plane voltage (VCP) pad or external pin, connecting bit lines of the memory device to a constant current driver, which works in tandem with the VCP pad or external pin to perform massive parallel read or write operations. The inventive concepts include fast test setup and initialization of the memory array. The data can be retention tested or otherwise verified using similar massive parallel testing techniques. Embodiments also include a memory test system including a memory device having DFT circuitry configured to perform massive parallel stress testing, retention testing, functional testing, and test setup and initialization.

A machine for generating piece-wise non-linear reference waveforms at low cost, particularly in integrated circuit technologies. The reference waveform can be a distorted sinusoidal waveform such as a truncated sinusoid. Provided that local distortion is low enough in some waveform segments, for instance, in the transitions between saturation levels, parts of the waveform can be used as non-linear reference segments in data converters based on comparison of inputs. The distorted sinusoidal waveform can also be filtered to reduce distortion. In the preferred embodiment of the invention, suitable sinusoids with high or low distortion can be generated using an op-amp configured with a Wien Bridge providing positive feedback and a resistor bridge providing negative feedback. The invention differs from prior art Wien Bridge oscillators in having negative feedback gain that forces the op-amp output into saturation. One filter stage is provided by the positive feedback network itself. Additional filtering can allow further distortion reduction. The specification suggests a cascade of servo-grounded Wien Bridge stages as a simple and efficient approach to the filtering. The invention can be fabricated using a small number of parts which are easy to fabricate with existing integrated circuit technologies such as CMOS, so that low-cost, low-power implementations can be included in mixed-signal chips as parts of A/D converters, D/A converters, or calibration signal generators. The invention is also amenable to massively parallel and shared implementations, for instance, on a CMOS image sensor array chip or on a image display device.

The invention discloses a GPS signal large-scale parallel quick capturing method, which comprises the following steps: configuring a large-scale parallel quick capturing module firmware comprising submodules of multiplier, data block cache, parallel part correlative processing, frequency domain transformation, postprocessing and digital controlled oscillator, code generator and the like in a system CPU; through the calling computation, converting low-medium frequency digital signals into baseband signals in a processing procedure to combine a data block; performing zeroing extension of the length and the data block on each equational data section in the data block; then based on FFT transformation computation, performing parallel part correlative PPC processing on each extended data section and local spreading codes, and performing FFT transformation on each line of a formed PPC matrix to obtain a result matrix; and performing coherent or incoherent integration on a plurality of result matrixes formed by processing a plurality of data blocks to increase the processing gain, improve the capturing sensitivity, roughly determine the code phase and the Doppler frequency of GPS signals, and achieve two-dimensional parallel quick capturing of the GPS signals. The method has high processing efficiency and high capturing speed, and can be applied to various GPS positioning navigation aids.

The amount of data being delivered across networks is constantly increasing. This system and method demonstrates an improved system and method for establishing secure network connections with increased scalability and reduced latency. This approach also includes arbitrary segmentation of incoming network traffic, and dynamic assignment of parallel processing resources to execute application code specific to the segmented packets. The method uses a modified network state model to optimize the delivery of information and compensate for overall network latencies by eliminating excessive messaging. Network data is application generated, and encoded into pixel values in a shared framebuffer using many processors in parallel. These pixel values are transported over existing high speed video links to the Advanced Network Interface Card, where the network data is extracted and placed directly on to high speed network links.

A method, system, and computer readable medium for converting a series of computer executable instructions in control flow graph form into an intermediate representation, of a type similar to Static Single Assignment (SSA), used in the compiler arts. The indeterminate representation may facilitate compilation optimizations such as constant propagation, sparse conditional constant propagation, dead code elimination, global value numbering, partial redundancy elimination, strength reduction, and register allocation. The method, system, and computer readable medium are capable of operating on the control flow graph to construct an SSA representation in parallel, thus exploiting recent advances in multi-core processing and massively parallel computing systems. Other embodiments may be employed, and other embodiments are described and claimed.

MicroLED devices can be transferred in large numbers to form microLED displays using processes such as pick-and-place, thermal adhesion transfer, or fluidic transfer. A blanket solder layer can be applied to connect the bond pads of the microLED devices to the terminal pads of a support substrate. After heating, the solder layer can connect the bond pads with the terminal pads in vicinity of each other. The heated solder layer can correct misalignments of the microLED devices due to the transfer process.

A router for interconnecting external devices coupled to the router. The router comprises a switch fabric and a plurality of routing nodes coupled to the switch fabric. Each routing node is capable of transmitting data packets to, and receiving data packets from, the external devices and is further capable of transmitting data packets to, and receiving data packets from, other routing nodes via the switch fabric. The router also comprises a control processor for comparing the N most significant bits of a first subnet address associated with a first external port of a first routing node with the N most significant bits of a second subnet address associated with a second external port of the first routing node. The router determines a P-bit prefix of similar leading bits in the first and second subnet addresses and transmits the P-bit prefix to other routing nodes.

Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.

This invention provides a device and methods for the rapid detection and/or diagnosis and/or characterization of one or more allergies (e.g., causes IgE mediated allergic reaction (immediate hypersensitvity) in a mammal (e.g., a human or a non-human mammal). In certain embodiments, the device comprises a microcantilever array where different cantilevers comprising the array bear different antigens. Binding of IgE to the antigen on a cantilever causes bending of the cantilever which can be readily detected.

The invention belongs to the field of computer figures, and provides a modeling structure of a GPU texture mapping non-blocking memory Cache. The modeling structure comprises a texture Cache storage status and control unit (1), a missing information status handling register memory cell (MSHR) (2), a multi-request combination and collision detection unit (3), and a texture memory Cache core unit (4). Hardware modeling with accurate periods is conducted on a texture memory Cache access process, parallel processing of texture access request data is realized through a multi-process mode including input request collision detection, request combination and division, multiple ports, multiple Banks and non-blocking flowing, and large-scale parallelism and high throughput demands of texture access data are met effectively. Moreover, the modeling structure effectively avoids configuration of complex circuit signal design and rapid assessment large-scale hardware system, is suitable for system level design and development of circuits in an early age, and provides effective reference for products and functions of the same kind.

A distributed processing RAID data storage system utilizing optimized methods of data communication between elements. In a preferred embodiment, such a data storage system will utilize efficient component utilization strategies at every level. Additionally, component interconnect bandwidth will be effectively and efficiently used; systems power will be rationed; systems component utilization will be rationed; enhance data-integrity and data-availability techniques will be employed; physical component packaging will be organized to maximize volumetric efficiency; and control logic of the implemented that maximally exploits the massively parallel nature of the component architecture.

The invention discloses a large-scale parallel program property-predication realizing method based on representative replay, belonging to the technical field of parallel program property prediction. The method comprises the following steps: collecting communication sequences and calculation vectors of parallel programs, analyzing calculation similarity of the processes, selecting a representativeprocess, recording the communication content of the representative process, using a calculation node of a target platform to replay the representative process, obtaining the sequence calculation timeof the representative process, and using the calculation time to replace the calculation time of other processes; obtaining the communication records of the parallel programs; and using a network simulator to automatically predict the final program property. By using the invention, only few hardware sources can be used, and the accurate parallel program property prediction can be obtained.

A methodology and processing model utilize a unique set of data structures and processing algorithms, which are capable of being leveraged on a Massively Parallel Relational Database Management System (RDBMS) to provide fast, accurate, and scalable access to text data that is stored in these data structures. The methodology relies on a positional co-occurrence-based Statistical Natural Language Processing (SNLP) algorithm, a set of data structures that define the data to be searched and contain the co-occurrence patterns that are created by the SNLP algorithm, a real-time relevancy formula and weighting structure that returns the most relevant documents to the user.

The invention discloses a two-stage self-adaptive scheduling method suitable for a large-scale parallel data processing tasks. Two-stage scheduling is performed on tasks from a task stage and a subtask stage. By the method, the problem of parallel scheduling difficulty caused by complex dependence relationship among the tasks is solved effectively, parallelism degree is increased, orderly and efficient parallel processing of large-scale data processing tasks is realized, task waiting or executing time is reduced, and overall executing time is shortened. In addition, by the method, executor operation statistical information can be fed back to a scheduler, self-adaptive adjusting of executor pool size and task type is realized, and scheduling is constantly optimized, so that system resourceusing efficiency is improved.