The invention relates to a
semiconductor device with high performance, low
power consumption and an optimized structure. The
semiconductor device comprises a buffer layer, a channel layer, a
barrier layer, a
contact layer, a source
electrode, a drain
electrode and a gate
electrode. The buffer layer provides lattice matching and
thermal stability, the channel layer has
high electron mobility and saturation speed, and the
barrier layer optimizes device performance by adjusting an energy band structure. A first groove and a second groove which completely penetrate to the upper surface of a channel layer are introduced into a
barrier layer, the control capability of a grid electrode on a channel region is enhanced, meanwhile, the design of the grooves is overlapped with the edge projection of a
contact layer, and the
electric field effect of the edge of the grid electrode is enhanced. In addition, the interlayer stress is optimized by adopting a multi-layer buffer strategy, and the performance of the device is further improved by optimizing the thickness of each functional layer. The manufacturing process comprises the steps of substrate preparation, layer growth,
etching treatment, electrode formation,
passivation layer deposition and the like, and the
semiconductor device realizes high performance, low
power consumption and high reliability by optimizing the structural design and the manufacturing process.