17568results about "Coupling light guides" patented technology

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A chip package includes a housing, one or more electrical connections coupled to an exterior of the housing, a photonic integrated circuit, and a scanning unit. Both the photonic integrated circuit and the scanning unit are disposed within the housing. The photonic integrated circuit has at least one waveguide designed to guide a beam of light. The scanning unit is designed to laterally scan the beam of light across a focal plane outside of the housing. The scanning unit is aligned with the photonic integrated circuit such that the beam of light is coupled between the photonic integrated circuit and the scanning unit.

Various embodiments provide for electro-photonic networks, including a plurality of processing elements connected by bidirectional photonic channels, suited for implementing neural-network models. Weights of the model may be preloaded into memory of the processing elements based on assignments of neural nodes to processing elements implementing them, and routers of the processing elements can be configured to stream activations between the processing elements based on a predetermined flow of activations in the model.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

A medical device operating as a stylet is described. The medical device can include an insulating layer (or sheath) encapsulating both a multi-core optical fiber and a conductive medium. The optical fiber can include a cladding and a plurality of core fibers spatially arranged within the cladding. Each of the core fibers can include a plurality of sensors distributed along a longitudinal length of that corresponding core fiber and each of these sensors can be configured to: (i) reflect a light signal of a different spectral width based on received incident light, and (ii) change a characteristic of the reflected light signal for use in determining a physical state of the multi-core optical fiber. The conductive medium can provide a pathway for electrical signals detected at a distal portion of the conductive medium. The conductive medium may be concentric to the cladding, but separate and adjust thereto.

Disclosed in the present invention is a method for automatically measuring and adjusting the refractive index of the cross-section of an optical fiber. The method comprises the following steps: S1, optical fiber alignment; S2, detection of optical signals; S3, automatic compensation for optical fiber fusion splicing; S4, analysis of the optical signals; and S5, automatic adjustment and compensation. Compared with the conventional related art, the automatic compensation technique for optical fiber fusion splicing in the present invention has advantages such as higher quality stability, reduced manual intervention, precise parameter adjustment, rapid response capability and improved production efficiency, and is applicable to production and application in the field of optical fiber communications.

The invention relates to the field of pressure sensors, in particular to a pressure sensor and a processing method, and a chip comprises a silicon substrate, a silicon dioxide dielectric layer, a device layer, a metal electrode and packaging glass. The device layer comprises a silicon carbide single crystal device layer and a silicon device layer; the silicon carbide single crystal device layer is arranged on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer and the silicon substrate are connected in sequence; the device layer is etched to form a sensitive resistor device layer, an annular sealing region and a micro-channel; the sensitive resistance device layer is isolated from the annular sealing area through the micro-channel; the device layer, the silicon dioxide dielectric layer and the silicon substrate are etched to form a cross beam etching area; the silicon substrate is etched to form a silicon pressure cavity and a beam film; the metal electrode is arranged on the top of the device layer; and the packaging glass anode is bonded at the top of the device layer or the bottom of the silicon substrate so as to solve the problems of low high temperature resistance and low sensitivity of the MEMS pressure sensor.

An apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. The first mating protrusion is to be partially disposed within a first recess formed in a second surface of a photonic integrated circuit (PIC) die when the first surface of the optical interposer opposes the second surface of the PIC die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die. A first portion of an outer surface of the first mating protrusion is to contact a first side wall of the first recess and a second portion of the outer surface of the first mating protrusion is to oppose a second side wall of the first recess such that a second space is to be defined therebetween.

The invention relates to a light receiving end, which is characterized in that an array lens for coupling emergent light of each channel of a 45-degree optical fiber array into a corresponding channel of an array detector chip is arranged between a 45-degree total reflection surface of a V-shaped groove in the 45-degree optical fiber array and the array detector chip, and the side surface of the array lens is fixed with the side surface of a cover plate in the 45-degree optical fiber array in a bonding manner. The invention discloses an optical receiving end coupling method. The method comprises the following steps of: aligning each channel of a 45-degree optical fiber array with each channel of an array detector chip one by one in an active coupling manner; the array lens is coupled between the 45-degree total reflection surface of the V-shaped groove in the 45-degree optical fiber array and the array detector chip in an active coupling manner, so that light emitted from each channel of the 45-degree optical fiber array is coupled into the corresponding channel of the array detector chip, and when the optimal coupling position is reached, glue dispensing is performed, and the light emitted from each channel of the 45-degree optical fiber array is obtained. And the side surface of the array lens is fixed with the side surface of the cover plate in the 45-degree optical fiber array. The beneficial effects are that the optical receiving end is optimal in performance, highest in yield and low in cost.

An eyepiece includes a planar waveguide having a front surface and a back surface. The eyepiece also includes a grating coupled to the back surface of the planar waveguide and configured to diffract a first portion of the light propagating in the planar waveguide out of a plane of the planar waveguide toward a first direction and to diffract a second portion of the light propagating in the planar waveguide out of the plane of the planar waveguide toward a second direction opposite to the first direction and a wavelength-selective reflector coupled to the front surface of the planar waveguide. The wavelength-selective reflector comprises a multilevel metasurface comprising a plurality of spaced apart protrusions having a pitch and formed of a first optically transmissive material and a second optically transmissive material disposed between the spaced apart protrusions.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention relates to an MEMS mode wafer, an MEMS probe card detection method, an MEMS probe card detection device and a storage medium. The detection method is applied to MEMS wafer detection equipment, and comprises the following steps: loading test configuration parameters of an MEMS probe card to be detected; fixing the MEMS probe card to be tested on a probe seat of test equipment; placing an MEMS mode wafer matched with the to-be-tested MEMS probe card at a preset target position on a test platform of test equipment; the MEMS mode wafer comprises a test point array which is the same as a to-be-tested MEMS wafer corresponding to the to-be-tested MEMS probe card; starting a visual alignment system, and aligning the MEMS probe card to be tested with the MEMS mode wafer; the MEMS probe card to be tested is calibrated; and executing the test task of the MEMS wafer to be tested, and detecting the MEMS probe card to be tested. The test task is automatically executed by using the MEMS mode wafer, and the efficient test of the MEMS probe card is realized.

The invention relates to the technical field of silicon waveguide and optical fiber coupling, and particularly provides an AI-based silicon waveguide-optical fiber mode field self-alignment coupling method and system, and the method comprises the steps: monitoring the strain distribution of a chip in real time through an integrated distributed fiber bragg grating array, and obtaining the light field intensity distribution of a coupling region through cooperation with a near-field optical probe array; constructing a deep space-time convolutional network, and generating a deformation compensation vector and a waveguide reconstruction parameter by an output layer; a nanofluid channel is integrated on the side wall of the waveguide, and the refractive index of liquid is adjusted through an electrowetting effect to realize dynamic broadening of a mode field; and the electrostatic driving micro-beam embedded below the waveguide adjusts the spatial pose of the waveguide according to an instruction of an output layer of the depth space-time convolutional network. The system comprises a light field intensity acquisition module, a convolutional network construction module and a spatial pose adjustment module. According to the method, real-time analysis and prediction are performed, so that system parameters are actively adjusted, and alignment precision and stability are improved.

An optical-electrical substrate for providing electrical and optical connections to a photonic integrated circuit (PIC) includes a glass body with glass optical waveguides along an upper surface, and electrically conductive vias extending through a portion of the glass body from an intermediate surface to a lower surface. The intermediate surface is arranged at an elevation positioned between the upper and lower surfaces, and may optionally support redistribution layers and an electrical integrated circuit. An optical-electrical substrate may be fabricated by defining glass optical waveguides along an upper surface of a glass body, and forming electrically conductive vias through the glass body from the intermediate surface to the lower surface. A connection method includes registering a PIC with an optical-electrical substrate as described herein; heating bonding bumps arranged between the PIC and the intermediate surface; and providing optically transmissive paths between the PIC and glass optical waveguides of the substrate.

The invention discloses an MEMS thermal flow sensor based on a glass film structure and a preparation method of the MEMS thermal flow sensor. The sensor comprises a glass inner silicon substrate, a back cavity, a silicon through column, a heating resistor, a temperature measurement resistor, an environment temperature measurement resistor, a chromium adhesion layer, a PAD port and a silicon nitride protection layer. Wherein the heating resistor is located in the center, and the temperature measuring resistors are symmetrically distributed on two sides of the heating resistor; the back cavity is located on the back of the glass inner silicon substrate, and the heating resistor, the temperature measuring resistor and the environment temperature measuring resistor lead a PAD port to the back of the glass inner silicon substrate through a silicon through column. A thermal temperature difference principle is adopted, and upstream and downstream temperature measuring resistors form a Wheatstone bridge. When the flow velocity is not zero, the Wheatstone bridge outputs, and the larger the flow velocity is, the larger the output is. Based on the glass and silicon composite substrate, the suspension film structure is formed through the silicon etching process, transmission of heat to the substrate is greatly reduced, and the heat utilization rate is increased.

Described herein are a computing systems comprising a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer, an inner interface comprising a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface comprising a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, wherein the outer interface at least partially encloses the inner interface.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention relates to an optical engine and a forming method thereof, the optical engine comprises an adapter plate, an electric chip, an optical chip and a packaging substrate, the adapter plate comprises a first surface, a second surface opposite to the first surface, and a first through hole penetrating through the first surface and the second surface, the first surface of the adapter plate and the front surface of the electric chip are mounted on the optical chip and are electrically connected with the optical chip, and the second surface of the adapter plate is mounted on the packaging substrate and is electrically connected with the packaging substrate. According to the 3D fan-out type packaging optical engine integrated with the TSV adapter plate, the problems that an existing 3D fan-out type packaging optical engine is large in module size and cannot support the extremely high number of channels can be solved at the same time, and the problems that an existing 3D integrated optical engine with the TSV is high in cost and chip incoming materials are fixed can be solved at the same time.

The invention discloses an interposer, a photoelectric co-packaging structure and a preparation method thereof, and the interposer comprises a substrate which comprises a glass substrate or a quartz substrate; the first waveguide layer is arranged on the substrate, and at least one first waveguide structure is arranged in the first waveguide layer; the first waveguide structure comprises a first optical waveguide; the second waveguide layer is arranged on the side, away from the substrate, of the first waveguide layer, and at least one second waveguide structure is arranged in the second waveguide layer; the second waveguide structure comprises N second optical waveguides, third optical waveguides,... and (N + 1) th optical waveguides which are sequentially stacked on one side, far away from the substrate, of the first waveguide layer; wherein 1 < = N; the refractive indexes of the second optical waveguide, the third optical waveguide,..., and the N + 1th optical waveguide are sequentially increased, and the refractive index of the second optical waveguide is greater than the refractive index of the first optical waveguide. The technical scheme of the invention aims to provide the photoelectric co-packaging structure capable of realizing high-density integration.

Disclosed herein is a waveguide-based display comprising: a waveguide, a source of image modulated light projected over a field of view; an input coupler for coupling said light into a total internal reflection (TIR) path within the waveguide; and a grating structure for providing beam expansion of the TIR light in at least one direction and extracting the TIR light from the waveguide. The grating structure may include a plurality of grating elements having at least two different grating prescriptions and at least one surface relief grating formed by a phase separation process.

Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention provides a preparation method of an island and beam film structure micro differential pressure sensor with an IC (Integrated Circuit), which comprises the following steps: arranging an N-type buried layer, a P-type buried layer and an island film structure on an SOI (Silicon On Insulator) silicon wafer, then connecting the SOI silicon wafer with a double-parabolic silicon wafer, and arranging a medium isolation groove, an N-type buried layer connecting region, a P well, a P-type buried layer connecting region, a sensitive resistor, a P-type base region, an N-type base region, an N-type emitter region and a P-type emitter region on the SOI silicon wafer. According to the invention, the preparation of the complementary bipolar transistor double-buried layer is completed by combining a semiconductor manufacturing technology and an MEMS manufacturing technology under the condition of not using an epitaxial process; the process flow is integrally simplified, and the preparation efficiency is improved.

Silicon photonics technologies adds integrated optics functionality to CMOS integrated circuits thereby leveraging high volume manufacturing. Independent of geometry or technology these silicon photonic devices require packaging with single mode optical fibers to interface to the optical network and / or co-packaging with active semiconductor devices, discrete microoptoelectromechanical systems (MOEMS) s or monolithically integrated MOEMS. Stringent performance constraints and minimizing manufacturing costs / times are consistent demands on such photonic circuits. Accordingly, there is a demand for low-cost and low-loss optical coupling technologies for packaging that can easily be scaled for mass production that overcome limitations in the prior art. The inventors have established design methodologies, packaging schemes and component designs that leverage automated passive assembly techniques for speed / cost in combination with directly written optical interconnects that allow for offsetting the losses that would arise from the manufacturing tolerances of these passive assembly techniques.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention provides an optical engine based on 3D packaging and a packaging method. The optical engine comprises an optical chip, an electric chip, an optical fiber module and a heat dissipation substrate. The heat dissipation substrate comprises a main body part and a sunken part extending out of the side face, provided with the optical port, of the optical chip; the optical chip comprises a first surface and a second surface, the first surface of the optical chip is connected with the second surface of the electric chip, the second surface of the optical chip is adhered to the main body part of the heat dissipation substrate, and the bottom of the optical fiber module is adhered to the concave part of the heat dissipation substrate. The electric chip is placed on the high-frequency substrate material, and the expansion coefficient of the substrate material is similar to that of the chip, so that the reliability of the chip after bonding can be ensured; the PIC and the FA are packaged in a coplanar manner by using the external heat dissipation substrate at the top, and a plurality of bonding surfaces are provided for the FA, so that the difficulty that the relative positions of the PIC and the FA are not matched due to thermal stress is solved.

There is provided a photonic integrated apparatus for determining an orientation and / or a position of an optical waveguide, by measuring a relative intensity and a relative phase difference of the probe light signal incident on a sensor array. The phase profile of the probe light signal projected spatially on the sensor array is particularly sensitive to small changes in the optical probe's orientation and distance. The apparatus measures the relative intensity and relative phase difference of the probe light signal incident on a sensor array. A photonic integrated sensor circuit comprises the sensor array and one or more optical interferometric circuits. Changes in the sensed relative intensity and relative phase difference of the probe light signal, as sampled by the sensor array, indicate variations in the relative orientation and / or distance between the optical waveguide and the sensor array.

An article of manufacture including a fiber optic termination of a small core optical fiber for use with a surgical laser apparatus (the output from which may be characterized by a high M2 factor) or other high-power or high-energy laser (including an appropriate fiber laser) is configured for safe and efficient coupling of light at a large laser focal point and / or to enable the process of coupling of radiant intensities exceeding the silica fiber damage thresholds and / or those ionizing the air if fully focused therein. The termination may include a glass cylinder structured to include a core region and a glass cladding region the ratio of dimensions of which is substantially equal to the ratio of respectively-corresponding dimensions of the employed optical fiber. A method of propagating light through such article of manufacture.

The invention discloses a preparation method of a vertical comb-driven MEMS (Micro Electro Mechanical System) micromirror, which comprises the following steps of: forming a through alignment mark and a pre-etched comb structure on a device layer by using a first composite mask, and forming the through alignment mark and the pre-etched comb structure on the back surface of the device layer on a first substrate through a composite mask process, after the first substrate and the second substrate are bonded, the self-alignment composite mask of the comb tooth structure is aligned with the back face pre-etched comb tooth structure through the through alignment mark, high-precision alignment of the comb tooth structure is achieved, accumulated errors are avoided, and the yield of device preparation is improved.