23945results about "Coupling light guides" patented technology

A package includes a first die with a bridging element with a first interconnect region, a first photonic transceiver portion, a second interconnect region, a first photonic path to an optical interface (OI), and a second photonic path from the OI to the first photonic transceiver portion. The first interconnect region electrically couples the first photonic transceiver portion to a second photonic transceiver portion in an analog / mixed-signal die (AMS die), while the second interconnect region connects a third photonic transceiver portion in a general die to the second photonic transceiver portion using an electrical coupling embedded in the first die. The electrical interconnects in the first interconnect region are less than two millimeters in length.

A circuit package is described that includes a photonic interposer, a second interposer, and a die partially overlapping and connected to both the photonic interposer and the second interposer.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A connector assembly includes an electrical connector, a metal shielding cage and a light guide element. The electrical connector includes an insulating body and a number of conductive terminals. The insulating body includes a mounting surface configured to be mounted to a circuit board and an installation through hole. The light guide element includes a light pipe which is at least partially inserted into the installation through hole along a mating direction. The light guide pipe includes a light guide head and an end far away from the light guide head. The end is disposed adjacent to the light emitting element on the circuit board.

The invention relates to the technical field of light emitting devices, and discloses a control method for a silicon light integrated multi-wavelength light emitting device, and the method comprises the steps: carrying out the grating coupling processing and polarization state separation processing of a plurality of wavelength channels of the silicon light integrated multi-wavelength light emitting device, and obtaining an initial optical characteristic data set; performing temperature response characteristic analysis to obtain a temperature field characteristic parameter set; performing spectral characteristic analysis on the plurality of wavelength channels to obtain wavelength channel characteristic vectors; a wavelength drift coefficient matrix and a refractive index change coefficient matrix are calculated, and a multi-wavelength linkage control data model is generated; according to the method, a hierarchical control structure comprising a quick response layer, a temperature compensation layer and a polarization optimization layer is constructed, multi-wavelength cooperative control operation is executed, and a steady-state control parameter set is output, so that the wavelength stability control precision and the temperature control precision are improved, the adaptive capacity to disturbance of different time scales is enhanced, and the stability of the system is improved. And stable operation under complex working conditions is ensured.

A package includes a first die with a compute element and first region, a second die with a compute element and second region, and a bridging element connecting the first and second dies. The bridging element includes interconnect regions for electrical coupling, a first photonic path from the first interconnect region to the second, and a second photonic path in the reverse direction. A photonic transceiver is integrated into the bridging element, with one portion sending and receiving optical signals via the photonic paths, and the other portion located in an AMS block in the first die or second die near the memory and compute elements. The transceiver portions are connected by a short electrical interconnect (less than 2 mm).

A chip package includes a housing, one or more electrical connections coupled to an exterior of the housing, a photonic integrated circuit, and a scanning unit. Both the photonic integrated circuit and the scanning unit are disposed within the housing. The photonic integrated circuit has at least one waveguide designed to guide a beam of light. The scanning unit is designed to laterally scan the beam of light across a focal plane outside of the housing. The scanning unit is aligned with the photonic integrated circuit such that the beam of light is coupled between the photonic integrated circuit and the scanning unit.

Various embodiments provide for clock signal distribution within a processor, such as a machine learning (ML) processor, using a photonic fabric.

Various embodiments provide for electro-photonic networks, including a plurality of processing elements connected by bidirectional photonic channels, suited for implementing neural-network models. Weights of the model may be preloaded into memory of the processing elements based on assignments of neural nodes to processing elements implementing them, and routers of the processing elements can be configured to stream activations between the processing elements based on a predetermined flow of activations in the model.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

The present disclosure relates to circuit package implementations. The circuit package includes a PIC that allows for the transmission of data photonically between hardware coupled to the PIC. The circuit package further includes one or more spacers that are positioned above the PIC in a manner that allows light to pass through an optical path between the top surface of the circuit package and the PIC. Different spacers can be added to the package at different stages of the manufacturing process such that the optical path is maintained through the manufacturing of the circuit package. The circuit package having the optically accessible PIC may be implemented within the framework of a microelectronic package.

A medical device operating as a stylet is described. The medical device can include an insulating layer (or sheath) encapsulating both a multi-core optical fiber and a conductive medium. The optical fiber can include a cladding and a plurality of core fibers spatially arranged within the cladding. Each of the core fibers can include a plurality of sensors distributed along a longitudinal length of that corresponding core fiber and each of these sensors can be configured to: (i) reflect a light signal of a different spectral width based on received incident light, and (ii) change a characteristic of the reflected light signal for use in determining a physical state of the multi-core optical fiber. The conductive medium can provide a pathway for electrical signals detected at a distal portion of the conductive medium. The conductive medium may be concentric to the cladding, but separate and adjust thereto.

Disclosed in the present invention is a method for automatically measuring and adjusting the refractive index of the cross-section of an optical fiber. The method comprises the following steps: S1, optical fiber alignment; S2, detection of optical signals; S3, automatic compensation for optical fiber fusion splicing; S4, analysis of the optical signals; and S5, automatic adjustment and compensation. Compared with the conventional related art, the automatic compensation technique for optical fiber fusion splicing in the present invention has advantages such as higher quality stability, reduced manual intervention, precise parameter adjustment, rapid response capability and improved production efficiency, and is applicable to production and application in the field of optical fiber communications.

The invention relates to the field of pressure sensors, in particular to a pressure sensor and a processing method, and a chip comprises a silicon substrate, a silicon dioxide dielectric layer, a device layer, a metal electrode and packaging glass. The device layer comprises a silicon carbide single crystal device layer and a silicon device layer; the silicon carbide single crystal device layer is arranged on the silicon device layer; the silicon device layer, the silicon dioxide dielectric layer and the silicon substrate are connected in sequence; the device layer is etched to form a sensitive resistor device layer, an annular sealing region and a micro-channel; the sensitive resistance device layer is isolated from the annular sealing area through the micro-channel; the device layer, the silicon dioxide dielectric layer and the silicon substrate are etched to form a cross beam etching area; the silicon substrate is etched to form a silicon pressure cavity and a beam film; the metal electrode is arranged on the top of the device layer; and the packaging glass anode is bonded at the top of the device layer or the bottom of the silicon substrate so as to solve the problems of low high temperature resistance and low sensitivity of the MEMS pressure sensor.

An apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. The first mating protrusion is to be partially disposed within a first recess formed in a second surface of a photonic integrated circuit (PIC) die when the first surface of the optical interposer opposes the second surface of the PIC die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die. A first portion of an outer surface of the first mating protrusion is to contact a first side wall of the first recess and a second portion of the outer surface of the first mating protrusion is to oppose a second side wall of the first recess such that a second space is to be defined therebetween.

The invention discloses an MEMS device architecture, which comprises a cap layer, a device layer and a substrate layer, the cap layer is bonded with the device layer, the bonded whole is bonded with the substrate layer, the cap layer is manufactured based on a first silicon substrate, the bottom of the cap layer is provided with a cavity structure, and the cap layer is internally provided with a high-deep groove structure. A silicon dioxide film is arranged on the groove wall of the high-deep groove structure, polycrystalline silicon is deposited and filled in the high-deep groove structure, and a silicon dioxide layer is arranged on the upper surface of the first silicon substrate; the device layer is manufactured based on an SOI wafer and comprises a first silicon structure layer composed of top layer silicon, a buried oxide layer and a second silicon structure layer composed of back substrate silicon. The substrate layer comprises a second silicon substrate, a bottom layer cavity is formed in the top face of the second silicon substrate, and exhaust holes are formed in the bottom face of the second silicon substrate. According to the method, deep groove etching, polycrystalline silicon groove filling and bonding technologies are combined, advanced materials such as the SOI wafer and the polyimide layer are utilized, and excellent signal isolation and flexibility of various MEMS IMU applications are achieved.

The invention relates to a light receiving end, which is characterized in that an array lens for coupling emergent light of each channel of a 45-degree optical fiber array into a corresponding channel of an array detector chip is arranged between a 45-degree total reflection surface of a V-shaped groove in the 45-degree optical fiber array and the array detector chip, and the side surface of the array lens is fixed with the side surface of a cover plate in the 45-degree optical fiber array in a bonding manner. The invention discloses an optical receiving end coupling method. The method comprises the following steps of: aligning each channel of a 45-degree optical fiber array with each channel of an array detector chip one by one in an active coupling manner; the array lens is coupled between the 45-degree total reflection surface of the V-shaped groove in the 45-degree optical fiber array and the array detector chip in an active coupling manner, so that light emitted from each channel of the 45-degree optical fiber array is coupled into the corresponding channel of the array detector chip, and when the optimal coupling position is reached, glue dispensing is performed, and the light emitted from each channel of the 45-degree optical fiber array is obtained. And the side surface of the array lens is fixed with the side surface of the cover plate in the 45-degree optical fiber array. The beneficial effects are that the optical receiving end is optimal in performance, highest in yield and low in cost.

An eyepiece includes a planar waveguide having a front surface and a back surface. The eyepiece also includes a grating coupled to the back surface of the planar waveguide and configured to diffract a first portion of the light propagating in the planar waveguide out of a plane of the planar waveguide toward a first direction and to diffract a second portion of the light propagating in the planar waveguide out of the plane of the planar waveguide toward a second direction opposite to the first direction and a wavelength-selective reflector coupled to the front surface of the planar waveguide. The wavelength-selective reflector comprises a multilevel metasurface comprising a plurality of spaced apart protrusions having a pitch and formed of a first optically transmissive material and a second optically transmissive material disposed between the spaced apart protrusions.

The invention relates to the technical field of optical communication, in particular to an optical module heat dissipation structure and a heat dissipation method thereof.The optical module is composed of an upper cover, a base, a PCBA board, an upper heat dissipation assembly and a lower heat dissipation assembly, and the upper heat dissipation assembly and the lower heat dissipation assembly are arranged on the upper side and the lower side of the PCBA board respectively and each composed of a heat conduction board and a heat dissipation device; the heat-conducting plate is arranged between the PCBA plate and the radiator, the first side of the heat-conducting plate is in contact with the PCBA plate, the second side of the heat-conducting plate is in contact with the radiator, and the radiator is internally provided with a radiating main air duct extending in the length direction of the radiator; cooling fins are embedded in the first side and the second side of the radiator, the cooling fins embedded in the second side of the radiator make contact with the corresponding upper cover or base, and the second side of the radiator is the side away from the heat conduction plate. According to the invention, heat generated by components on the PCBA board is transferred and dissipated by adopting a heat dissipation mode of combining dual-channel air-cooled heat dissipation and contact heat dissipation, and the internal temperature of the optical module can be efficiently reduced.

A device includes a spot size converter on a substrate. The substrate includes an optical fiber alignment structure formed thereon. The spot size converter is aligned with the optical fiber alignment structure. The spot size converter includes an oxide layer that has a first refractive index and includes a tapered section such that a first end of the spot size converter is smaller than a second end of the spot size converter. The spot size converter also includes a waveguide core in the oxide layer. The waveguide core is tapered and is smaller at the first end than at the second end of the spot size converter. The spot size converter further includes a cladding layer surrounding the oxide layer, the cladding layer having a second refractive index lower than the first refractive index of the oxide layer.

An apparatus includes a housing capable of being mounted in a rack, and a vertically oriented switch card. The vertically oriented switch card includes one or more vertically oriented application-specific integrated circuits (ASIC) mounted on the vertically oriented switch card. The switch card includes a two-dimensional arrangement of plug ports; each plug port is configured to receive a pluggable optical module. The switch card also includes a two-dimensional arrangement of channel intakes, each channel intake is positioned adjacent to at least one of the plug ports of the two dimensional arrangements of plug ports, each channel intake receives air and directs the received air towards an interior of the housing capable of being mounted in a rack.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

The invention relates to an MEMS mode wafer, an MEMS probe card detection method, an MEMS probe card detection device and a storage medium. The detection method is applied to MEMS wafer detection equipment, and comprises the following steps: loading test configuration parameters of an MEMS probe card to be detected; fixing the MEMS probe card to be tested on a probe seat of test equipment; placing an MEMS mode wafer matched with the to-be-tested MEMS probe card at a preset target position on a test platform of test equipment; the MEMS mode wafer comprises a test point array which is the same as a to-be-tested MEMS wafer corresponding to the to-be-tested MEMS probe card; starting a visual alignment system, and aligning the MEMS probe card to be tested with the MEMS mode wafer; the MEMS probe card to be tested is calibrated; and executing the test task of the MEMS wafer to be tested, and detecting the MEMS probe card to be tested. The test task is automatically executed by using the MEMS mode wafer, and the efficient test of the MEMS probe card is realized.

The invention relates to the technical field of silicon waveguide and optical fiber coupling, and particularly provides an AI-based silicon waveguide-optical fiber mode field self-alignment coupling method and system, and the method comprises the steps: monitoring the strain distribution of a chip in real time through an integrated distributed fiber bragg grating array, and obtaining the light field intensity distribution of a coupling region through cooperation with a near-field optical probe array; constructing a deep space-time convolutional network, and generating a deformation compensation vector and a waveguide reconstruction parameter by an output layer; a nanofluid channel is integrated on the side wall of the waveguide, and the refractive index of liquid is adjusted through an electrowetting effect to realize dynamic broadening of a mode field; and the electrostatic driving micro-beam embedded below the waveguide adjusts the spatial pose of the waveguide according to an instruction of an output layer of the depth space-time convolutional network. The system comprises a light field intensity acquisition module, a convolutional network construction module and a spatial pose adjustment module. According to the method, real-time analysis and prediction are performed, so that system parameters are actively adjusted, and alignment precision and stability are improved.

An optical-electrical substrate for providing electrical and optical connections to a photonic integrated circuit (PIC) includes a glass body with glass optical waveguides along an upper surface, and electrically conductive vias extending through a portion of the glass body from an intermediate surface to a lower surface. The intermediate surface is arranged at an elevation positioned between the upper and lower surfaces, and may optionally support redistribution layers and an electrical integrated circuit. An optical-electrical substrate may be fabricated by defining glass optical waveguides along an upper surface of a glass body, and forming electrically conductive vias through the glass body from the intermediate surface to the lower surface. A connection method includes registering a PIC with an optical-electrical substrate as described herein; heating bonding bumps arranged between the PIC and the intermediate surface; and providing optically transmissive paths between the PIC and glass optical waveguides of the substrate.

This optical connector comprises: a plurality of optical fibers; a ferrule having a plurality of fiber holes through which the plurality of optical fibers are inserted, two positioning holes, and a connection end surface in which the plurality of fiber holes and the two positioning holes are opened; and a housing for holding the ferrule. The connection end surface is inclined with respect to a virtual plane perpendicular to a longitudinal direction of the plurality of fiber holes when viewed from a juxtaposing direction in which the two positioning holes are arranged. The housing has a housing-side contact surface, and the ferrule has a ferrule-side contact surface that limits the amount of protrusion of the ferrule from the housing by coming into contact with the housing-side contact surface. In a state in which the housing-side contact surface and the ferrule-side contact surface are in contact with each other, the ferrule is swingable about a swing center axis with respect to the housing. The swing center axis is located at a position at which the housing-side contact surface and the ferrule-side contact surface are in contact with each other, and extends in an orthogonal direction that is orthogonal to both the longitudinal direction and the juxtaposing direction.

The invention discloses an MEMS thermal flow sensor based on a glass film structure and a preparation method of the MEMS thermal flow sensor. The sensor comprises a glass inner silicon substrate, a back cavity, a silicon through column, a heating resistor, a temperature measurement resistor, an environment temperature measurement resistor, a chromium adhesion layer, a PAD port and a silicon nitride protection layer. Wherein the heating resistor is located in the center, and the temperature measuring resistors are symmetrically distributed on two sides of the heating resistor; the back cavity is located on the back of the glass inner silicon substrate, and the heating resistor, the temperature measuring resistor and the environment temperature measuring resistor lead a PAD port to the back of the glass inner silicon substrate through a silicon through column. A thermal temperature difference principle is adopted, and upstream and downstream temperature measuring resistors form a Wheatstone bridge. When the flow velocity is not zero, the Wheatstone bridge outputs, and the larger the flow velocity is, the larger the output is. Based on the glass and silicon composite substrate, the suspension film structure is formed through the silicon etching process, transmission of heat to the substrate is greatly reduced, and the heat utilization rate is increased.

Methods, apparatuses, and systems associated with a sample testing device are provided. For example, an example sample testing device may include a substrate layer defining a bottom surface of the sample testing device, as well as a waveguide disposed on the substrate layer and includes at least one reference channel and at least one sample channel.