6189 results about "Wafer" patented technology

Methods are provided for deriving a partially continuous dependency of metrology metric(s) on recipe parameter(s), analyzing the derived dependency, determining a metrology recipe according to the analysis, and conducting metrology measurement(s) according to the determined recipe. The dependency may be analyzed in form of a landscape such as a sensitivity landscape in which regions of low sensitivity and/or points or contours of low or zero inaccuracy are detected, analytically, numerically or experimentally, and used to configure parameters of measurement, hardware and targets to achieve high measurement accuracy. Process variation is analyzed in terms of its effects on the sensitivity landscape, and these effects are used to characterize the process variation further, to optimize the measurements and make the metrology both more robust to inaccuracy sources and more flexible with respect to different targets on the wafer and available measurement conditions.

A method of processing a substrate on which a layer of photoresist has been applied, the method involving: exposing the layer of photoresist to radiation that carries spatial information to generate exposure-induced changes in the layer of photoresist that form a pattern having one or more features; and before developing the exposed photoresist, interferometrically obtaining measurements of the pattern in the exposed layer of photoresist for determining at least one of (1) locations of the one or more features of the pattern and (2) magnitudes of the exposure-induced changes.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

The invention discloses a graphite bearing disc used for a production process of an LED epitaxial wafer. The graphite bearing disc comprises a plurality of wafer grooves formed in the bearing disc, wherein the wafer grooves are used for containing epitaxial wafer substrates. The graphite bearing disc is characterized in that a convex part structure is arranged on a central region of the bearing disc so that the vortex area of the central region of the bearing disc in an epitaxial production process can be reduced, and the problem that the light intensity of a partial region, which is formed towards the center of a shaft of the bearing disc, of the epitaxial wafer of an inner ring is low can be solved; and therefore, the brightness uniformity of the inner ring is improved and the whole uniformity of the brightness of the epitaxial wafers of the inner and outer rings is improved.

The invention provides a production method of 50-micron ultrathin chips. An adhesive film is pasted to the surface of a wafer graph, and a film cutter is inclined to cut the film; the wafer is thinned through coarse grinding, fine grinding, polishing and eroding, four feeding speeds exist only in the coarse grinding, and three speeds exist in the polishing; a film is tightly stretched on the back face of the thinned wafer, the adhesive film on the front face of the wafer is torn off, and feeding and discharging are performed automatically; scribing is performed with a step mode and an anti-cracking scribing process of the double-shaft scribing technology, and production of the 50-microns ultrathin chips is completed. The production method can guarantee the processing capability of a back-end process along with increasing of sizes of the chips, reduce the quality abnormities that in the scribing process, the surfaces of the chips are cracked and the back faces are stretched to be broken, reduce the resistance borne by a scribing cutter in the cutting process, effectively solve the quality problem that the chips are cracked and stretched to be broken, achieve the processing of the ultrathin chips and provide technical preparation for the development direction of high-density, high-performance, light and thin IC packaging products.

The invention provides a silicon-glass-silicon structure surface acoustic wave temperature and pressure integrated sensor and preparation thereof, and relates to a sensor. The sensor has a silicon-glass-silicon sandwich structure. A pressure sensor is integrated on a silicon-based pressure-sensitive film of the upper layer. A temperature sensor is integrated on a silicon substrate of the bottom part. The silicon substrate and the upper layer are isolated by a glass framework. The manufacturing method comprises the steps that the silicon substrate is prepared; the silicon-based pressure-sensitive film is prepared; a sandwich structure cavity is formed by the silicon substrate, the silicon-based pressure-sensitive film and the glass framework through bonding; the substrate layer of an SOI wafer is etched with the buried silicon oxide layer in the SOI wafer acting as a corrosion auto-stop layer so that the device layer of the SOI wafer is remained to act as the silicon-based pressure-sensitive film of the pressure sensor; four electrode regions are formed on the silicon-based pressure-sensitive film through etching, and the etching regions are arranged above the electrode regions of the temperature sensor and the pressure sensor with the bonding interface of the glass framework and the silicon-based pressure-sensitive film and the inlaid electrodes in the silicon-based pressure-sensitive film acting as the etching stop layer respectively; and array devices are split and then single devices are obtained.

A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.

The invention provides a wafer three-dimensional integrated lead wire process and a structure thereof. The process can be applied to a wafer three-dimensional integration process for the wafers of a three-dimensional memory. A dielectric layer 13 is arranged between a first wafer 11 and a three-dimensional memory device 14 and a contact hole 15 for metal interconnection is configured to be in contact with the dielectric layer 13. The invention provides a new lead wire process, making it possible to pass through a thick device layer for wire leading on a backside.

The invention relates to a laser machining method for matching with a light-emitting diode (LED) inner cutting process. According to the laser machining method, metal reflecting films or distributed Bragg reflecting films or double-layer reflecting films which consist of the metal reflecting films and the distributed Bragg reflecting films are distributed on the reverse side of a wafer; laser is focused to the reflecting films, and laser beams and the wafer make relative motion, so that the single-layer reflecting films or one layer or two layers of double-layer reflecting films are removed by gasifying to form a groove; a central line of the groove aligns with that of a cutting way on the front of the wafer; and in the inner cutting process, inner cutting laser is focused inside the wafer by the groove to form an internal crack area and form a linear array along the cutting direction, and pressure is exerted on the cutting way on the front of the wafer, so that the wafer is cracked along the set cutting direction. The method is matched with the inner cutting process to cut the LED wafer, so the method has the characteristics of high speed, high accuracy, small damage to the surface of sapphire and the like.

The invention discloses an integrated circuit defect image recognition and classification system based on a fusion deep learning model, and provides a mode of using a fusion model based on a deep convolutional neural network (CNN) to carry out on-line automatic recognition and classification on defect images of a wafer so as to timely detect the change of the number of various defects of the wafer. The core mechanism of the method is a defect image feature extraction method constructed by two deep learning models integrated into a learning mechanism. According to the deep CNN fusion model, a Combined3 defect image classification model is constructed on the basis of two frameworks of SE _ Inception _ V4 and SE _ Inception _ ResNet _ V2; and a sequence model optimization (SMBO) algorithm isutilized to perform hyper-parameter optimization on the fusion depth CNN recognition model, so that the model recognition precision is improved. Increasing automation levels. And the identification cost is reduced because an engineer is replaced by the AI model, and the working efficiency is greatly improved. Based on a real-time identification and classification result, engineers can count defectdata and search reasons in time, so that process parameters are adjusted, and the yield is improved.

This invention relates to a system and a method for washing semiconductor wafer with high efficient ozone water. The method mainly utilizes super-pure water and gaseous phase ozone to carry out gas-liquid resolution and combination, concentration dynamic analysis and information feed-control containing the production of high density large flow liquid-phase ozone water for cleaning the solution, wafer, dynamic monitor to the density of ozone and additives in the solution and water temperature and analysis and feeding to the monitor values. The system includes a liquid-phase ozone generating unit, a storage tank or a washing tank, an additive supplied unit, a monitor unit and an automatic feed/control unit.

The invention discloses a chemical mechanical polishing (CMP) device. The chemical mechanical polishing device comprises a polishing table, a polishing cushion, a polishing heat, a clamping ring, a first radiating device and a second radiating device, wherein the polishing cushion is fixed on the polishing table; the end face of the polishing head is matched with the polishing cushion for grinding a wafer; the clamping ring is arranged on the edge of the end face of the polishing head for clamping the wafer; the first radiating device is arranged around the outer side of the polishing head; and the second radiating device is arranged between the polishing cushion and the polishing table. The invention further provides a chemical polishing system. Due to the adoption of the technical scheme provided by the invention, the requirement of keeping the polishing temperature constant in a chemical mechanical polishing process which cannot be realized by using the conventional CMP device is met, the phenomenon of non-uniform removing thickness of a CMP wafer is avoided, and the rejection rate of the wafer is reduced.