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55 results about "Device degradation" patented technology

The degradation device is designed to deliver separated solid material to the degradation device, in particular to the reactor device, for renewed degradation as substrate. well as methods for the fabrication of implantable degradable devices of the present invention which contain one or more degradable biopolymer fibers.

Hot-carrier device degradation modeling and extraction methodologies

The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added. In an exemplary embodiment, only devices with minimum channel length have degraded models constructed. The present invention also allows the degradation of one device parameter to be determined based on an age value derived from another parameter. In yet another aspect, a degraded device is modeled as a fresh device with a voltage source connected to a terminal.
Owner:CADENCE DESIGN SYST INC

Hot carrier circuit reliability simulation

The present invention is directed to a number of improvements in methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects. A plurality of different circuit stress times can be simulated within a single run. Different aging criteria may be used for different circuit blocks, circuit block types, devices, device models and device types. The user may specify the degradation of selected circuit blocks, circuit block types, devices, device models and device types independently of the simulation. Device degradation can be characterized in tables. Continuous degradation levels can be quantized. Techniques are also described for representing the aged device in the netlist as the fresh device augmented with a plurality of independent current sources connected between its terminals to mimic the effects of aging in the device. The use of device model cards with age parameters is also described. To further improve the circuit reliability simulation, a gradual or multi-step aging is used instead of the standard one step aging process. Many of these features can be embedded within the circuit simulator. A user data interface is also presented to implement these techniques and further allow users to enter their device models not presented in the simulator. For example, a proprietary model of, say, the substrate current in an NMOS could used be with a SPICE simulator employing a different model to simulate the aging of the circuit.
Owner:CADENCE DESIGN SYST INC

Hot-Carrier Device Degradation Modeling and Extraction Methodologies

The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added. In an exemplary embodiment, only devices with minimum channel length have degraded models constructed. The present invention also allows the degradation of one device parameter to be determined based on an age value derived from another parameter. In yet another aspect, a degraded device is modeled as a fresh device with a voltage source connected to a terminal.
Owner:LIU ZHIHONG +5

Numerical simulation method and system of MOS device inhomogeneous interface degeneration electric charges

The invention is applicable to the technical field of MOS devices, and provides a numerical simulation method and system of MOS device inhomogeneous interface degradation electric charges. The ground floor of software is modified, a functional model for calculating the number of the inhomogeneous interface electric charges Nit (x,t) is added, and therefore numerical simulation of influences of the inhomogeneous interface electric charges on device performance can be achieved. An interface electric charge degradation model interface is further added for achieving the numerical simulation method, and therefore the numerical simulation on the inhomogeneous interface electric charges caused by various effects can be achieved. A device parameter extraction interface is further added for achieving the numerical simulation method, and device parameters comprising threshold voltage, output characteristics, transconductance, electrons, hole concentration distribution, potential distribution, electric field distribution and the like can be extracted. According to a degradation model of an NBTI, unique change rules of the pure polarization NBTI effect under HCI stress can be disclosed, the relationship between device degradation and the service life is deeply understood, the process design is guided, and the development of reliability studying of integrated circuits can be further promoted.
Owner:SHENZHEN UNIV
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