664results about How to "Reduce electric field strength" patented technology

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a "keyhole" shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

In an active matrix display device, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shaped semiconductor region, is used as a switching element. Each of the TFT have offset regions and lightly doped drain (LDD) regions. Then, by supplying a selection signal to the gate lines, the TFTs are operated, thereby writing data to the pixel, while a suitable voltage is supplied to the capacitance line, a channel is formed thereunder and it becomes a capacitor. Thus the amount of discharge from the pixel electrode is reduced by the capacitor.

The invention discloses a quantum dot light emitting diode and a preparation method thereof. The quantum dot light emitting diode comprises a substrate, an anode, a hole transport layer, a quantum dot light emitting layer, an electron transport layer and a cathode in sequence from bottom to top, wherein the materials of the quantum dot light emitting layer include quantum dots and an amorphous insulating compound. The quantum dot light emitting layer is prepared by forming a film through spin coating of solution of the amorphous insulating compound containing the quantum dots, in order to weaken the electric field intensity at the quantum dot light emitting layer. Therefore, the possibility of electron recombination is improved while the electron and hole injection barriers are reduced, and thus, the efficiency and service life of QLED devices are increased effectively.

A printing apparatus has a series of inkjet print heads spaced from one another in a transport direction. A continuous belt driven around a roller system is used to feed sheet media successively to the print heads so that a partial image printed by one print head is overprinted at a subsequent print head with registration of the partial images. A sheet medium is caused to become electrostatically tacked to the belt by passing the sheet past a charging device. Movement of the belt is tracked by a tracking sub-system and operation of the print heads is coordinated with the tracked belt movement to achieve precise registration of the partial images.

This invention relates to a panel display with doped-polysilicon field emission cathode array structure and its process technology, in which, the display includes a sealed vacuum cavity composed of a cathode panel, an anode panel and surrounding glasses, anode conduction strips etched on the anode panel and fluorescence powder layer on the conduction strips, a supporting wall and getter attached elements, in which, a doped polysilicon field emission cathode array structure is prepared on the cathode panel to reduce the distance between the cathode and the grating, control the working voltage of the grating and reduce the current of the control grating.

A nonvolatile semiconductor memory has memory cells (1) each having an insulated-gate FET that has an information storage part. A semiconductor region (27) is formed at the surface of a channel region of each memory cell. The semiconductor region has the same conductivity type as a channel conductivity type and functions to decrease the strength of an electric field at the surface of the channel region. If the insulated-gate FET is of an n-channel type, the semiconductor region is of an n-type. The semiconductor region suppresses threshold voltage variations among the insulated-gate FETs of the memory cells and prevents soft-writing in the memory cells.

A memory cell patterned as a trench transistor is provided with a first gate electrode (4) as auxiliary gate for source-side injection and a second gate electrode (5) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence (10) provided for charge trapping and comprising a storage layer (12) between boundary layers (11, 13). The first gate electrode (4) and the second gate electrode (5) are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence (10). Source/drain regions (3) are arranged on the top side laterally with respect to the trenches. Word lines (6), source/drain lines and control gate lines are present for the electrical driving.

The invention discloses an edge terminal structure of a high-voltage power semiconductor device. The edge terminal structure comprises a plurality of field limiting rings which wind the power semiconductor device and have a conduction type opposite to that of a substrate; one or two side of each field limiting ring is provided with a doped region which has a conduction type the same as that of the field limiting ring and the doping concentration smaller than that of the field limiting ring; the field limiting rings are coated with field plates; and the field limiting rings and the field plates are separated by silicon dioxide layers. The material of the field plate can be selected from copper, aluminum, polysilicon, oxygen-doped polysilicon and the like. The doped regions with lower concentration are added around the conventional field limiting rings, so the intensity of electric field lines of an edge cellular can be effectively reduced, the electric field strength borne by the edge cellular is reduced, the breakdown voltage is improved, the area efficiency of the edge terminal structure is effectively improved, the chip area is saved, and the chip cost is reduced.

A pad electrode of a high electron mobility transistor is formed solely of a pad metal layer without providing a gate metal layer. A high concentration impurity region is provided below the pad electrode, and the pad electrode is directly contacted to a substrate. Predetermined isolation is ensured by the high concentration impurity region. Accordingly, in a structure not requiring a nitride film as similar to the conventional art, it is possible to avoid defects upon wire boding attributing to hardening of the gate metal layer. Therefore, even in the case of a buried gate electrode structure for enhancing characteristics of the high electron mobility transistor, it is possible to enhance reliability and yields.

The invention is concerned with the manufacture method of the ditch groove power semiconductor device. It is: provides the materials of the basal; forms the first electric transmit epitaxy layer on the basal; forms the second electric transmit zone and the ditch groove inside the epitaxy layer; forms the ebb first electric transmit area and the medium layer with the ditch groove; and then, forms the electric transmit area within the medium layer; forms the first electric transmit source area on the surface of the second electric transmit area; forms the second electric transmit contact area with higher doping PH indicator on the second electric transmit zone surface; forms the passivation layer cap on the top of the ditch groove which must with the medium layer and the electric transmit area; forms the diffusion protecting layer on the surface of the source area and the contact area; finally, forms the structure surface with good electric connection. The invention can control the threshold voltage of the device and improves the breakdown strength of the oxide layer of the device bottom area, and improves its electric connection reliability with no extra cover film printing plate and complex method request.

A manufacturing method of a semiconductor device comprises forming a semiconductor substrate including an active region and an element isolation film, forming a first recess on the semiconductor substrate, forming an oxide film on a sidewall of the first recess, forming a second recess by etching a lower part of the first recess, and forming a gate in a lower part of the second recess.

A laterally double diffused metal oxide semiconductor transistor of an N-shaped silicon-on-insulator (SOI) comprises a semiconductor substrate. A buried oxide is arranged on the semiconductor substrate, an N-shaped doped semiconductor drift region is arranged on the buried oxide and a P-shaped well region is arranged above the N-shaped doped semiconductor drift region, and a field oxide, a metal layer, a gate oxide, a polysilicon gate and an oxide layer are arranged on the surface of the transistor. An N-shaped source region and a P-shaped contact region are arranged in a P-shaped well. The transistor is characterized in that the transistor also comprises at least a layer of floating oxide structure which is positioned in the N-shaped doped semiconductor drift region between a drain region and the buried oxide; moreover, a plurality of layers of floating oxide structure are allowed to further optimize the distribution of longitudinal electric fields in the drain region, thereby increasing the entire breakdown voltage of the transistor.

This invention discloses a structure of LED electrode and its manufacturing method. After forming a pn contact surface LED on the baseplate, a layer of silicon oxide is formed around the grain and onthe cut-path part, and deposited by a transparent conductive layer and a layer of Au or AuGe on it, or and opening an open-end at the center; after contacting with heated and alloy formed ohm, a longstrip of Al, Al alloy or Au connecting wire pad is formed at a side of the grain for writing and used as the LED positive electrode, and the negative electrode is formed on the substrate by metal contact. The other structure is that both positive and negative electrodes are on the front with etched pn interface p-type layer, and negative electrode is formed with n-type material and positive electrode with p-type material.

A high-performance semiconductor apparatus which can be easily introduced into the MOS process, reduces the leakage current (electric field strength) between the emitter and the base, and is insusceptible to noise or surge voltage, and a manufacturing method of the semiconductor apparatus. The emitter 111 is formed by performing the ion implantation twice by using the conductive film (109) as a mask. The second emitter area (111b) is formed by ion implantation of a low impurity density impurity ion, and the first emitter area (111a) is formed by ion implantation of a high impurity density impurity ion. As a result, the low impurity density second emitter area is formed in the circumference of the emitter 111, which lowers the electric field strength, and reduces the leakage current. Also the conductive film is connected with the emitter electrode (116), which makes the apparatus insusceptible to noise.

An image displaying device having multiple photosensing devices have successfully suppressed a leakage current from each photosensing device and improved the S/N ratio. In the image displaying device, pixels and photosensing devices are disposed as pairs in a matrix pattern on a substrate. Each of the pixels and each of the photosensing devices are driven independently. Each photosensing device includes a semiconductor layer that is a photoelectric conversion layer connected to at least a first electrode and a second electrode. The contact surfaces of the first and second electrodes with respect to the semiconductor layer are disposed so that their center axes are separated from each other.

The present invention discloses a method for fabricating a buried bit line of a mask ROM. The method includes providing a semiconductor substrate with a photoresist layer, and patterning the photoresist layer to form a photoresist pattern. A first ion implantation process is performed to form a first doped region in the semiconductor substrate not covered by the photoresist pattern. Then, an organic layer is coated on the photoresist pattern and the semiconductor substrate and an etching process is performed to form an organic spacer at two sides of the photoresist pattern. Finally, a second ion implantation process forms a second doped region in the semiconductor substrate not covered by the photoresist pattern and the organic spacer. Finally, the photoresist pattern and the organic spacer are removed.

A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates.