713results about How to "Suppress leakage current" patented technology

The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

A thin film transistor with which oxygen is easily supplied to an oxide semiconductor layer and favorable transistor characteristics are able to be restored and a display unit including the same are provided. The thin film transistor includes sequentially over a substrate a gate electrode, a gate insulting film, an oxide semiconductor layer including a channel region, and a channel protective layer covering the channel region A source electrode and a drain electrode are formed on the oxide semiconductor layer located on both sides of the channel protective layer, and at least one of the source electrode and the drain electrode has an aperture to expose the oxide semiconductor layer.

A P-type MOSFET 120 includes a semiconductor substrate (N-well 102b); a gate insulating film formed on the semiconductor substrate, composed of a high-dielectric-constant film 108 which contains a silicate compound containing a first element selected from the group consisting of Hf, Zr and any of lanthanoids, together with N; a gate electrode formed on the gate insulating film, and is configured by a polysilicon film 114 containing a P-type impurity; and a blocking oxide film 110 formed between the gate insulating film and the gate electrode, blocking a reaction between the first element and the polysilicon film 114, and having a relative dielectric constant of 8 or above.

A photovoltaic device and a manufacturing method thereof are provided. The photovoltaic device includes: a substrate; a first conductive layer formed on the substrate; P layers and N layers alternately formed along a first direction on the first conductive layer; and I layers covering the P layers and the N layers on the first conductive layer, wherein the P layers and the N layers are separated from each other by a first interval, the I layers are formed between the P layers and the N layers that are separated by the first interval, and the P layers, the I layers, and the N layers formed along the first direction form unit cells.

An amorphous-silicon TFT (thin-film-transistor) in an LCD device has a larger channel length at both the edge portions of the channel of the TFT compared to the central portion of the channel by forming chamfers at the corners of the source and drain electrodes. The larger channel length at both the edge portions reduces the leakage current caused by the turned-around light incident onto the channel.

The invention provides a shifting register unit, a drive method thereof, a grid drive circuit and a display device. The shifting register unit comprises a first pull-up node control unit, a second pull-up node control unit, a first pull-down node control unit, a second pull-down node control unit, a grid drive signal output unit and a carry signal output unit. The second pull-up node control unit is controlled by a first clock signal to control the potential of a pull-up node to be first potential at the pull-down keeping stage. The first pull-down node control unit is controlled by the first clock signal to control the potential of a pull-down node to be second potential at the pull-down keeping stage. The grid drive signal output unit is controlled by the pull-up node and the pull-down node to control a grid drive signal output end to output a grid drive signal. The carry signal output unit is controlled by the pull-up node and the pull-down node to control a carry signal output end to output a carry signal. The problems that under long-time or high-temperature reliability work conditions, the threshold voltage of a thin film transistor is greatly drifted and the response speed is low are solved.

A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiO₂ layer formed thereon, and a gate electrode 15 formed on the insulation structure. Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.

A multilayer ceramic capacitor has a laminate comprising dielectric layers stacked alternately with internal electrode layers of different polarities, wherein: the dielectric layers contain ceramic grains whose primary component is BaTiO₃; the ceramic grains contain at least one type of donor element (D) selected from the group that includes Nb, Mo, Ta, and W, and at least one type of acceptor element (A) selected from the group that includes Mg and Mn; and the ratio of the concentration of the donor element (D) and that of the acceptor element (A) (D/A) is greater than 1 at the center parts of the ceramic grains, while the D/A ratio is less than 1 at the outer edge parts of the ceramic grains (if A=0, then D/A=∞ and D=A=0 never occurs).

The embodiment of the invention discloses a display panel, a driving method and a display device. The display panel comprises a substrate base plate; a plurality of sub-pixels positioned on one side of the substrate base plate; the plurality of sub-pixels being arranged in an array; each sub-pixel comprising a pixel driving circuit and a light-emitting element; a pixel driving circuit, comprisingan initialization transistor and a driving transistor, and the initialization transistor and the driving transistor each comprising a first electrode, a second electrode and a grid electrode; a firstelectrode of the initialization transistor being electrically connected with a grid electrode of the driving transistor, and the driving transistor being used for providing driving current for the light-emitting element; and at least one switch module. The second electrodes of the initialization transistors of the at least two sub-pixels are connected with the output end of the same switch module.The input end of the switch module is electrically connected with the initialization signal end. The switch module is used for transmitting an initialization signal to the second electrode of the initialization transistor. The problem that the gate voltage of a driving transistor is unstable due to electric leakage of an initialization transistor can be solved, and the display effect is improved.

A piezoelectric element comprises a piezoelectric layer and an electrode provided to the piezoelectric layer. The piezoelectric layer is made of complex oxide having a Perovskite-type structure containing bismuth and iron, and the complex oxide includes at least one kind of a first doping element selected from the group consisting of sodium, potassium, calcium, strontium and barium and a second doping element formed from cerium.

In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

In view of micronizing semiconductor device and of suppressing current leakage in a shared contact allowing contact between a gate electrode and an impurity-diffused region, a semiconductor device 100 includes a first gate electrode 108, a fourth source/drain region 114b, and a shared contact electrically connecting the both, wherein in a section taken along the gate length direction, the first gate electrode 108 and the fourth source/drain region 114b are disposed as being apart from each other, an element-isolating insulating film 102 is formed over the entire surface of a semiconductor substrate 160 exposed therebetween, and the distance between the first gate electrode 108 and the fourth source/drain region 114b is made substantially equal to the width of the sidewall formed on the side face of the first gate electrode 108, when viewed in another section taken along the gate length direction.

A field-effect transistor includes a first semiconductor layer formed on a substrate, and a second semiconductor layer. The first semiconductor layer has a containing region provided as an isolation region which contains non-conductive impurities, and a non-containing region which contains no non-conductive impurities. A first region is defined by a vicinity of a portion of the interface between the containing region and the non-containing region, the portion of the interface being below a gate electrode, the vicinity including the portion of the interface and being included in the containing region. The second semiconductor layer includes a second region which is located directly above the first region. The concentration of the non-conductive impurities of the second region is lower than that of the first region.

In a manufacturing process of a display device, hydrogenation in an I layer of photodiodes D1 and D2 is progressed less than that in a channel portion of a pixel TFT, and a defect density due to dangling bonds not terminated in the I layer of the photodiodes D1 and D2 is made higher than a defect density in the channel portion of the pixel TFT. Thus, while suppressing a leakage current of the pixel TFT, the sensitivity of the photodiodes D1 and D2 to light is improved. Moreover, a gate electrode is provided above an i region of a pin-type optical sensor diode with an insulating film interposed therebetween. Thus, a gate voltage can control a threshold of a bias voltage when a current starts to flow into the optical sensor diode and a leakage current is prevented from flowing into the optical sensor diode.

The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a p-type nitride layer formed on the nitride semiconductor layer between the source and drain electrodes; an n-type nitride layer formed on the p-type nitride layer; and a gate electrode formed between the source and drain electrodes to be close to the source electrode and in contact with the n-type nitride layer so that a source-side sidewall thereof is aligned with source-side sidewalls of the p-type and n-type nitride layers is provided. Further, a method of manufacturing a nitride semiconductor device is provided.

An organic electroluminescence device including: an anode; a cathode; two or more emitting units that are disposed between the anode and the cathode, each unit having an emitting layer; and a charge-generating layer that is disposed between the emitting units, wherein the charge-generating layer includes an N layer nearer to the anode and a P layer nearer to the cathode, and the N layer includes a compound represented by the following formula (I) or (II):

A developing apparatus includes a developer carrying member, disposed opposite to an image bearing member, for carrying developer which is caused to jump from the developer carrying member to the image bearing member to develop an electrostatic latent image formed on said image bearing member by creating an oscillation electric field between the image bearing member and the developer carrying member at an opposing portion where the image bearing member and the developer carrying member are opposed to each other; and a jumping developer regulation member for regulating an area in which the developer is caused to jump in the opposing portion. The jumping developer regulation member is disposed apart from the developer carried by the developer carrying member and is an insulating member or an electrically floating member.