31results about How to "Increase circuit speed" patented technology

A solid-state imaging device includes a reference-signal generating unit that generates plural kinds of reference signals for converting an analog pixel signal into digital data, a reference-signal selecting unit that selects any one of the plural kinds of reference signals, a comparing unit that compares the pixel signal and the selected reference signal, and a count unit that performs count processing in parallel with comparison processing in the comparing unit and stores a count value at a point when the comparison processing is completed. The count unit decides digital data of the pixel signal in a 1 LSB step by storing a count value at a point when the comparison processing is completed for any one of the plural kinds of reference signals and correcting the stored count value on the basis of results of the comparison processing for respective remaining reference signals of the plural kinds of reference signals.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C³MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C³MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element (“LE”) with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block (“LAB”), each LE in effect lends one look-up table (“LUT”) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.

A spread spectrum clock generation circuit capable of further reducing the electromagnetic wave radiation with a simple configuration has been disclosed and, particularly in a spread spectrum clock generation circuit using a current control oscillator (ICO), a differential signal to which a spread spectrum modulation signal, the period or amplitude of which changes, is added is generated, and the differential signal is applied to the ICO and a clock is generated.

A data store and method of storing data is disclosed that comprises: an input for receiving a data value; at least one storage cell comprising: a feedback loop for storing the data value; an output for outputting the stored data value; the feedback loop receiving a higher voltage and a lower voltage as power supply, the data store further comprising: a voltage supply for powering the data store, the voltage supply outputting a high voltage level and a low voltage level; write assist circuitry arranged between the voltage supply and the at least one storage cell, the write assist circuitry being responsive to a pulse signal to provide a discharge path between the high voltage level and a lower voltage level and thereby generate a reduced internal voltage level from the high voltage level for a period dependent on a width of the pulse signal, the reduced internal voltage level being lower than the high voltage level, such that when powered the feedback loop receives the reduced internal voltage level as the higher voltage for a period determined by the pulse width and the high voltage level at other times; and pulse signal generation circuitry for generating said pulse signal.

A memory device, current sense amplifier and method of operating the same are disclosed herein. In accordance with one embodiment, the current sense amplifier circuit may include a pair of cross-coupled transistors, a pair of output nodes and a first pair of load transistors. The pair of cross-coupled transistors may be coupled for receiving a pair of differential currents and for generating a pair of differential voltages, which may then be supplied to the pair of output nodes. The first pair of load transistors may have mutually-connected gate terminals, mutually-connected drain terminals, and a source terminal coupled to a different one of the output nodes. In a unique aspect of the invention, an equalization transistor may coupled between the pair of output nodes for equalizing the pair of differential voltages for a predetermined amount of time at the beginning of a sense cycle. As such, the equalization transistor may be added to prevent the current sense amplifier circuit from generating erroneous results during the predetermined time period.

A voltage level shifter for receiving a digital signal from a first voltage domain and converting said signal to a digital signal in a second voltage domain is disclosed. The voltage level shifter comprises: an input for receiving said digital signal from said first voltage domain; a device connected to said input of said voltage level shifter for receiving said digital signal from said first voltage domain and for outputting a digital signal in said second voltage domain, said device being powered by said second voltage domain; a first switching device arranged to connect a high level voltage source of said second domain to an input of said device in response to said input digital signal having a high level and to isolate said high level voltage source of said second domain from said input of said device in response to said input digital signal having a low level; and a second switching device arranged between said voltage level shifter input and said input of said device for inhibiting current flow from said high level voltage source of said second domain to said voltage level shifter input in response to a high level signal at said voltage level shifter input and for allowing current flow in both directions between said voltage level shifter input and said input of said device in response to said voltage level shifter input having a low level signal.

A BGA package comprises a chip with an array pad design disposed on the top surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof. The bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. All of the power supply pads and ground pads are adjacent to one another and designed in the outer row of the bonding pads, and the I/O pads are designed in the outer row, the middle row and the inner row of the bonding pads. The outer row, middle row, and the inner row of the bonding pads are electrically connected to the substrate through three tiers of bonding wires with different loop height, respectively.

A packaging approach reduces the overall footprint for interconnecting multiple semiconductor devices. In an embodiment, a processor mounts onto the center of a substrate with flexible appendages and memory components mount to the flexible appendages. The appendages fold over the processor to produce a processor/memory module. The processor/memory module occupies less area on the main printed circuit board than the laterally interconnected processor and memory devices would occupy.

An apparatus for controlling discrete data in a disk overwrite area or a power calibration area comprises a signal-processing unit, an address-processing unit, a control signal-processing unit, a clock recovery circuit, a signal-processing unit parameter control unit, and a clock recovery circuit parameter control unit, wherein the control signal-processing unit uses a message produced by a data on the disc to determine the control signals such as hold, load, or increasing bandwidth for holding, loading, and increasing the bandwidth of the parameters for processing the related circuits (such as the circuit of the signal-processing unit or the clock recovery circuit) of the discrete data produced between the two data clusters, so as to increase the convergent speed of the circuits for assuring the accuracy of reading data.

The present invention relates to CML(Current Mode Logic)-type input driving method and tunneling diode logic using MOBILE(Monostable Nistable transition Logic Element) configuration, as kinds of very high-speed digital logic circuits. The objectives of the present invention are to improve the disadvantage of MOBILE circuit configuration that is an existing tunneling diode logic, and at the same time provide new MOBILE based logic functions. Wherein, the difficulty for input voltage adjustment is resolved by replacing the input part with a CML input driving gate, and speed problem due to transistor is resolved. Moreover, a plurality of logic functions such as inverted return-to-zero D flip-flop, non-inverted return-to-zero D flip-flop, return-to-zero OR gate, return-to-zero D flip-flop generating differential output, and optical flip-flop are implemented.

A CNFET based pulse generator, including a first Carbon Nanotube Field Effect Transistor (CNFET), a second CNFET, a third CNFET, a fourth CNFET, a fifth CNFET, a sixth CNFET, a seventh CNFET, an eighth CNFET, a ninth CNFET, a tenth CNFET, an eleventh CNFET, a twelfth CNFET, a thirteenth CNFET, and a fourteenth CNFET. The first CNFET, the third CNFET, the fifth CNFET, the seventh CNFET, the tenth CNFET, the twelfth CNFET, and the thirteenth CNFET are P-type CNFETs. The second CNFET, the fourth CNFET, the sixth CNFET, the eighth CNFET, the ninth CNFET, the eleventh CNFET, and the fourteenth CNFET are N-type CNFETs.

Signals can be superimposed on optical phase even when low-coherency light is used, and a bit rate and a signal coding format similar to those used in ordinary optical communications can be used. A transmitter includes an asymmetric interferometer or an antisqueezed light generator to convert a train of single pulses into a train of dual pulses. A receiver also includes an asymmetric interferometer that provides the same delay time as that between the dual pulses. The receiver allows pulses originating in the same light source to interfere, so that signals can be superimposed on the phase even when a low-coherency light source is used. The delay time (optical path length difference) provided in the asymmetric interferometer is set to be longer than half the period of the pulses outputted from the optical pulse source. In the transmitter, two pulses are modulated as a unit, one of the two pulses being the rear pulse of a pair of dual pulses and the other pulse being the front pulse of the next pair of dual pulses. In the receiver, a balanced detector receives the modulated pulses, and the balanced detector only outputs interference pulses but does not output non-interference pulses.

The invention discloses a CMOS full adder. The CMOS full adder comprises more than one PMOS field effect transistor, more than one NMOS field effect transistor and a connecting circuit. The connectingcircuit is used for connecting the more than one PMOS field effect transistor and the more than one NMOS field effect transistor. The connecting circuit is configured to reduce a threshold voltage ofat least one of the more than one PMOS field effect transistor and the more than one NMOS field effect transistor. The invention further discloses a multi-bit full adder. The multi-bit full adder comprises a plurality of CMOS full adders. The CMOS full adder and the multi-bit full adder can effectively reduce the ascending, descending and propagation delay conditions of the device, thereby improving the circuit speed.

The present invention discloses a method for preparing a novel material layer structure of a circuit board, comprising the steps of: (1) combining a film with a copper layer to form an FCCL single-sided board; (2) applying a semi-cured functional material layer on a back side of the film of the FCCL single-sided board, wherein the semi-cured functional material layer is an MPI film, an LCP film, a TFP film, a PTFE film, a copper ion migration resistant film, an LDK high-frequency functional adhesive, a copper ion migration resistant adhesive, or a mixture of the LDK high-frequency functional adhesive and the copper ion migration resistant adhesive to form a novel material layer structure for a circuit board. An article prepared by performing the above methods is also disclosed. The prepared novel material layer structure of the circuit board has high-frequency characteristics and/or copper ion migration resistance, and can be used as an integral structure. In the circuit board manufacturing process, it can be manufactured as the circuit board manufacturing material to be different circuit board structures, which brings great convenience for subsequent circuit board manufacturing and simplifies the manufacturing process.

Provided is a method for producing a self-aligned metal oxide thin-film transistor (TFT) component, which comprises: selecting a substrate (11), and preparing a gate electrode (12) on the substrate (11); arranging an insulation layer (13), a transparent electrode layer (14) and photoresist (15) in sequence on the gate electrode (12); using the gate electrode (12) as a mask, and exposing from a back of the substrate (11) to form source and drain electrodes (141, 142) that are aligned with the gate electrode (12); depositing a metal oxide semiconductor layer (17) on the transparent electrode layer (14); etching the semiconductor layer (17) and the source and drain electrodes (141, 142) to make outer ends of the source and drain electrodes (141, 142) come out of the metal oxide semiconductor layer; depositing a passivation layer (18), and leading out the source and drain electrodes (141, 142). The component uses a transparent conductor as an electrode layer, uses a bottom gate as a mask to perform back exposure, and etches the source and drain electrodes, which implements self-alignment between the source and drain electrodes and the gate electrode, effectively reduces parasitic capacitance, and improves component performance. The component is in a bottom gate and bottom contact structure. No etching blocking layer needs to be fabricated, simplifying a process, reducing usage of photolithographic masks, improving efficiency, and improving electrical characteristics of the component.

This invention relates to a phase-lock loop and its applied loop filter including a first resistor, a first capacitor and an amplifier with a specific gain value, among which, the amplifier has an input end coupled to the input and output ends of the loop filter by the first resistor, the amplifier has an output end coupled to the input end of the amplifier via the first capacitor.