5results about How to "Improve conversion speed" patented technology

The invention discloses a reference power supply fluctuation stabilization method for a successive approximation analog-to-digital converter, which is applied to a sectional successive approximation analog-to-digital converter. Designing a linear charge compensation circuit, and improving a reference power supply circuit of the fine quantization ADC; the reference power supply circuit of the fine quantization ADC comprises a buffer and a linear charge compensation circuit. The linear charge compensation circuit comprises a binary capacitor array used for providing compensation charges and a control circuit, serves as an auxiliary power supply circuit and is used for rapidly stabilizing reference power supply fluctuation generated by most significant bit switching of the fine quantization ADC before comparison of least significant bits, and the conversion precision of fine quantization is improved. According to the invention, the influence of the reference power supply fluctuation on the conversion precision can be reduced, and the conversion speed and the conversion precision of the SAR ADC can be improved; and meanwhile, the requirements on a high-power-consumption on-chip reference power supply driver and a large-area on-chip decoupling capacitor are greatly reduced, and the power consumption and the area overhead of the SAR ADC are reduced.

The application provides a folded cascode amplifier, an integrated circuit, a chip and an electronic device. The folded cascode amplifier comprises a bias circuit configured to provide a bias current according to a bias voltage, a first input differential unit and a second input differential unit arranged symmetrically, a folded cascode unit, and a fifth group of current mirrors connected to the folded cascode unit. The folded cascode unit comprises a first group of cascode tubes and a second group of cascode tubes, and a first group of current mirrors to a fourth group of current mirrors. The first group of cascode tubes comprises a first output transistor and a first load current tube connected in series, the second group of cascode tubes comprises a second output transistor and a second load current tube connected in series, and the first group of current mirrors multiplexes the first load current tube, and the fourth group of current mirrors multiplexes the second load current tube. The folded cascode amplifier improves the transconductance, the slew rate, the conversion rate and the gain-bandwidth product through the proportional cooperation of the several groups of current mirrors.

The technical scheme of the invention provides a low-phase-noise four-stage ring oscillator based on a novel negative skew delay unit. The voltage output waveform of the voltage-controlled oscillator of the four-stage negative skew delay unit is more symmetrical, so that the generation of second-order harmonics is reduced. Therefore, the existence of the diode connection type PMOS tube improves the power consumption of the voltage-controlled oscillator, and increases the conversion speed of the output node voltage from high to low, so that the phase noise of the voltage-controlled oscillator of the four-stage negative skew delay unit is reduced by 10dB compared with the phase noise of a voltage-controlled oscillator without an improved structure. According to the invention, the KVCO linearity of the voltage-controlled oscillator of the four-stage negative skew delay unit is improved.

The invention belongs to the technical field of measurement, and particularly relates to a high-resolution high-precision multi-skew integral analog-to-digital converter and an analog-to-digital conversion method.The high-resolution high-precision multi-skew integral analog-to-digital converter comprises a four-path parallel high-precision constant current source circuit, an integrator, an integral output proportional amplification module, a comparator, an integrator zeroing reset circuit and an FPGA; a traditional voltage source / resistor charge injection combination is replaced by four paths of high-precision constant current source circuits, so that the integrator has two zero crossing points while higher-precision quantification of the charge and discharge charge quantity of the integrator is realized, and the influence of a comparator judgment hysteresis phenomenon on the precision is reduced. Through parallel operation of integrator charge and discharge control, data calculation and filtering, data transmission and display and other events in an FPGA, the problem that next analog-to-digital conversion can be started only after a calculation processing result is obtained and the calculation result is filtered and output after a switch control integrator in a traditional double-skew integral analog-to-digital converter charges and discharges is solved. In conclusion, the method has higher resolution, precision and conversion speed.

The invention discloses a method for offsetting sampling noise for a two-stage analog-to-digital converter and the analog-to-digital converter. The two-stage analog-to-digital converter comprises a multi-bit SAR ADC (Synthetic Aperture Radar Analog to Digital Converter) serving as a first stage, an incremental multi-bit order configurable Noise Shaping SAR ADC serving as a second stage and a configurable floating voltage domain amplifier serving as an inter-stage amplifier, wherein the interstage amplifier is arranged between the first stage and the second stage, the input end of the interstage amplifier is connected to the top plate of the CDAC in the first stage, and the output end of the interstage amplifier is connected to the top plate of the CDAC in the second stage. By designing a sampling noise offset method, an interstage amplification linearity enhancement method based on two-step conversion and an interstage amplifier gain digital calibration method based on jitter, the conversion speed and precision of the analog-to-digital converter are improved.