Differential pipelined analog to digital converter with successive approximation register subconverter stages

Abstract

Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs. In one implementation, the capacitors are switched according to a thermometer code to reduce differential converter non-linearity, and the first subconverter stage gain is reduced to improve the conversion system bandwidth.

Description

FIELD OF INVENTION The present invention relates generally to signal processing, and more particularly to a pipeline analog to digital data converter having pipelined fully differential multi-bit successive approximation register subconverter stages. BACKGROUND OF THE INVENTION Wireless communications products and other modern electronic devices typically process and generate both digital and analog signals. To perform their intended functions, these systems often convert analog signals into digital signals, referred to as analog to digital (A / D) conversion. Accordingly, these systems require circuitry to interface signals from the analog domain to signals in the digital domain so that they may perform further digital signal processing. In particular, analog to digital conversion systems (A / D converters, or ADCs) are needed to interface the analog and digital domains. Advances in wireless communications devices, DVD systems, and other related technologies indicate a need for incr...

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