89results about How to "Reduce die area" patented technology

A sigma-delta digital-to-analog converter comprises a current digital-to-analog converter (IDAC) stage which generates a current depending on an input digital signal. An output current-to-voltage converter converts the generated signal to a voltage on a continuous-time basis. The amplifier used in the output current-to-voltage converter is chopper-stabilized. The converter can be single bit or multi-bit. The IDAC stage can be implemented with a pair of branches, a first branch comprising a first biasing current source and a second branch comprising a second biasing current source. The biasing current sources can be chopper-stabilized by connecting the bias current sources to the output current-to-voltage converter by a set of switches. The switches connect the biasing current sources to the output current-to-voltage converter in a first configuration and a second, reversed, configuration. This modulates flicker noise contributed by the bias current sources to the chopping frequency. from where it can be removed by filtering downstream of the current-to-voltage converter.

A feedback-controlled battery charger circuit (500) provides, alternatively, constant current and constant voltage to a battery (328) being charged. Current and voltage at the charger output (326) are sensed in sensing elements (308) and compared to preset reference values from reference generators for current (330) and voltage (332), thus generating error signals for both current and voltage. These error signals are amplified in separate amplifiers (530, 534); then, depending on battery voltage, one of the amplified error signals is automatically selected by a signal selector (540). The selected error signal is applied to a single compensation amplifier (554) with reactive feedback loop (552, 556); the output of the compensation amplifier with feedback (504) then controls the output current or voltage of the output stage (306). This output stage is a voltage controlled current source. The output of this voltage controlled current source is connected through an output filter (318) and sensing elements (308) to the battery (328) being charged.

Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs. In one implementation, the capacitors are switched according to a thermometer code to reduce differential converter non-linearity, and the first subconverter stage gain is reduced to improve the conversion system bandwidth.

Broadly speaking, the invention pertains to substrates for use in semiconductor manufacturing. A peripheral ledge or similar structure can be provided in a die attach pad, so as to retain adhesive that may flow from the die support surface when the die is attached to the die attach pad. In this manner, adhesive is prevented from flowing off the die attach pad, where it can create unwanted conductive areas on the outer surface of an IC package. The accompanying reduction in area of the die support surface, and retention of adhesive from any downbond areas, also prevents delamination of the adhesive.

Methods and apparatus are presented for sensing current flowing in a power transistor of a switch mode converter, in which a voltage is sensed across a first field effect transistor connected in a series circuit branch in parallel with the power transistor, and the sensed voltage is used to generate output signal to indicate the current flowing in the power transistor.

An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit. The power mesh power connection structure is operative to connect the first and second power rails of the first plurality of standard cells to the voltage supply and voltage return, respectively, and is configured so as to reduce a first voltage differential between respective first power rails of the standard cells and to reduce a second voltage differential between respective second power rails of the standard cells.

A multiple-stage digitally-switched impedance has one “type B” stage and at least two “type A” stages. The type A stages are cascaded between high and low reference nodes and the type B stage. Each stage comprises a string of series-connected impedances and a switch network. A decoder responds to an digital input signal by controlling the switch networks to switch selectable portions of the strings in the type A stages into a series connection with the type B stage's string, and to control the type B stage's switch network to tap its string at a location to provide a impedance corresponding to the n-bit digital input signal between the final output node and at least one of the high and low reference nodes. Each stage provides a portion of the impedance's n-bit resolution, and the sum of the bits of resolution provided by each stage equals the total n-bit resolution.

A system and method for computing anisotropic texture mapping parameters by using approximation techniques reduces the complexity of the calculations needed to perform high quality anisotropic texture filtering. Anisotropic texture mapping parameters that are approximated may be computed using dedicated processing units within a graphics processor, thereby improving anisotropic texture mapping performance. Specifically, the major axis and minor axis of anisotropy are determined and their respective lengths are calculated using approximations. Other anisotropic texture mapping parameters, such as a level of detail for selecting a particular level are computed based on the calculated lengths of the major and minor axes.

An on-chip response adjuster is based on an on-purpose generated and dominant transfer pole or zero of a signal response so as to provide a process-stable phase behavior of the circuitry. The signal response is defined directly by a passive frequency variant component (Lfold) and by transistor operation point, e.g. biasing, of a transistor configuration (Qcas,Qaux). As a result, electrically controlled signal response adjusters can be provided with fully integrated, single-chip integrated or system-on-chip (SoC) techniques.

Systems and methods that decompress block compressed texture data may decompress the texture data while simplifying computations to reduce die area while maintaining the required accuracy. Reducing the die area permits more texture data to be decompressed in the same die area compared with a more accurate decompression, thereby increasing texture decompression throughput. Computations are simplified by combining denominators for linear interpolation with format conversion to decompress texture data components compressed using conventional block compression formats.

An on-chip differential inductor includes a 1^st interwound winding having a substantially octagonal shape, or rectangular octagonal shape, and a 2^nd interwound winding having a substantially octagonal shape, or rectangular octagonal shape, that is interwound with the 1^st interwound winding. Both the 1^st and 2^nd interwound windings are on the same layer of the integrated circuit. Each interwound winding includes two nodes; one of node of each winding is commonly coupled to a reference potential. The other node of each winding is operably coupled to receive a respective leg of a differential signal.

This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source-drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.

A novel single chip tuner integrated circuit (IC) for multiple video reception in a cable modem. The tuner circuit is well suited for use in cable modem systems adapted to implement the DOCSIS 3.0 specification which specifies multiple simultaneous video channel reception. The single-chip tuner integrated circuit comprises a plurality of tuner sub-circuits wherein each tuner sub-circuit is operative to generate a single output channel, determined in accordance with a tune commend input. The tune command input is used to generate a frequency reference signal that is input to a corresponding tuner sub-circuit. The frequency reference signal for a tuner sub-circuit is mixed with an input RF receive signal from the CATV input to the cable modem to generate a baseband channel. The baseband channel is subsequently filtered, amplified and input to the PHY circuit wherein undergoes analog to digital conversion (ADC) before being input to a baseband processor.

An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.

Pipelined analog to digital conversion systems are provided having cascaded multi-bit successive approximation register subconverter stages using thermometer coding. Capacitor arrays are provided in the subconverter stages, where switching logic selectively couples the capacitors to operate in sample, conversion, and residue amplification modes for generating multi-bit subconverter digital outputs and analog subconverter residue outputs, wherein the capacitors are switched according to a thermometer code to reduce differential converter non-linearity.

A method and system for interface compression in a raster stage of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive at a first level in a coarse raster component to generate a plurality of tiles related to the graphics primitive. The method determines whether a window ID operation is required for the plurality of tiles. If the operation is required, a respective plurality of uncompressed coverage masks for the tiles are output from the coarse raster component to a fine raster component on a one coverage mask per clock cycle basis. If the operation is not required, a compressed coverage mask for the tiles is output in a single clock cycle. The tiles are subsequently rasterized at a second-level in the fine raster component to generate pixels related to the graphics primitive.

An apparatus having an input transmission line, a plurality of amplifiers and an output transmission line is disclosed. The input transmission line may include a plurality of first inductors configured to receive an input voltage. The amplifiers may be configured to generate a plurality of intermediate currents by amplifying a plurality of intermediate voltages at a plurality of first nodes between the first inductors. The output transmission line generally includes a plurality of second inductors configured to generate an output current at an output node by combining the intermediate currents. Each of a plurality of second nodes connected to the second inductors may transfer a plurality of the intermediate currents. Each of the second inductors generally has a different one of a plurality of inductance values.