3387results about "Analogue-digital converters" patented technology

In an encoder, multiple channels of audio information representing multidimensional sound fields are split into subband signals and the subband signals in one or more subbands are combined to form composite signals. The composite signals, the subband signals not combined into a composite signal and information describing the spectral levels of subband signals combined into composite signals are assembled into an encoded output signal. The spectral level information conveys either the amplitude or power of the combined subband signals or the apparent direction of the sound field represented by the combined subband signals. In digital implementations, adaptive bit allocation may be used to reduce the informational requirements of the encoded signal.

A technique for hiding of data, including watermarks, in human-perceptible images, that is, image host data, is disclosed. In one embodiment a method comprises three steps. In the first step, data to be embedded is inputted. In the case of a watermark, this data is a unique signature, and may be a pseudo-noise (PN) code. In the case of hidden data to be embedded in the host data, this data is the hidden data itself, or the hidden data as spread against the frequency spectrum by a pseudo-noise (PN) code. In the second step, the inputted data is embedded within the host data, in accordance with a perceptual mask of the host data. The perceptual mask determines the optimal locations within the host data to insert the inputted data. In the case of images, these optimal locations are determined by reference to the human visual system. In the third step, the host data, with the embedded data, is further masked by a non-frequency mask. In the case of image data, the non-frequency mask is a spatial mask.

A low power integrated circuit having analog to digital conversion circuitry capable of receiving a plurality of analog signals and converting them to a digital value. The digital value is then transmitted, upon request, over a single wire bus. The accuracy of the analog to digital conversion circuitry can be calibrated via trim codes stored in an onboard EPROM.

The present invention provides an innovative technique for rapidly and accurately determining whether two audio samples match, as well as being immune to various kinds of transformations, such as playback speed variation. The relationship between the two audio samples is characterized by first matching certain fingerprint objects derived from the respective samples. A set (230) of fingerprint objects (231,232), each occurring at a particular location (242), is generated for each audio sample (210). Each location (242) is determined in dependence upon the content of the respective audio sample (210) and each fingerprint object (232) characterizes one or more local features (222) at or near the respective particular location (242). A relative value is next determined for each pair of matched fingerprint objects. A histogram of the relative values is then generated. If a statistically significant peak is found, the two audio samples can be characterized as substantially matching.

A module operable to be mounted onto a surface of a board. The module includes a linear accelerometer to provide a first measurement output corresponding to a measurement of linear acceleration in at least one axis, and a first rotation sensor operable to provide a second measurement output corresponding to a measurement of rotation about at least one axis. The accelerometer and the first rotation sensor are formed on a first substrate. The module further includes an application specific integrated circuit (ASIC) to receive both the first measurement output from the linear accelerometer and the second measurement output from the first rotation sensor. The ASIC includes an analog-to-digital converter and is implemented on a second substrate. The first substrate is vertically bonded to the second substrate.

A touch-sensitive device includes a touch panel, drive unit, and measurement unit. A touch applied to a given node of the panel changes a capacitive coupling between a given drive and sense electrode of the touch panel. The drive unit delivers first and second drive signals, having different first and second frequencies, to first and second drive electrodes respectively at the same or overlapping times. The measurement unit receives a first response signal from a sense electrode, and analyzes the signal using maximum likelihood estimation to determine the coupling capacitance between the first drive electrode and the sense electrode, and between the second drive electrode and the sense electrode. More drive electrodes, including in some cases all the drive electrodes, can be driven with unique drive frequencies, and more sense electrodes, including in some cases all the sense electrodes, can be sensed by the measurement unit.

A sensor panel having a matrix of independently decoded sensors, arranged in a two-dimensional pattern allows a consumer identification unit (CIDU) to detect a user-specific gesture made with a gesturing instrument such as an RF ID device. The CIDU monitors on a timed basis which of the sensors in the panel are receiving a signal from an RF ID device which has entered the proximity of one or more of the sensors. The user moves the sensor in a two-dimensional pattern to perform a “gesture signature” in free space near the panel, and the CIDU records the sequence of receiving sensors. This sequence can then be quickly and efficiently handled as a number to be looked up to identify and authenticate the user. Preferably, the user is allowed to define multiple signature gestures, each having the possibility of being associated with a transaction or authorization level.

A delta-sigma modulator comprising a first quantizer providing a first digital signal d0(k) representing the input signal g(t); a loop filter with input signal paths; a loop quantizer providing a corrective digital signal d1(k) representing the loop filter's output signal y(t); an array of feedback DACs D/A converting the sum d(k)=df(k)=d0(k)+d1(k) of the first and the corrective digital signals and injecting feedback signals into the loop filter.The loop filter's input node is applied the difference of the input signal g(t) and the global analog feedback signal a3(t). The global feedback signal a3(t) is delayed several clock cycles with respect to the digital output signal d(k). The delay is used to carry out mismatch-shaping and deglitching algorithms in the feedback DACs. The feedback DACs' different delays and gain coefficients are designed such that the modulator is stable. The filter's input signal paths and the compensating DAC are designed such that the gain from the input signal g(t) to the loop quantizer is small, ideally zero. Thus, the loop quantizer's resolving range can be a fraction of the first quantizer's resolving range, whereby the output signal's d(k) resolution can be much higher than the individual resolutions of d0(k) and d1(k).The delta-sigma modulator is well suited for the implementation of high-resolution wide-bandwidth A/D converters. Important applications include digital communication systems.

A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.

An analog-to-digital converter system [50D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal, d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, alpha, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero. An analog compensation signal, m0, which is described by a well-controlled relationship to the residue signal, r0, is extracted from the filter [158]. Ideally, the closed-loop signal transfer function from g to m0 will be zero, or at least small in the signal band. A second quantizer [160] converts the analog compensation signal, m0, into a second digital signal, dm0(k). The two digital signals, d0(k) and dm0(k), are filtered individually and then added to form the overall output signal, dg(k). The second digital filter [164] has a low signal-band gain, which implies that the sensitivity to signal-band errors caused by the second quantizer [160] will be low. The output signal, dg(k), is a highly-accurate high-resolution representation of the input signal, g. Circuit imperfections, such as mismatch, gain errors, and nonlinearities, will cause only noise-like errors having a very low spectral power density in the signal band.The invention facilitates the implementation of uncalibrated highly-linear high-resolution wide-bandwidth A/D converters [50D], e.g., for use in digital communication systems, such as xDSL modems and other demanding consumer-market products for which low cost is of the essence.

A digital and analog television signal digitization and processing device that performs the digitization and processing functions using a common reference frequency source that is used to generate multiple subclock signals, wherein the reference frequency source is independent of any synchronizing characteristic of the input signal. For dual channel analog signal processing, the common frequency source is not locked to either channel/input signal. Digital signal processing is accomplished based on the same common reference frequency source. Advantageously, the present invention allows all of the analog-to-digital converters and decoder circuitry/logic necessary for simultaneously digitizing and processing several analog and digital television signals to be integrated on a single integrated circuit as well as eliminating duplicate frequency generation circuits.

A characteristic thumbprint is extracted from a data signal, the thumbprint based on statistics relating to the data signal. The data signal can be compared indirectly by matching this thumbprint against one or more reference thumbprints. The data signal may be any type of signal, including streaming digitized audio or obtained from static files. A database for containing a number of such thumbprints and methods for searching the database are also described.

An apparatus performs adaptive analog-to-digital conversion. The apparatus according to one embodiment comprises a frequency modulator unit for changing an input analog signal into a modulated analog signal with a frequency spectrum in a bandwidth of interest, a parallel delta sigma conversion unit operatively connected to the frequency modulator unit, the parallel delta sigma conversion unit converting the modulated analog signal into a digital signal, and a controller operatively connected to the frequency modulator unit and the parallel delta sigma conversion unit, the controller adjusting at least one parameter relating to a frequency characteristic of the frequency modulator unit and/or the parallel delta sigma conversion unit.

The invention relates to a method for measuring currents in a motor controller. Some current sensing devices placed on the motor wires or inside the motor controller provide low amplitude output signals thus complicating sampling and data processing. In order to improve the signal/noise ratio, an oversampling technique is disclosed which makes used of a differential transmission of the output signal. Further, by applying intelligent sorting techniques on the sampled data, a substantial improvement in the signal/noise ratio can be obtained. The invention also concerns a motor controller using this method, and discloses the use of a power card and a control card, where the current sensing device is placed on the power card and a differential amplifier is placed on the control card. The gain of the differential amplifier is controlled by components placed on the power card as well as on the control card.

An enhancement that reduces the digital interface rate of analog-to-digital (A/D) and digital-to-analog (D/A) converters through the use of compression and decompression is described. The present invention improves A/D converters by compressing the sampled version of the A/D converter's analog input signal in real time, thereby significantly decreasing the required bit rate of the A/D converter's digital interface. Similarly, the present invention improves D/A converters by decreasing the required bit rate of the D/A converter's digital interface. D/A converters enhanced by the present invention include a decompressor that decompresses the D/A converter's compressed digital input in real time, prior to conversion to an analog output signal. The present invention's simplicity and its ability to be implemented using multiple compression and decompression elements allow its use in A/D and D/A converters with arbitrarily high sampling rates. By selecting a desired compression ratio during lossy compression, users of the present invention can precisely control the bit rate of the A/D and D/A converter's digital interface. Users of the present invention can dynamically choose the desired balance between the quality and the bit rate of A/D and D/A converters by adjusting various compression and decompression control parameters.

A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

An MPU changes the phase of a sampling clock signal by one step for each frame until the change in the phase reaches 360 degrees. An image quality detector portion sequentially receives a digital image signal to detect a maximum one of data about the absolute value of a difference between adjacent pixels in one frame as an image quality judgement data signal. The MPU detects a maximum one of all image quality judgement data to determine a phase at that time as an optimum phase of the sampling clock signal. The MPU then periodically checks image quality on a screen, and makes a real-time correction to the phase of the sampling clock signal if a temperature drift or the like occurs.

D/A converter of this invention including n+1 capacitors in total consisting of one terminating capacitor (C0) and n binary-weighted capacitors (C1-4) that are subjected to binary weighting ratio of 1:2:4: . . . :2⁽ⁿ⁻¹⁾, and, an inverting amplifier (INV1), further comprising: a feedback switching means (SWR5) provided between the input and output of the inverting amplifier (INV1); a switching means for terminating operation (SWR0) supplies one of two main reference voltages (VB,VT) to the terminating capacitor (C0), and then, makes connection of the terminating capacitor (C0) to the output of the inverting amplifier (INV1); a plurality of switching means for input operation (SWD1-4,SWR1-4) makes selection of one of the two main reference voltages (VB,VT) to be provided for the n binary-weighted capacitors (C1-4) depending on digital data (D1-4), and then, makes connection of the second terminal side of the n binary-weighted capacitors (C1-4) to the output of the inverting amplifier (INV1).

A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representation of the modulated analog serial data). The DSP communicatively couples to the ADC and receives the digitized serial data. Based upon the known characteristics of the digitized serial data and the digitized serial data itself, the DSP determines compensation operations to be performed upon the serial data to compensate for inadequacies of the receiver and/or channel response. These compensation operations may be (1) performed on the analog serial data before digitization by the ADC; (2) applied to the ADC to modify the operation of the ADC; and/or (3) performed on the digitized serial data by the DSP or another device.

A radio frequency front end for a television band receiver and spectrum sensor includes a low noise amplifier that amplifies a received signal output of a radio frequency antenna connected to the radio frequency front end, a pin diode attenuator circuit that selectively attenuates an output of the low noise amplifier, and a buffer amplifier that amplifies an output of the pin diode attenuator.

A time-interleaved analog-to-digital conversion apparatus is disclosed. The time-interleaved analog-to-digital conversion apparatus is applied for a television system and includes an input multiplexing module, a gain multiplexer and an analog-to-digital converter. The input multiplexing module receives a plurality of image signals, and samples the image signals according to a clock signal to generate a sample multiplexing signal. The gain multiplexer receives a plurality of gain signals and selectively transmits one of the gain signals corresponding to the sample multiplexing signal according to the clock signal, so as to generate a gain multiplexing signal. The analog-to-digital converter receives the sample multiplexing signal, the gain multiplexing signal and the clock signal. The analog-to-digital converter amplifies and converts the sample multiplexing signal to a digital signal according to the gain multiplexing signal and the clock signal.

A solid state imager includes an arrangement for converting analog pixel values to digital form on an arrayed per-column basis. An N-bit counter supplies an N-bit DAC to produce an analog ramp output providing a ramp signal with a level that varies corresponding to the contents of the counter. Latches or equivalent digital storage elements are each associated with a respective column. A counter bus connects the counter to latch inputs of said latches, and comparators associated the columns gate the latches when the analog ramp equals the pixel value for that column. The contents of the latch elements are transferred sequentially to a video output bus to produce the digital video signal. There can be additionally black-level readout latch elements, for storing a digital value that corresponds to the dark or black video level, and a subtraction element subtracts the black level value from the pixel value to reduce fixed pattern noise. An additional array of buffer latches can be employed.

A power converter including a hardware efficient control loop architecture. Error detection circuitry may generate an error signal based on the difference between a power converter output voltage and a reference voltage. An oversampling ADC may digitize the error signal. The transfer function associated with the ADC may include quantization levels spaced at non-uniform intervals away from a center code. A digital filter may calculate the average of the digitized error signal. A nonlinear requantizer may reduce the number of codes corresponding to the output of the digital filter. A proportional integral derivative (PID) unit may multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command, and a gain compensation unit may dynamically adjust the PID coefficients to maintain a constant control loop gain. A noise-shaped truncation unit including a multi-level error-feedback delta sigma modulator may reduce the resolution of the PID duty cycle command.

In an image pickup device with A/D converters at each column signal line, improvements in the A/D conversion speed and accuracy in image sensors having A/D converters are achieved. In an image pickup device wherein sensing elements are arranged in a matrix and A/D converters are arranged for each column signal line, the A/D converter first retains in its memory unit as an initial value an electric signal corresponding to the signal of the sensing element which is an analog signal, then initiates charge or discharge of the memory unit at a rate corresponding to the size of an input fixed signal, measures the time period from either the charge start time or the discharge start time until the memory unit electric signal becomes equal to the reference signal, and then recognizes the measured time period as a digital value.

The present invention provides an adaptive, intelligent transform based Analog to Information Converter (AIC) for wideband signals by directly converting an analog signal to information (e.g., features, decisions). This direct conversion is achieved by (i) capturing most of the information of a wideband signal via hardware/software implemented mathematical transformations, (ii) effectively removing unwanted signals such as jammer and interfere from the input signal, and (iii) using novel algorithms for highly accurate decision making and feature extraction (e.g., high probability of detection with low probability of false alarm). The jump in the improvement over today's state-of-the-art is in terms of effective and optimum signal information extraction at high-speed.

A scalable audio coding/decoding method and apparatus are provided. The coding method includes the steps of (a) signal-processing input audio signals and quantizing the same for each predetermined coding band; (b) coding the quantized data corresponding to the base layer within a predetermined layer size; (c) coding the quantized data corresponding to the next enhancement layer of the coded base layer and the remaining quantized data uncoded and belonging to the enhancement layer, within a predetermined layer size; and (d) sequentially performing the layer coding steps for all layers, wherein the steps (b), (c) and (d) each comprise the steps of: (i) obtaining gamut bit allocation information representing the number of bits of the quantized data corresponding to the respective subbands belonging to a layer to be coded; (ii) obtaining the number of bits allocated to the respective subbands within each subband size of the layers; (iii) generating an index representing the presence of quantized data for predetermined frequency components forming the subbands for the quantized data corresponding to the number of allocated bits; and (iv) generating bitstreams by coding the quantized data corresponding to the gamut bit allocation information, quantization step size, index and number of bits allocated to the respective subbands, by a predetermined coding method.

A transformer-isolated analog-to-digital converter (ADC) feedback apparatus and method provides reduction of circuit complexity in high power/high voltage systems having a transformer-isolated sensing circuit. The feedback apparatus is a circuit including an ADC for receiving an analog input signal and a transformer having a first winding that receives a modulated output of the analog-to-digital converter. A second winding of the transformer provides an isolated data output of the ADC. A demodulator is coupled to the second winding of the transformer and demodulates the isolated output to generate a digital representation of the analog input signal. The ADC may be a delta-sigma converter and the demodulator may be the corresponding decimation filter. The circuit further includes an isolation circuit for introducing a clock signal and/or power supply waveform at the second winding of the transformer, so that the ADC circuit is supplied with an isolated clock and/or an isolated power supply.

An electronic apparatus includes a CMOS image sensor and a signal processor operable to process an output signal from the CMOS image sensor. The CMOS image sensor includes the following elements: an imaging region; a reference signal generator operable to generate a reference signal; a comparator operable to compare the reference signal generated by the reference signal generator with a signal transmitted from the imaging region; a counter operable to count, in parallel with comparison performed by the comparator, a predetermined count clock and to hold a count value at the time of completion of comparison performed by the comparator; and a reference signal supply interface unit operable to supply the reference signal generated by the reference signal generator to a plurality of comparators via different signal lines, respectively.