3269results about "Analogue-digital converters" patented technology

The invention discloses a sampling implementation method and system suitable for motor protection quick response, belongs to the technical field of motor protection, and can increase the sampling frequency and improve the quick response of motor fault protection. Comprising the steps that motor phase current and bus voltage are collected, after anti-aliasing filtering is conducted, parallel sampling is conducted through a main ADC module and a redundant ADC module which are independently configured, and the following operations are synchronously executed based on a double-buffer-area framework: in a first buffer area, a compensation coefficient updating period is dynamically adjusted, and convergence is restrained; in the second buffer area, generating a voltage gradient prediction sequence, and compensating data abrupt change; when the harmonic frequency spectrum amplitude or the voltage gradient prediction sequence exceeds the limit, an oversampling mode is triggered, a redundant ADC module is allocated to load a multi-order digital filter, and an independent hardware acceleration unit is started to process harmonic compensation and gradient prediction in parallel; and generating a dynamic safety envelope, and if the gradient extreme value in the preset continuous window breaks through the safety envelope, generating an overvoltage fault signal.

The invention discloses a multichannel high-precision PAF signal synchronous acquisition system and a multichannel high-precision PAF signal synchronous acquisition method, and relates to the technical field of phased array signal acquisition and processing, the multichannel high-precision PAF signal synchronous acquisition system is characterized in that a hydrogen atomic clock time-frequency distribution module is in signal connection with a plurality of signal acquisition processing boards, and each signal acquisition processing board comprises a double-loop phase determination clock circuit and an RFSoC circuit; and the double-loop phase determination clock circuit is in signal connection with the RFSoC circuit. The time-frequency distribution module adopts a time-frequency signal output by a hydrogen atomic clock as a reference, so that the synchronization precision is ensured; the clock architecture of the acquisition processing board card adopts a phase determination mode, so that a Tile clock and a PL logic clock in the board are strictly in phase with an external input reference clock, and ADC acquisition synchronization of all channels is ensured; a phase clock circuit design is determined by adopting double loops, and all output clocks and an input reference clock keep a strict phase relationship; the system adopts a three-step synchronization process, so that the synchronous acquisition of hundreds of paths of PAF signals reaches the ps-level precision.

The invention belongs to the technical field of signal acquisition and processing, and discloses a low-noise biopotential signal acquisition system and a low-noise biopotential signal processing method. An original bioelectricity signal of a human body is collected through an electrode array, and analog-to-digital conversion is carried out after the signal is processed by a multi-stage self-adaptive filtering and amplifying circuit. A digital signal is sequentially subjected to adaptive wavelet transform denoising and empirical mode decomposition to obtain a multi-level intrinsic mode function set, an intrinsic mode function of a characteristic frequency band is extracted from the multi-level intrinsic mode function set, and the signal is reconstructed. Introducing a dual noise reduction mechanism combining adaptive wavelet transform and empirical mode decomposition; a signal quality real-time evaluation system is established, and system parameters including the gain of a variable gain amplifier and the bandwidth of a dynamic band-pass filter are dynamically adjusted through closed-loop feedback. The self-adaptive optimization of the whole biopotential signal acquisition process is realized, various interferences are effectively inhibited, the signal characteristics are reserved, and the signal-to-noise ratio is remarkably improved.

A system for data collection related to a fluid conveyance environment includes a data acquisition circuit comprising inputs and outputs; input sensors to provide sensor data values, coupled to a component in the fluid conveyance environment; and a processor comprising the data acquisition circuit. The processor is configured to determine a data storage profile; responsive to the data storage profile, configure the data acquisition circuit to selectively couple at least one of the inputs to at least one of the outputs; interpret the at least one of the sensor data values; store at least a portion of the at least one of the sensor data values in response to the data storage profile; analyze a set of the sensor data values and determine a data quality parameter; and adjust at least one of the data storage profile and a data collection routine in response to the data quality parameter.

The invention relates to a high-precision temperature sensor based on complementary dynamic element matching and a zoom analog-to-digital converter and a working method, and belongs to the technical field of sensor improvement, and the sensor comprises an analog front end, an analog-to-digital converter, a digital rear end and a control logic. An improved chopping technology is adopted, and one clock signal is adopted to control two sub operational amplifiers, so that the output stability and precision of the analog front end are improved. A complementary dynamic element matching technology is utilized, errors caused by voltage drop at the two ends of a switch are reduced, the influence of channel charge injection is counteracted, a scaling type analog-to-digital converter design is provided for an analog-to-digital conversion part, and balance among power consumption, speed and precision is achieved. According to the method, a 10-bit successive approximation register analog-to-digital converter is used for measuring a numerical value and a change trend, and the numerical value and the change trend are analyzed, so that the expression effects of a current mirror structure, a transistor, a filter and the like are evaluated, the aging of the transistor is found in advance, and a clear direction is provided for future design improvement.

The invention relates to a multi-channel acquisition module, system and method based on trigger synchronization automatic calibration, and belongs to the field of electronic measurement, the acquisition module comprises a channel conditioning and acquisition circuit, a trigger and input and output feedback circuit, a clock synchronization and calibration signal generation circuit and an FPGA receiving and synchronous calibration circuit; the method has the advantages that the multi-channel synchronization precision is high, convenient channel expansion is supported, pairwise interconnection delay calibration can be carried out between modules in parallel, the system calibration time does not increase linearly along with the increase of the number of the channels, the interconnection relation is realized through annular connection, and a large fan-out cable is not needed.

The invention provides a common-mode feedback circuit and a differential amplifier thereof, the common-mode feedback circuit comprises a sampling circuit and an amplifier circuit, the sampling circuit comprises a first input end, a second input end and a first output end, the first input end receives a first differential signal Voutp, and the second input end receives a second differential signal Voutn; the level shift module comprises a third input end, a fourth input end and a second output end, receives a common-mode signal VCMS and a reference common-mode signal VOCM output by the sampling circuit, and adjusts the common mode of the common-mode signal VCMS and the reference common-mode signal VOCM to enable the second output end to output a common-mode feedback signal VCMFB processed by the level shift module; the amplifier circuit receives a common mode feedback signal VCMFB. After the technical scheme is adopted, the same speed as that of a differential loop can be realized, the current of a main operational amplifier can be multiplexed, the power consumption of a common-mode loop is far lower than that of a main loop, and meanwhile, the common-mode level can be randomly adjusted.

The invention discloses a multi-channel AFE signal acquisition method and system based on adaptive adjustment, and the method comprises the steps: synchronously acquiring multi-channel analog signals through a multi-channel parallel AFE module, and configuring an independent programmable gain amplifier and an anti-aliasing filter for each channel; extracting time-frequency domain characteristic parameters of each channel signal in real time; dynamically generating an optimal adjustment strategy based on the time-frequency domain characteristic parameters, and adaptively adjusting the gain coefficient, the filtering bandwidth and the sampling rate parameter of each channel through a closed-loop feedback mechanism; and abnormal signal detection is realized by adopting an inter-channel cross validation algorithm, and automatic isolation of a fault channel and intelligent switching of a redundant channel are triggered. Through dynamic parameter intelligent adjustment, multi-channel cooperative fault tolerance and energy efficiency optimization architecture, the problems of signal distortion, response lag and high power consumption in a traditional multi-channel signal acquisition system are solved, and the signal fidelity and the system reliability are remarkably improved.

The invention discloses a signal sampling method for a multi-channel signal converter, and the method comprises the steps: carrying out the synchronous and parallel sampling of an analog signal source according to a multi-channel signal collection module, so as to obtain multi-channel original signal sequence data; performing inter-channel time delay calibration and amplitude normalization processing on the multichannel original signal sequence data to obtain a calibrated multichannel signal data set; the invention relates to the technical field of signal processing. According to the signal sampling method for the multi-channel signal converter, the multi-channel signal converter improves the data consistency and accuracy through the technologies of synchronous sampling, time delay calibration, amplitude normalization and the like, meanwhile, precision adjustment of self-adaptive filtering, dynamic threshold segmentation and entropy driving is adopted, signal interference and abnormal data are reduced, and the signal quality is improved. The non-uniform resampling and compression technology is adopted to optimize the storage and transmission efficiency, key data is ensured to be transmitted preferentially, hardware is accelerated through an FPGA, and the real-time performance and the processing capacity of the system are improved.

Methods and systems for a monitoring system for data collection in an industrial environment including a data collector communicatively coupled to a plurality of input channels connected to data collection points operationally coupled to at least one industrial component in at least one of an industrial boiler system or industrial pipeline system; a data storage structured to store a library of stored noise patterns associated with operation of the at least one industrial component; a data acquisition circuit structured to interpret a plurality of detection values from the collected data; and a data analysis circuit structured to: analyze the collected data, determine a measured noise pattern for the at least one industrial component, and compare the measured noise pattern to the library of stored noise patterns to identify a changed condition of the at least one industrial component.

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

The invention discloses a current and voltage signal synchronous correction and output method and system, and relates to the technical field of power system analysis and control. Compared with a previous current and voltage signal correction method, the method solves the problems that traditional multi-channel signal acquisition depends on conventional clock control, and synchronization precision is insufficient; a conventional sampling circuit is weak in anti-interference capability. The problem that an existing scheme lacks efficient error prediction and dynamic optimization capability is solved. Through a multi-channel FPGA clock synchronization and double-differential sampling technology, complete acquisition of high-frequency transient characteristics of voltage and current signals is ensured; a dynamic calibration algorithm and multi-stage composite filtering are combined, so that common-mode interference and non-linear errors are effectively suppressed; and finally, through optical fiber isolation output and intelligent feedback control, signal full-link synchronous correction is realized, the electric energy metering error can be reduced, the fault positioning precision is improved, the characteristics of high precision, strong anti-interference and low energy consumption are realized, and a reliable data reference is provided for intelligent power grid and new energy grid connection.

Systems for self-organizing data collection and storage in a power generation environment are disclosed. A system may include a data collector for handling a plurality of sensor inputs from sensors in the power generation system, wherein the plurality of sensor inputs is configured to sense at least one of: an operational mode, a fault mode, a maintenance mode, or a health status of at least one target system. The system may also include a self-organizing system for self-organizing a storage operation of the data, a data collection operation of the sensors, or a selection operation of the plurality of sensor inputs. The self-organizing system may organize a swarm of mobile data collectors to collect data from a plurality of target systems.

The invention discloses a multipath signal conversion crosstalk-free optimization system and method, and relates to the technical field of data acquisition and signal processing, and the system comprises a detection module which is used for generating an initial calibration parameter based on a synchronization signal phase deviation detection result, and an adjustment module which is used for adjusting the frequency and phase of a sampling clock according to the initial calibration parameter, the calibration module is used for carrying out alignment calibration on multiple paths of data to obtain an alignment error value, and the optimization module is used for further optimizing a sampling clock based on the alignment error value to realize accurate calibration; compared with a traditional hardware phase-locked loop system, the multipath signal conversion crosstalk-free optimization system and method have higher adjustment flexibility and synchronization precision, are suitable for a high-frequency and high-precision data acquisition application environment, and improve overall sampling accuracy and data analysis reliability while maintaining system stability.

A configurable power monitoring system for electronic devices is described herein. In an example, a device can include a first circuit that can receive a first voltage signal from a voltage bus and output a second voltage signal that is lower than the first voltage signal. An electronic system can be coupled to the voltage bus. A second circuit can be coupled to the electronic system and can output a third voltage signal corresponding to current flow through the electronic system. An amplifier can amplify the third voltage signal to generate an amplified voltage signal. An accumulator can determine a power consumption value of the electronic system based on the second voltage signal and the amplified voltage signal. A data communication system can transmit the power consumption value to the electronic system and can receive configuration data usable to adjust an accuracy and / or a dynamic sensing range of the device.

The invention discloses a PUF (Physical Unclonable Function) structure based on delay difference quantization, and the structure comprises a PUF circuit which comprises two time delay circuits which are connected in parallel; a plurality of layers of differential tapped circuits TDC, and decoders connected with each layer of differential tapped circuit TDC; the delay data quantization unit is connected with the multi-layer decoder, and the delay data quantization unit is connected with the LFSR confusion structure; the two delay circuits are connected with the multi-layer differential tap circuit TDC through the signal selection structure, the signal selection structure inputs delay signals which respond first and then respond in the two delay circuits into a start end and a stop end of each layer of differential tap circuit TDC, the decoder determines delay time of the two delay circuits under corresponding delay resolution, and the decoder outputs the delay time to the multi-layer differential tap circuit TDC. The delay data quantization unit is used for averaging the delay time under different time delay resolutions to serve as final delay data, and the final response R is output after the final delay data is confused by the LFSR confusion structure. Signals of the two symmetrical delay paths are respectively input into a framework of a multi-layer TDC quantization circuit, so that delay difference digital code quantization is realized.

A system includes an expert graphical user interface configured to: present a list of reliability measures of an industrial machine, facilitate a selection by a user of a reliability measure from the list of reliability measures, present a representation of a smart band data collection template associated with the reliability measure selected by the user, and a data routing and collection system configured to, in response to a user indication of acceptance of the smart band data collection template, collect data from a plurality of sensors in an industrial environment in response to a data value from one of the plurality of sensors being detected outside of an acceptable range of data values.

The invention discloses a multi-channel parallel sampling high-dynamic response analog-to-digital conversion method, system and equipment and a storage medium, and belongs to the technical field of power electronics and signal processing, and the method comprises the steps: configuring a high-speed analog-to-digital converter channel to form a parallel sampling module, carrying out the alternate sampling of an input power grid analog signal, and generating a discrete sampling sequence group; inputting to a control unit to extract feature data, and calculating to obtain a fluctuation feature value; constructing a channel clock control vector, sending the channel clock control vector to each high-speed analog-to-digital converter channel, adjusting a sampling trigger moment, and re-executing analog signal sampling to obtain a sampling sequence after phase compensation processing; performing waveform reconstruction processing to obtain continuous reconstruction waveform data; and performing electric energy integral operation, and outputting a dynamic metering result. According to the invention, the problems of slow response, sampling distortion and large metering error of the analog-to-digital conversion system under the conditions of frequency fluctuation, unsteady disturbance and bidirectional power in the prior art are solved.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

The invention provides a full-parallel arbitrary multiplying power variable sampling system, and belongs to the technical field of signal processing. The system comprises an up-sampling system and a down-sampling system, the up-sampling system is used for a transmitter and comprises an up-sampling filter and an up-sampling interpolator, and the down-sampling system is used for a receiver and comprises a down-sampling filter, an extractor and a down-sampling interpolator; the up-sampling system can process four paths of input signals in parallel, and four paths of output signals are obtained after the four paths of input signals are processed in parallel; the down-sampling system is formed by cascading a plurality of down-sampling filters and an extractor, an extraction module is responsible for down-sampling of integer 2n times, and a decimal interpolator is connected behind the extractor to realize down-sampling processing of any decimal times. According to the invention, the limitation of traditional integer or simple fractional multiple sampling is broken through, arbitrary-multiplying-power precise resampling of the GHz-level signal is realized, the processing speed and the interpolation precision are obviously improved, the error is low, the anti-aliasing capability is strong, and the method is suitable for the high-requirement fields such as private network communication.

The invention discloses an ion source automatic beam adjusting method, a radiotherapy system and related equipment, and relates to the technical field of radiotherapy, and the method comprises the steps: monitoring and adjusting a plurality of control parameters in real time, and obtaining an optimal control parameter combination; under the optimal control parameter combination, the variable quantity of each control parameter before and after adjustment and the performance change of the proton beam are obtained; performing a pulse width charge test according to the variation of each parameter before and after adjustment and the performance change of the proton beam; obtaining an optimal adjustment parameter and an adjustment amount through a pulse width charge test result; and through the optimal adjustment parameter and adjustment amount, automatic beam adjustment is realized, stable and efficient acceleration of the proton beam in the synchrocyclotron system is realized, and the stability and consistency of the proton beam are ensured.

The invention discloses a multi-closed-loop parameter autonomous smooth switching control method based on load characteristic identification. A variable load, a load characteristic sampling unit, a bias superposition unit, a closed-loop reference given unit, a closed-loop switching unit, a closed-loop control unit and a power output unit are included. The load characteristic sampling unit transmits the acquired variable load circuit and other signals to the closed-loop switching unit after bias superposition of the bias superposition unit; the closed-loop switching unit performs phase operation on the bias superposed signal to obtain a corresponding power supply closed-loop control mode, and transmits the identified power supply closed-loop control mode to the closed-loop control unit; and the closed-loop control unit is used for switching a power supply closed-loop control mode by combining a closed-loop reference value output by the closed-loop reference giving unit so as to control the power output unit to output corresponding power to the variable load. According to the invention, through the self-generated conduction characteristics of the diodes, the hysteresis function can be realized without adding extra algorithms and circuits, and autonomous smooth switching can be realized.

The invention relates to a method for realizing multi-channel ADC (Analog to Digital Converter) data synchronization processing based on an FPGA (Field Programmable Gate Array), which comprises the following steps that: the FPGA receives a clock frequency generated by an external clock generator and takes the clock frequency as a working clock of the FPGA; a plurality of groups of same-frequency clocks and same-phase clocks are generated in the FPGA and are respectively used as working clocks of the ADC chips; the FPGA receives sampling data of each ADC, an enable signal is set, and when the enable signal is effective, digital down-conversion, decimation filtering and FIR filtering are carried out on each sampling data; and after FIR filtering is completed, another enable signal ENend is generated, and data are further stored or transmitted to an upper computer. According to the method and the device for realizing the multi-channel ADC data synchronous processing based on the FPGA, the processor and the computer readable storage medium thereof, synchronous start and stop of the processing flow are controlled through the enable signals ENstart and ENend, synchronous processing of the multi-channel ADC data is ensured, accuracy and effectiveness are improved, and the method and the device have a wide application range.

The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

The invention belongs to the technical field of integrated circuits, and particularly relates to a time mismatch extraction method based on parallel windowing autocorrelation. According to the method, firstly, clustering processing is carried out on signal points; thirdly, preliminarily screening out legal signals based on the time occupancy rate of the signals, and constructing an initial legal signal library; a similarity score between the signals is further calculated through an IDK algorithm, and adjacent frequency bands are divided through a Pettitt method; and finally, continuation of legal signals is realized by means of a DBSCAN clustering algorithm, and automatic construction of a legal signal library is completed. The method is not only suitable for scenes without prior information, but also can be applied under the condition with partial prior information, and can be dynamically updated according to actual requirements. The method is based on radio frequency spectrum monitoring big data, can construct a legal signal library with high reliability and strong generalization ability, provides effective support for subsequent illegal signal monitoring, and has important application value.

The invention discloses a peak code modulation circuit based on a dynamic memristor, which comprises the dynamic memristor and a signal conversion module, and is characterized in that the signal conversion module comprises a signal isolation module, a feature extraction module and a pulse conversion module which are connected in sequence. The dynamic memristor generates a voltage signal with a slow-rising and steep-falling characteristic under constant current input. The signal isolation module comprises a high-impedance input buffer circuit; the feature extraction module comprises an asymmetric time constant signal processing circuit used for performing enhanced extraction on the steep drop feature of the memristor output signal; and the pulse conversion module comprises a dual-threshold positive feedback hysteresis comparison circuit and is used for converting the output signal of the feature extraction module into a rectangular digital pulse. The circuit is specially designed according to the characteristics of the memristor, is simple in structure, is easy to integrate, can achieve the efficient conversion from an analog signal to a standard digital pulse, and is suitable for the fields of neuromorphic calculation and low-power-consumption signal processing.

The invention discloses an external ADC synchronous sampling method and device based on microprocessor timer cascade, and relates to the field of microprocessor external ADC high-speed synchronous sampling. The method comprises the following steps: periodically generating an external ADC sampling trigger signal by configuring a first timer; triggering a second timer update event by using an external ADC data ready signal, automatically sending data to ADC peripherals through an SPI interface DMA sending channel, and automatically carrying ADC sampling data to a memory buffer area through an SPI interface DMA receiving channel; continuous and single conversion modes are supported, and the data integrity is ensured by adopting a double-buffering mechanism. And full-link hardware synchronization from sampling triggering to data storage is realized. By implementing the technical scheme provided by the invention, the technical bottleneck of realizing high-speed synchronous sampling on middle and low-end microprocessor platforms without a DMAMUX function is overcome. The MCU interruption frequency and resource occupation are obviously reduced, time sequence jitter caused by software delay is eliminated, and the sampling synchronization precision and the system real-time performance are greatly improved.

The invention discloses a full-localization ultra-high-speed multi-channel ADC (Analog to Digital Converter) acquisition and processing platform, and relates to the technical field of signal processing. The platform comprises a high-stability clock distribution calibration module, a synchronous acquisition and pulse injection module, a pulse detection and integer deviation module, a coarse-grained translation alignment module, a sub-sampling phase extraction module, a fractional delay interpolation alignment module, a hierarchical storage and flow control module and a high-speed interface synchronous output module. Multi-channel sampling clock synchronization is realized through FPGA dynamic phase adjustment; performing coarse-grained translation by injecting calibration pulses to detect integer deviation, extracting a sub-sampling phase difference, and adopting fractional delay filtering to realize sub-sampling precision alignment; hierarchical storage and intelligent flow control are carried out according to priorities, and synchronous data flow is output through a domestic high-speed interface; through a full-flow domestic chip and a synchronous correction technology, sub-sampling precision alignment and hierarchical flow control output of a multi-channel ADC at an ultrahigh sampling rate are realized.

An example analog-to-digital converter (ADC) includes first ADC circuitry, second ADC circuitry, and dither circuitry. The dither circuitry of the example ADC is to generate a first dither signal to produce a first dithered input signal at a first output coupled to an input of the first ADC circuitry, generate a second dither signal to produce a second dithered input signal at a second output coupled to an input of the second ADC circuitry, the first dither signal and the second dither signal to have opposite signs, and produce an output signal at a third output based on the first output of the first ADC circuitry and the second output of the second ADC circuitry.

The invention discloses a digital-to-analog converter chip which comprises an analog power supply for supplying power to an analog power supply domain, a digital power supply for supplying power to a digital power supply domain and a clock power supply for supplying power to a clock power supply domain, the digital power supply domain comprises a first linear voltage regulator, and the clock power supply domain comprises a second linear voltage regulator. Power supply output ends of the analog power supply, the digital power supply and the clock power supply are respectively connected with a power supply detection circuit; the power supply detection circuit is used for outputting a power supply establishment signal; the digital power domain comprises a second AND gate unit, and the clock power domain comprises a third AND gate unit; wherein the second AND gate unit is used for enabling the first linear voltage regulator to start; and the third AND gate unit is used for enabling the second linear voltage regulator to start. The problem that in the prior art, the LDO of the digital power domain and the LDO of the clock power domain are likely to be different in voltage building time in the power-on starting process, and consequently overvoltage of a low-voltage device is caused is solved, and the reliability of a digital-to-analog converter chip is improved.