287results about "Analogue-digital converters" patented technology

This invention provides a semiconductor device that automatically corrects the conversion value of an analog-to-digital converter, a method for correcting the conversion value of an analog-to-digital converter, and a program for doing so. [Solution] The analog / digital converter 1 outputs a converted value DS obtained by converting the input signal IN from analog to digital. The non-volatile memory 11 stores multiple correction values. The correction circuit 21 selects a correction value from the multiple correction values ​​according to the situation, depending on the situation affecting the offset on the converted value DS of the analog / digital converter 1, and outputs an output value OUT with the offset on the converted value DS corrected based on the selected correction value.

Embodiments of the present application relate to analog-to-digital converter decision control. An analog-to-digital converter (ADC) (100) includes a capacitive digital-to-analog converter (CDAC) (102), a comparator (106), and a successive approximation register (SAR) control circuit (108). The comparator (106) is coupled to an output of the CDAC (102). The SAR control circuit (108) is coupled to an output of the comparator (106) and an input of the CDAC. The SAR control circuit (108) includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal is coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC (102).

This invention discloses a microcontroller-based analog-to-digital (AD) acquisition method, circuit, and vehicle. The microcontroller includes a reference signal input terminal, a calibration signal input terminal, and an AD acquisition terminal. The reference signal input terminal is electrically connected to an external reference voltage source, the calibration signal input terminal is electrically connected to a calibration source, and the AD acquisition terminal is electrically connected to an analog signal acquisition circuit. The AD acquisition method includes: acquiring a calibration voltage signal through the calibration signal input terminal and acquiring an external reference voltage signal through the reference signal input terminal; determining whether to acquire an analog voltage signal through the AD acquisition terminal based on the calibration voltage signal and the internal reference voltage signal; if so, acquiring the analog voltage signal through the AD acquisition terminal; during the acquisition of the analog voltage signal through the AD acquisition terminal, determining the signal quantity of the analog voltage signal based on the external reference voltage signal, enabling relatively accurate detection of the acquired analog voltage signal value. The process is simple, efficient, low-cost, and suitable for widespread use.

An imaging circuit arrangement is provided, comprising a column of image pixels coupled to a pixel output line, a first data converter circuit with an input coupled to the pixel output line and configured to output a first bit set, an integrator with an input coupled to the first data converter, and a second data converter circuit with an input coupled to the integrator and configured to output a second bit set. The first data converter circuit can be an analog-to-digital converter with a successive approximation register. The integrator can include an amplifier for charging an integrating capacitor. The second bit set can be scaled based on a calibrated value before being combined with the first bit set.

The application discloses an analog-digital conversion circuit and chip, a motor driving device, an electrical equipment, and a vehicle and equipment, wherein the analog-digital conversion circuit comprises an analog signal sampling module, a clock signal generating module and a flip-flop, the analog signal sampling module is used for acquiring an analog signal and generating an analog sampling signal; the clock signal generating module is used for generating a clock signal; a first input end of the flip-flop is connected with an output end of the analog signal sampling module, a second input end of the flip-flop is connected with an output end of the clock signal generating module, and an output end of the flip-flop is connected with a switch control end of the analog signal sampling module; the flip-flop is used for controlling a duty cycle of an output signal according to the clock signal and the analog sampling signal to generate a digital pulse signal. The analog-digital conversion circuit of the embodiment has a wider collection range for the analog signal, and the circuit has a wide application range. The motor driving device, the electrical equipment, the vehicle and the equipment have more stable performances.

This invention proposes a non-uniform phase-shifted optical quantization analog-to-digital converter (ADC) with anti-pulse amplitude jitter, comprising an electro-optic modulator, a non-uniform phase shifter, a complementary light generation module, an optical power control module, and a balance threshold decision module. The electro-optic modulator performs electro-optic conversion on the input analog electrical signal and completes optical sampling. The non-uniform phase shifter performs phase shifting on the optical signal input to the electro-optic modulator. The complementary light generation module splits the optical signal input to the non-uniform phase shifter into two complementary optical signals. The optical power control module controls the power ratio between the two complementary lights input to the complementary light generation module. The balance threshold decision module performs differential detection on the complementary light output from the optical power control module and performs threshold decision output quantization encoding. This invention solves the problem of sampling pulse amplitude jitter affecting quantization performance and can better meet the application requirements of high-speed, high-performance analog-to-digital conversion.

A hearing aid comprising an input unit configured to provide first and second digitized signals associated with first and second sampling rates, respectively, the first and second digitized signals comprising a plurality of first frames and a plurality of second frames; a first analysis filter bank configured to generate first frequency domain signals associated with a first frequency range and a second frequency range based on the first digitized signals; a second analysis filter bank configured to generate second frequency domain signals associated with the first frequency range based on the second digitized signals; wherein the first frequency range of the first frequency domain signals and the second frequency domain signals comprise the same frequency band; and a signal processing unit configured to generate a first processed signal based on the first frequency range of the first frequency domain signals and the second frequency domain signals; an output unit configured to output an audible signal based on the first processed signal.

This invention belongs to the field of analog integrated circuit technology, specifically relating to a frequency adaptive circuit for downhole detection. This invention utilizes a closed-loop adaptive feedback mechanism, employing multiple excitation frequencies generated by a frequency generator to continuously match and adapt to the transducer's resonant frequency. When a set of excitation frequencies achieves the highest matching degree with the resonant frequency, the echo energy reaches its peak. The frequency generator is adaptively adjusted based on the excitation frequency corresponding to the maximum peak signal obtained during the detection phase, and this optimal excitation frequency is used to generate the excitation signal in subsequent operations, thus completing the adaptation between the excitation frequency and the resonant frequency. This invention effectively avoids the influence of downhole temperature and pressure changes on the transducer's resonant frequency, and combines high automation, good real-time performance, and high imaging quality.

The utility model relates to chip calibration technical field, especially, a kind of beamformer and ultrasonic chip, including the calibration circuit being coupled with sampling circuit, the relationship between the sampling capacitor C s And parasitic capacitance C p Between by the calibration circuit is indeed, to realize the calibration of the relationship between the input signal and output signal of the sampling circuit, avoid the influence of parasitic capacitance and ultrasonic chip output signal bandwidth, realize the decoupling of the limiting relationship of parasitic capacitance and ultrasonic chip output signal bandwidth, so that the switch capacitor circuit of ultrasonic chip can adopt smaller sampling capacitor, more simple layout layout reaches sufficient bandwidth simultaneously;Smaller sampling capacitor greatly reduces chip area, while reducing the load of front-stage circuit, thereby reducing the power consumption of chip.

Platforms and methods for improving correspondence between sensor data and haptic output are disclosed. A platform may include a haptic user device and a data collection system to collect sensor data. The haptic user interface may provide different types of haptic stimulation to a user based on the sensor data. The data collection system has a cognitive input selection system with machine learning to improve the effectiveness of the haptic output to the user. The machine learning is trained on feedback of user behavior. The machine learning improves the effectiveness of the haptic output by determining which type of haptic simulation to provide such that the haptic output logically corresponds to the sensor data, or by determining to vary one or more of a timing, an intensity level, or a duration of the haptic output based on the sensor data.

This invention discloses a high-speed four-switch architecture for digital-to-analog converters, relating to the field of integrated circuit technology. When D0 transitions from high to low, DON transitions from low to high, D1 and D1N are both high, M1 switches from off to on, M2 switches from on to off, and M3 and M4 are off. The tail current source I1 flows the output current to the output node VOUTN through M1 and M6. During this process, the current charges the intermediate node Vx, causing Vx to transition from low to high, and DON to transition from low to high. Due to the presence of cross-coupling capacitor C3, the Vx node is accelerated from low to high, thus accelerating the establishment of node VOUTN. Similarly, the presence of C1, C2, and C4 also accelerates the establishment of nodes VOUTN and VOUTP, thereby accelerating the overall switching speed and significantly improving the sampling rate of the digital-to-analog converter, enabling its widespread application in high-speed fields.

The application provides a multi-channel sampling method, a multi-channel sampling device and a computer readable storage medium. The method comprises the following steps: obtaining trigger source information corresponding to a plurality of sampling channels of a target ADC module; determining a plurality of channel groups corresponding to the plurality of sampling channels according to a target application scenario; determining a first priority of at least one sampling channel included in each channel group according to a first preset rule; determining a second priority of the plurality of channel groups according to a second preset rule; and in the case that the trigger source information indicates that the plurality of sampling channels include a plurality of target sampling channels, sequentially outputting a plurality of conversion signals corresponding to the plurality of target sampling channels according to the first priority and the second priority. Through the application, the problem of high cost when the ADC implements multi-channel hybrid sampling is solved, and the effect of ADC hybrid sampling can be achieved by only simple circuit configuration.

Circuits and methods are disclosed for minimizing charge loss due to negative transient voltages at summing terminals (116, 120) of an analog-to-digital converter (ADC) (104). The ADC is coupled to a multi-bit digital-to-analog converter (DAC) (112A) at the summing terminals (116, 120). The ADC and the DAC include PMOS transistors and NMOS transistors whose timing is controlled to reduce charge loss. The PMOS transistors are turned on before the NMOS transistors. Also, the PMOS transistors of the ADC are turned on at a slower rate than the PMOS transistors of the DAC.

The present application relates to the technical field of electronic circuit, and especially relates to a readout circuit of a terahertz detection array, which comprises: a readout link at least comprising a current feedback instrumentation amplifier, a programmable gain amplifier and an incremental analog-to-digital converter connected in sequence; the current feedback instrumentation amplifier amplifies the signal output by the detector and outputs a first-stage amplified signal, the current feedback instrumentation amplifier comprises an instrumentation amplifier body and a first ripple suppression module, the first ripple suppression module comprises a first redundant segmented current steering DAC and a first DAC code register; the programmable gain amplifier further amplifies the first-stage amplified signal, the programmable gain amplifier comprises a gain amplifier body and a second ripple suppression module, and the second ripple suppression module comprises a second redundant segmented current steering DAC and a second DAC code register. The present application effectively reduces the chip area and power consumption while ensuring that the readout circuit of the terahertz detection array has high gain, low noise and low offset.

This application discloses a method for dynamically adjusting the analog signal filtering coefficient and a temperature measuring device, relating to the field of industrial control technology. The method updates a continuously changing counter by comparing the sampled value with the current output value in real time, and dynamically adjusts the filtering coefficient based on the comparison result of the absolute difference between the two values ​​and preset first and second thresholds. After limiting, the output is updated based on whether the continuous trend of the counter exceeds a set value. This method fundamentally solves the inherent contradiction of traditional fixed-window filtering in simultaneously suppressing spike interference and rapidly responding to changes in real-world operating conditions. The processor of the temperature measuring device is configured to execute the above method, and combined with the three-wire connection method and matching resistor design of the hardware, it synchronously eliminates measurement errors introduced by long wires, achieving an adaptive balance between measurement anti-interference, accuracy, and system response speed. It is particularly suitable for temperature measurement scenarios with high reliability and high dynamic requirements.

This invention relates to a signal transmitter for a spatially distributed multi-parameter electrostatic sensor, comprising a first signal preprocessing circuit, a second signal preprocessing circuit, and a signal processing circuit. The first signal preprocessing circuit performs standard signal preprocessing and is used to multiplex signals from multiple sensors. The second signal preprocessing circuit includes N first signal amplification circuits, a signal superposition circuit, and a second signal amplification circuit. The first signal amplification circuits amplify the signals from each sensor, the signal superposition circuits superimpose the signals from multiple sensors, and the second signal amplification circuits amplify the superimposed signal. By using two different signal preprocessing processes, the appropriate preprocessing process can be selected according to different sensor signals, enabling reliable signal preprocessing.

A multiplying digital-to-analog converter (MDAC) includes an analog-to-digital converter (ADC), a selection circuit, an operational amplifier, a first switched capacitor (SC) circuit, a second SC circuit, a first switch, a second switch, a first load capacitor, and a second load capacitor. The ADC generates a selection signal according to a first input signal and a second input signal. The selection circuit generates a first reference voltage and a second reference voltage according to the selection signal. The first and second SC circuits amplify the signal component of the first and second input signals. The first switch receives the second reference voltage. The second switch receives the first reference voltage. The first load capacitor receives the second reference voltage through the first switch. The second load capacitor receives the first reference voltage through the second switch.

The present application relates to the field of array signal processing, and particularly relates to a high linearity pipeline ADC front-end sampling circuit. In the traditional structure, the sampling current of MDAC and Sub-ADC flows through the output impedance of the input signal source at the same time, which leads to signal-dependent voltage drop and thus introduces nonlinear error. The technical scheme of the present application is to construct a compensation circuit in the Sub-ADC branch, which is opposite in polarity to the input current of the MDAC branch, so that the input currents of the two branches are offset on the output impedance of the signal source, thereby significantly reducing the nonlinear distortion. The present application does not require additional high-gain amplifiers or complex calibration algorithms, and can effectively suppress the nonlinear caused by the input current through circuit structure optimization, and is suitable for high-speed high-precision pipeline ADC design.

The application discloses a kind of multi-channel synchronous acquisition isolation circuits and PCB structure, including multi-channel analog differential signal conditioning circuit, synchronous A / D converter, MCU main control chip, EtherCAT communication circuit and multi-stage isolation power supply architecture;Multi-channel analog differential signal conditioning circuit output end is connected with synchronous A / D converter input end;Synchronous A / D converter is connected with MCU main control chip by SPI bus;MCU main control chip is connected with EtherCAT communication circuit by separate SPI bus;Multi-stage isolation power supply architecture is connected with multi-channel analog differential signal conditioning circuit, synchronous A / D converter, MCU main control chip and EtherCAT communication circuit respectively.In high-precision industrial measurement, the rigorous synchronization of signal and extremely low crosstalk are guaranteed.

The application discloses a kind of unmanned plane efficient terrain data acquisition method and system of adaptive sampling and collaborative compression, belong to unmanned plane remote sensing and three-dimensional terrain reconstruction technical field.It includes: each unmanned plane real-time calculation dynamic terrain entropy value, and compared with dynamic threshold to trigger high-density adaptive sampling;According to entropy, data is divided into structure, texture, detail three layers, and is compressed differently, to generate compressed data stream and metadata abstract;Each unmanned plane exchanges metadata abstract through self-organizing network, and dynamically elects temporary coordination node to generate task instruction, realizes no center collaboration;Ground station receives compressed data stream, after space-time registration, layered fusion, finally reconstructs three-dimensional terrain model.The system includes corresponding module.The application solves the problems of rigid sampling, large data transmission pressure, unrobust collaborative architecture and low data processing efficiency in the prior art, and realizes efficient, high-precision and high-robustness unmanned plane collaborative terrain mapping.

A neural response packet protocol for a cochlear implant for measuring a neural response minimizes a communication error, which can be generated in a cochlear implant system, by flawlessly transmitting data by means of a load shift keying (LSK) method. In addition, in an embodiment, the stability of communication is enhanced by solving a cumulative time error problem due to continuous transmission of '0'. In addition, in an embodiment, power can be saved by supplying power to an element of an external device only during a back telemetry data reception section. This greatly reduces power consumption due to the characteristics of the cochlear implant system in which forward transmission is main data transmission, thereby contributing to extending the lifespan of a battery of the device or minimizing power consumption of the external device. In addition, in an embodiment, by providing a protocol supporting various sampling rates, it is possible to collect various biometric signals from high-speed sampling (e.g., 40 kHz) to low-speed sampling (e.g., 300 Hz). This makes it possible to select an appropriate sampling rate according to the type of a neural signal, thereby enabling more accurate neural signal analysis.

The application belongs to the technical field of electronic circuits. A high-speed data acquisition method and system of an isolation circuit based on a physical loop clock are proposed, a clock signal physical loop path is constructed, data signals and loop clock signals are transmitted through the same digital isolator channel, and then sampled through the internal loop clock domain of the FPGA and processed through the asynchronous FIFO cross-domain, realizing delay automatic offset and seamless data transfer. The application breaks through the isolation delay bottleneck, improves the acquisition rate, can automatically compensate the delay drift caused by environmental changes, avoids the metastability across the clock domain, reduces the design and calibration cost, and is suitable for high-voltage application scenarios such as industrial automation and new energy.

The application provides an analog-digital converter, a method for improving bandwidth of the analog-digital converter and an electronic device, and relates to the technical field of signal processing. A dynamic amplifier and a time-to-digital converter are added in the SAR ADC. The first input end of the dynamic amplifier is coupled with a capacitor array, the second input end of the dynamic amplifier is coupled with a comparator, and the output end of the dynamic amplifier is coupled with the time-to-digital converter. When the comparator enters a metastable state, the dynamic amplifier receives a control signal sent by the comparator, converts an input analog electric signal into a time sequence signal with time, and then converts the time sequence signal into a digital signal through the time-to-digital converter, so that higher resolution is obtained at the same time, that is, the conversion speed of the SAR ADC is improved, and the single-channel bandwidth of the SAR ADC is improved.

The application provides a bionic event-driven reconfigurable analog / digital converter and electronic equipment, which comprises an adjustable signal folding circuit, a dynamic comparator circuit and a bionic control logic circuit, and any two of the adjustable signal folding circuit, the dynamic comparator circuit and the bionic control logic circuit are connected; the adjustable signal folding circuit receives an externally transmitted first voltage signal, folds the first voltage signal to obtain a to-be-compared signal under the condition of triggering a folding action, and transmits the to-be-compared signal to the dynamic comparator circuit; the dynamic comparator circuit generates a comparison result according to the received to-be-compared signal, and transmits the comparison result to the bionic control logic circuit; the bionic control logic circuit generates a bionic clock signal according to the comparison result, and transmits the bionic clock signal to the dynamic comparator circuit; and the dynamic comparator circuit is opened / closed according to the bionic clock signal. The application can reduce the static power consumption generated by the analog / digital converter during operation.

This application relates to a two-stage Gray code counter with redundant bits. An N-bit counter includes a lower counter having a first output of M bits, the lower counter operating at a first count frequency. An upper counter having a second output of N-M+L bits operates at a second count frequency. The second count frequency is equal to the first count frequency divided by 2 (M‑L) An error correction controller is coupled to receive the first and second outputs and to perform operations including comparing L least significant bits (LSBs) of the second output to at least one most significant bit (MSB) of the first output, and correcting N-M MSBs of the second output in response to the comparison. The lower bits of the N-bit counter are the M bits of the first output, and the upper bits of the N-bit counter are the corrected N-M MSBs of the second output.

The application relates to the technical field of digital-analog hybrid integrated circuit design, and provides a resistance-capacitance hybrid analog-digital converter and a quantization method thereof.The resistance-capacitance hybrid analog-digital converter comprises a CDAC capacitor array connected to the positive input end and the negative input end of a comparator, and the output end of the comparator is connected to a SAR control logic circuit; a reference voltage sampling capacitor unit is selected to be connected between the output end of an RDAC resistor array and the ground to sample the output voltage of the RDAC resistor array, or to be connected between the input end of the CDAC capacitor array and the output end of the RDAC resistor array to provide a reference voltage for the CDAC capacitor array; in the sampling stage, the input voltage is stored on the CDAC, and the reference voltage sampling capacitor unit samples the output voltage of the RDAC; in the conversion stage, the comparator obtains a comparison result according to the voltage at the output end of the CDAC, and the switching of the RDAC and the CDAC is controlled through the SAR control logic circuit according to the comparison result, so that the successive approximation analog-digital conversion process is completed.