1562results about "Coding/ciphering apparatus" patented technology

A system and method for adaptive edge-cloud data processing dynamically distributes computational tasks between edge devices and cloud infrastructure in response to changing conditions. The system continuously monitors resource availability, network parameters, and workload characteristics while predicting future conditions using hierarchical forecasting models. A multi-objective optimization approach determines optimal task distribution, balancing processing latency, energy consumption, bandwidth utilization, and result quality. The system implements a partitionable processing pipeline that enables seamless task migration through state synchronization protocols and checkpoint mechanisms. During migration, the system preserves processing continuity by establishing dependencies, creating execution checkpoints, and verifying successful state transfer. Performance metrics may be continuously collected and analyzed to improve future decision-making. The system maintains operational resilience during connectivity disruptions through local decision-making capabilities and eventual consistency protocols, making it suitable for diverse applications including industrial IoT, connected vehicles, healthcare wearables, and smart city infrastructure.

Provided herein are systems, methods, computer-readable media, and techniques for providing trusted artificial intelligence (AI) using Fully Homomorphic Encryption (FHE), comprising: (A) providing a deep neural network (DNN)-based model with modified architecture, wherein the modified architecture at least (i) uses a Gaussian function as an activation function and (ii) removes one or more pooling layers; (B) obtaining encrypted data, wherein the encrypted data are generated by applying the FHE to plaintext data; and (C) generating an inference with the DNN-based model based on the encrypted data. Further provided herein are systems, methods, computer-readable media, and techniques for providing trusted AI using stochastic computing, using noise based computing, using an artificial immune system, and with secure multi-party computation (SMPC) based at least in part on watermarking.

Disclosed herein are systems and methods for threshold cryptography for cloud-based software-implemented hardware security modules. In an embodiment, an encryption system collects at least a decryption-threshold number of private-key shares from a secure store, where the private-key shares correspond to a public key generated in a first secure enclave as part of a secret key set, which also includes a first plural quantity of the private-key shares. The encryption system obtains an ephemeral-hardware-security-module-(eHSM)-encryption key by decrypting the collected private-key shares. The encryption system initializes, in a second secure enclave, a second instance of a first eHSM. The initialized second instance of the first eHSM is encrypted with the obtained eHSM-encryption key.

A device comprises a plurality of hardware, HW, modules including a first HW module comprising a Physically Un-clonable Function, PUF, the first HW module or the plurality of HW modules being communicated with a requester. The device receives (1006), from the requester, a request to transmit an output to the requester. It activates (1008) the PUF, reads a response from the PUF, and adds the response to an output. The device transmits (1012) the output to the requester, and it receives (1002) one or more of a firmware, FW, component, a software, SW, component, or a bitstream, BS, component before receiving (1006) the request from the requester.

A multi-party computation method includes: using a relay apparatus that relays communication between a user apparatus and MPC operation apparatuses in a multi-party computation system including at least one user apparatus and two or more MPC operation apparatuses; having the relay apparatus receive a first encryption key generated by each MPC operation apparatus and further transmit the first encryption key to the user apparatus; having the relay apparatus receive secret shares generated by the user apparatus and encrypted thereby using the first encryption key and a second encryption key generated by the user apparatus and transmit the encrypted secret shares and the second encryption key to each MPC operation apparatus; and having the relay apparatus further receive shares, encrypted using the user apparatus's second encryption key, of the results of operations performed by the MPC operation apparatuses and transmit the shares to the user apparatus.

A method and apparatus for authenticating a physical asset is provided. The method includes obtaining information from a tag associated with the physical asset, wherein the information includes a uniform resource locater (URL) and encrypted information, wherein the encrypted information corresponds to a cryptographic token on a distributed ledger and information about the physical asset. The method further includes transmitting a first message towards an authentication server based on the URL, wherein the first message comprises the encrypted information. The method further includes receiving a second message from the authentication server, the second message comprising an indication of authenticity of the physical asset.

A system and method for adaptive data processing combining compression and encryption. The system analyzes input data characteristics, compares probability distributions, and creates a transformation matrix to convert data into a dyadic distribution. It generates a main data stream of transformed data and a secondary stream of transformation information. The system dynamically selects and applies processing techniques, including transformation, encoding, compression, and encryption algorithms, based on analyzed characteristics and real-time performance metrics. It compresses the main data stream using Huffman coding and implements security measures to protect the output. A feedback loop monitors technique effectiveness, updates a knowledge base, and influences future selections. The system can operate in lossless, lossy, or modified lossless modes, adapting to different application requirements. This approach offers an efficient solution for scenarios where both data reduction and security are critical concerns.

A processor includes an execution unit for executing a message padding instruction including an operand field indicating a register buffering a message block segment of a message block to be padded and a mode field indicating which hash functions is to be applied to the message block. The execution unit includes a padding circuit configured to receive a message block segment from a register indicated by the operand field, where the message block spans multiple registers in a register file. Based on which hash function is indicated by the mode field, the padding circuit selects a byte location in the message block segment at which to insert at least one padding byte and inserts the at least one padding byte at the byte location within the message block segment. The message block segment as padded by the at least one padding byte is written back to the register file.

Methods, systems, and devices for encrypting and decrypting data. In one implementation, an encryption method includes inputting plaintext into a recurrent artificial neural network, identifying topological structures in patterns of activity in the recurrent artificial neural network, wherein the patterns of activity are responsive to the input of the plaintext, representing the identified topological structures in a binary sequence of length L and implementing a permutation of the set of all binary codewords of length L. The implemented permutation is a function from the set of binary codewords of length L to itself that is injective and surjective.

The invention relates to a three-way (horizontal-vertical-diagonal) scrambling image encryption method based on a 2D hyper-chaotic Vincent map, comprising three steps of an image encryption algorithm: computing the initial values and control parameters of the map from the key, generating the chaotic sequence from the Vincent map, scrambling the pixel locations and distributing the pixel values.

A self-timed readout driver for a leakage-based physical unclonable function (L-PUF) device, a L-PUF array using the same, and applications thereof are provided. The self-timed readout driver includes a precharge transistor, an inverter and a leaky device. The precharge transistor has a control end, a first end and a second end. The inverter is electrically connected to the second end of the precharge transistor. The leaky device having a control end electrically connected to ground, a first end electrically connected to the second end of the precharge transistor, and a second end electrically connected to ground. The control end of the precharge transistor is configured to receive an input signal. The inverter is configured to generate a sense enable (SE) signal. The input signal and the SE signal may be used as two input signals for the L-PUF device.

The invention relates to a computer-based image encryption method using a Bessel map with high chaotic performance, which is developed to fill the gaps between a high performance chaotic map and a simple encryption scheme.

Techniques, for secure processing of encrypted data on public resources, include receiving first data, indicating a sequence of reversible Boolean function control (BFC) gates, including a first segment for decrypting, a second segment for operating on the decrypted data, and a third segment for encrypting the resulting data. Second data indicates generic BFC gate rules for replacing a first sequence of two gates operating on an input N-bit word with a second sequence of one or more gates that produce the same output N-bit word. The second data is used to propagate: a gate from the first segment a distance into the second segment or beyond; and, a gate from the third segment a distance into the second segment or before. This produces an obfuscated sequence of reversible gates. Obfuscated instructions based on the obfuscated sequence of gates are sent to the public resources.

A secure processor for a post-quantum cryptography (PQC) algorithm CRYSTALS-KYBER, includes a communication unit, a management unit, a processing unit, and a storage unit. The communication unit is configured to receive and transmit data for the secure processor; the management unit is configured to control the processing unit according to the data; the processing unit is configured to process the data to form encrypted data, decrypted data and key data; and the storage unit is configured to store all data. The secure processor can efficiently and rapidly realize key generation, encryption and decryption of a KYBER algorithm under KYBER1024, KYBER768 and KYBER512 security levels, makes data encryption more complicated, and ensures security of the data.

An apparatus and method for attack-resistant encryption and decryption. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and generate memory access requests including load requests to read data from memory and store requests to store data to memory; and cryptographic circuitry to perform a plurality of rounds of encryption or decryption to encrypt or decrypt the data, respectively, the cryptographic circuitry to perform one or more redundant rounds for a corresponding one or more of the plurality of rounds, the one or more redundant rounds to include spatial or temporal differences relative to the corresponding one or more rounds; the cryptographic circuitry to generate a fault upon detecting a mismatch between an output of a redundant round output and an output of a corresponding round.

A multi-domain masked AND gate includes inner-domain calculations, re-sharing, register stage, cross-domain calculations, and compression. The inner-domain multiplication and the re-sharing are calculated prior to storing the re-shared variables in the register stage. Thus, the inputs to the cross-domain multiplication and the compression are performed on variables that have been refreshed by additional randomness. This AND gate does not need statistically independent inputs, is secure in the probing model even in the presence of glitches, also known as the robust probing model. A two-domain input and two domain output AND gate can be implemented using six (6) registers, four (4) two input logical AND gates, and eight (8) exclusive-OR (XOR) gates. The AND gate may also be used to implement an AES S-box that has two (2) register stages and takes two (2) clock cycles per computation.

A device and a method for performing a cryptographic algorithm A method performed by a device, the device comprising a first processor and a processing module, the method comprising: obtaining, by the first processor, first data, comprising a representation of computer program code that embodies a cryptographic algorithm; obtaining, by the first processor, second data; receiving, by the first processor, a request for a first mechanism to be performed, the request comprising: information identifying the first mechanism; information identifying the first data as corresponding to a program; and information identifying the second data as corresponding to an input; transmitting, by the first processor, to the processing module, a second request for the first mechanism to be performed, the second request comprising: information identifying the first mechanism; information identifying the first data as corresponding to a program; and information identifying the second data as corresponding to an input; and executing, by the processing module, the program represented in the first data taking the second data as the input.

To provide a quantum hash value generation system with quantum resistance, a quantum hash value generation method, and a blockchain network.SOLUTION: A quantum hash value generation system 1 includes a quantum state generator 2 configured to generate an input quantum state based on input data composed of an input bit string including a plurality of input bits, a quantum device 4 configured to convert the input quantum state into an output quantum state, a quantum measuring instrument 5 configured to acquire measurement values of the output quantum state by measuring the output quantum state, a measurement value analysis unit 320 configured to calculate a statistical index of the measurement values based on a probability distribution of the measurement values, and a quantum hash value generation unit 340 configured to generate a quantum hash value of the input data based on the statistical index of the measurement values.SELECTED DRAWING: Figure 1

Embodiments relate to a method and an electronic device for modifying a user interface of the electronic device. The method includes detecting, on the electronic device, a selection of a multi-keypad configuration among a plurality of multi-keypad configurations. Based on the selection of the multi-keypad configuration, a plurality of virtual keys are displayed on the user interface. The method includes receiving, on the user interface, a user touch gestures to configure one or more of the plurality of virtual keys to generate a virtual keyboard. The method includes updating machine learning models, image classifier models, and memory of the electronic device to update and store the generated virtual keyboard including the configuration of the one or more of the plurality of virtual keys to initiate user authentication in real time.

The embodiment of the invention provides an NTT acceleration chip. The chip comprises a twiddle factor calculation module which comprises a plurality of pre-calculation units and a plurality of real-time calculation units, and the plurality of pre-calculation units are used for calculating a plurality of initial row twiddle factors and row-to-row stepping factors by parallel execution and utilization of primitive unit roots; the plurality of real-time calculation units are used for executing one row twiddle factors in the plurality of initial rows obtained by the plurality of pre-calculation units in parallel, and repeatedly and iteratively calculating twiddle factors of other rows according to the inter-row stepping factors; the transpose module comprises a plurality of transpose units and is used for performing transpose processing on the input sequence in parallel to obtain a transpose sequence; and the NTT calculation module comprises a plurality of butterfly calculation units and is used for executing butterfly operation of each order and point number according to the twiddle factor obtained by the twiddle factor calculation module and the transposition sequence obtained by the transposition module in parallel to obtain an output sequence. The NTT calculation efficiency can be improved.

According to various embodiments, a method for encrypting image data for a neural network are disclosed. The method includes mixing the image data with other datapoints to form mixed data; and applying a pixel-wise random mask to the mixed data to form encrypted data. According to various embodiments, a method for encrypting text data for a neural network for natural language processing is disclosed. The method includes encoding each text datapoint via a pretrained text encoder to form encoded datapoints; mixing the encoded datapoints with other encoded datapoints to form mixed data; applying a random mask to the mixed data to form encrypted data; and incorporating the encrypted data into training a classifier of the neural network and fine-tuning the text encoder.

Watermarking is used to track and identify digital images. One claim includes acts of: processing obtained imagery to yield local image information, the local image information being inadequate to reveal a subject depicted in said obtained imagery, using the local image information, resolving geometric distortion of the imagery, the geometric distortion comprising scale and rotation, said resolving yielding geometrically resolved imagery, and detecting the encoded signal from the geometrically resolved imagery using secret detecting information. A great variety of other features and arrangements are also detailed.

Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.

To provide a safety design device, a safety design method, and a safety design program capable of deriving a security parameter whose safety is guaranteed in encryption design based on a Reused-A-LWE problem using a discrete Gaussian distribution as an error distribution.SOLUTION: A safety design device 1 includes: an inputting portion 11 that receives input of parameters n, m, q, s1, s2 of a Reused -A-LWE problem with a discrete Gaussian distribution as an error distribution; a calculation portion 12 that calculates a parameter sb of the LWE problem with the discrete Gaussian distribution as the error distribution from the parameter s1 and a constant C; an acquiring portion 13 that acquires a security parameter λ of the LWE problem by a calculation formula that guarantees predetermined safety; and an outputting portion 14 that outputs the acquired security parameter λ as a security parameter of the Reused -A-LWE problem.SELECTED DRAWING: Figure 1

A hashing circuit includes gates or combinations of gates, each being configured to asynchronously output a state value in response to a respective input to the gate or combination of gates. Each of a plurality of bit inputs is asynchronously coupled to one or more of the inputs to the gates or combinations of gates, and each of one or more of the outputted state values is asynchronously coupled to one or more inputs of other gates or combinations of gates, in combination with one or more of the bit inputs and / or one or more other outputted state values. All or some of the state values, or output bits from a logical function of all or some of the state values, or a combination of a first subset of the state values and a logical function of a second subset of state values, are provided as hash-circuit output bits.

Multiple helper data solutions (a.k.a., helper data images) are generated to produce preselected non-random values (a.k.a., “target values”) from a physically unclonable function (PUF) circuit. Therefore, multiple preselected PUF output values may be generated for a given integrated circuit die, where each the output values are derived from a combination of the chip-unique PUF circuit and the chip-unique helper data solution. These helper data blocks are stored in a nonvolatile memory on the integrated circuit die. In an embodiment, the preselected non-random values may be used as secret encryption or decryption keys. In this manner, multiple secret values can be reliably stored within a chip, using a combination of the chip-unique PUF circuit and the multiple chip-unique helper data solution.

An Advanced Encryption Standard (AES) cryptographic system and a method of performing Advanced Encryption Standard (AES) cryptography. The method comprises the steps of performing multiplicative inversion for SubBytes transformation using two forward-reverse linear-feedback shift registers, LFSRs, pairs; and using different respective initialization seeds for the pairs of forward-reverse LFSRs.

To provide a mechanism for determining whether pieces of confidential information match each other, while maintaining a confidential state.SOLUTION: There is provided a method for determining a fact that pieces of data match each other. The method is configured so that: each of multiple provider servers having confidential information performs processing with respect to its own confidential information, using one or more pieces of prescribed information; processed confidential information is divided into multiple pieces of partial information; a part of partial information are exchanged; at least one of the multiple provider servers or another server executes prescribed calculation using the part of exchanged partial information, and other partial information, without sharing by the multiple provider servers, at least one piece of prescribed information used for the processing; therefore it is determined that pieces of confidential information match each other.SELECTED DRAWING: Figure 3

The system is disclosed for visual marking sensitive documents for leak prevention. Each time an action is taken with regard to a document (e.g., creation, viewing, downloading), that action is added to a distributed ledger, essentially creating a unique hash for a new instance of the document. This new hash is visually embedded in the document as a code comprising a plurality of differently shaded pixels, wherein some of the pixels directly encode information regarding the document (e.g., an account that generated the new instance of the document, a date, a time, a unique ID for the document, etc.) and some of the pixels do not encode information. The code is capable of being scanned either digitally or physically on a printed version of the document, such that the immediate source of the document, corresponding to who leaked the document, is able to be discerned.

Disclosed herein are system, method, and computer program product embodiments for verifying the integrity of a boot process without relying on a boot aggregate value. An embodiment operates by cryptographically validating, by a hardware root of trust, a first code module associated with a digital signature. The embodiment determines that the first code module was cryptographically validated and cryptographically measures the first code module thereby generating a first measurement. The embodiment stores a representation of the first measurement in a first platform configuration register (PCR) of a trusted platform module. The embodiment configures a remote attestation agent to instruct a remote attestation server to attest the value stored in the first PCR. The embodiment transmits a TPM attestation quote to the remote attestation server. The embodiment receives an acknowledgment from the remote attestation server indicating a match between the value stored in the first PCR and an allowed cryptographic measurement.