1896 results about "Digital converter" patented technology

The invention provides a laser radar ranging method based on parallel detection, which relates to the technical field of laser radar ranging, and comprises the following steps: generating N lasers with different wavelengths, splitting beams by a beam splitter, separating optical channels with N independent wavelengths by a demultiplexer, performing frequency shift processing, combining N paths of optical signals after frequency shift through a beam combiner, and combining the N paths of optical signals after frequency shift through a beam splitter; generating a beam of composite reference light containing N wavelengths, wherein each wavelength has a specific frequency shift; signal light returned from a target and the composite reference light are jointly input into a coupler for frequency mixing so as to generate an optical beat frequency signal, and operation processing is performed to calculate the target distance and the target radial speed corresponding to each wavelength. According to the laser radar ranging method provided by the invention, parallel detection of the laser radar can be realized, beat frequency signals corresponding to a plurality of different wavelengths can be distinguished only by integrating a group of detectors, a cross-group amplifier and an analog-to-digital converter, the cost is greatly reduced, and the complexity of the system is reduced.

The invention provides an infrared image sensor and a pixel-level reading circuit thereof, and relates to the field of infrared image sensors. The pixel-level reading circuit is integrated in a single pixel unit, and comprises a direct injection input-level circuit used for converting an infrared light-generated current generated by an infrared image sensor into an analog voltage signal; the pulse frequency modulation analog-to-digital converter is connected with the direct injection input stage circuit and is used for converting the analog voltage signal into a pulse signal; the SR latch is electrically connected with the pulse frequency modulation analog-to-digital converter and is used for carrying out accumulative counting on the pulse signals so as to form digital code words reflecting the infrared light intensity; and the digital logic control unit is electrically connected with the SR latch and is used for transmitting the digital code word to a reading bus of the infrared image sensor, so that the output of a digital signal is realized, and the reading rate of the image sensor is improved.

The invention provides an optical sensing measurement method based on closed-loop adjustment of LED driving, and relates to the technical field of optical sensing. The method comprises the following steps: initializing a system; the microcontroller reads a current value of the analog-to-digital converter and calculates an error; calculating a new set value of the driving current of the light emitting diode according to the error; the microcontroller outputs the new set value to the digital-to-analog converter, the digital-to-analog converter controls the driving circuit to adjust the driving current of the light emitting diode, and after a preset time period, the current value of the analog-to-digital converter is collected; repeating the steps, when the error absolute value is smaller than a preset threshold value, judging that closed-loop convergence occurs, and recording the driving current at the moment and the current value of the analog-to-digital converter as measurement results; and obtaining the sample concentration according to the calibration curve and the driving current in the measurement result. According to the scheme, the dynamic range and the low-concentration precision are remarkably improved, LED aging and temperature excursion are inhibited, the circuit is simplified, and multiple groups of current-limiting resistors and multi-gear change-over switches are not needed.

The invention relates to the technical field of chip delay error dynamic compensation scheme design, in particular to a chip delay error dynamic compensation method and system based on TDC. The method comprises the following steps: measuring the transmission delay of a critical path in real time by using a time-to-digital converter core integrated in a chip; dynamically predicting a future delay error through an embedded algorithm based on the delay measurement value; and according to the predicted delay error, dynamic compensation is carried out on the chip timing sequence, and the compensation comprises adjustment of a clock signal or modification of path delay. A corresponding system includes a TDC core for real-time measurement, an embedded processing unit for running a predictive algorithm, and a dynamic compensation unit for performing compensation. Closed-loop control is formed through real-time monitoring, prediction and compensation, the influence of process, voltage and temperature changes on the time sequence of the chip can be effectively resisted, the time sequence precision, working stability and reliability of the chip are remarkably improved, and the method is particularly suitable for high-frequency and precise measurement chips.

The invention provides a single-ended input successive approximation analog-to-digital converter and an optical module chip. In a sampling stage, upper electrode plates of a plurality of first capacitors are connected with an input voltage Vin, part of lower electrode plates are connected with the input voltage Vin, and part of the lower electrode plates are connected with a reference voltage Vref; the upper electrode plates of the plurality of second capacitors are connected with a reference voltage Vref, part of the lower electrode plates are connected with an input voltage Vin, and part of the lower electrode plates are connected with the reference voltage Vref; in the pre-switching stage, an upper pole plate switch is switched off, and lower pole plate voltages of the multiple first capacitors and the multiple second capacitors are switched according to a preset mode, so that the upper pole plate voltages of the multiple first capacitors are all changed into a first preset voltage Vp, and the upper pole plate voltages of the multiple second capacitors are all changed into a second preset voltage Vn; in the comparison stage, the first preset voltage Vp and the second preset voltage Vn are input into the comparator for first-stage comparison. Through preset switching logic, single-ended analog-to-digital converter input can be converted into differential comparator input.

The invention belongs to the field of storage, and discloses a high-energy-efficiency mixed-precision charge domain in-storage computing architecture and a working method thereof. Comprising a single-slope analog-to-digital converter, a sparsity perception input alignment module, a multi-bit input accumulation module, a controller and an accumulation module, wherein the single-slope analog-to-digital converter consists of an index calculation array, a mantissa calculation array, a shared ramp voltage generator and a bidirectional counter. According to the invention, serial input binary coding based on capacitor voltage is suitable for floating point and integer multiply-accumulate operation with flexible bit width; according to the invention, a shared single-slope analog-to-digital converter (SS-ADC) is introduced to realize maximum index search and index difference calculation; according to the method, a sparsity perception calculation scheme is provided, low-importance input-weight pairs are filtered out through an adjustable threshold value, and invalid power consumption is reduced; according to the method, a multi-bit input accumulation method is further combined, and an ADC redundancy optimization quantization and normalization process is utilized, so that the overall energy efficiency is improved.

The invention discloses an MEMS resonator low ripple error temperature measurement system based on voltage feedback compensation, and the system comprises a trans-impedance amplifier, an analog-to-digital converter, a frequency detection module, a PI controller, a variable gain amplifier, a Schmitt trigger, a first digital-to-analog converter, a biasing circuit, mode switches S1 and S2, and a voltage feedback compensation loop. The compensation loop comprises an amplitude detection module, a lookup table, a second digital-to-analog converter and an adder; the amplitude detection module receives the digital signal from the analog-to-digital converter and outputs a vibration amplitude signal in real time; the lookup table receives the vibration amplitude signal, inquires and outputs a corresponding digital compensation voltage, and converts the digital compensation voltage into an analog voltage through a second digital-to-analog converter; the adder adds the analog voltage and a fixed bias voltage to generate a dynamic bias voltage and applies the dynamic bias voltage to a drive electrode of the MEMS resonator. According to the system, an amplitude-driving end bias voltage feedback compensation loop is introduced, so that the periodic ripples of the resonant frequency are effectively suppressed.

The invention relates to a clock delay circuit for reducing interleaving distortion of a time interleaving pipeline ADC, and belongs to the field of analog-to-digital converters. Comprising a four-channel time-interleaved sampling switched capacitor array, an allowance amplifier module and four groups of delay control circuits, the four-channel time-interleaved sampling switched capacitor array comprises four sampling switched capacitor arrays which are connected in parallel; the four sampling switch capacitor arrays connected in parallel are all communicated with the allowance amplifier module; each group of delay control circuits is correspondingly connected with one sampling switch capacitor array; the delay control circuit comprises a clock generation circuit and a programmable current source array; the programmable current source array is connected with the clock generation circuit; the output end of the clock generation circuit is connected with the corresponding sampling switch capacitor array; according to the invention, the effect of reducing interleaving distortion in the four-channel time-interleaving pipeline analog-to-digital converter is realized, and the performance of the whole analog-to-digital converter is further improved.

An error correction method for a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter (SAR ADC) are disclosed, which relate to integrated circuit technology. The successive approximation register analog-to-digital converter error correction method includes the following steps: a. detecting whether a comparator completes a data comparison within a specified time; if so, performing step b; if not, performing step c; b. after the comparator outputs data, starting a next data comparison cycle, and returning to step a; and c. interrupting the conversion, waiting for a signal to start a next conversion, starting the next data comparison cycle, and returning to step a. The method and SAR ADC can effectively prevent problems relating to (1) slow comparator speed caused by dead voltage and (2) burr interference.

The invention belongs to the technical field of nuclear power, and particularly relates to a nuclear power plant vibration measurement method and device based on a dynamic range technology. Comprising the following steps: sampling vibration signals after gain amplification by using a plurality of analog-to-digital converters with different measuring ranges to obtain an initial digital sequence; the initial digital sequence comprises a signal amplitude; performing amplitude region division on the initial digital sequence according to the magnitude of the signal amplitude to obtain a plurality of signal segments in different amplitude regions, and endowing the analog-to-digital converter with a target weight according to the saturation of the signal segments in the measuring range of each analog-to-digital converter; the saturation is the ratio of the signal amplitude to the upper limit of the measuring range of the analog-to-digital converter; the target weight comprises sub-weights respectively corresponding to a plurality of different signal segments of the analog-to-digital converter; and performing weighted fusion and splicing on the signal segments based on the sub-weights of the analog-to-digital converters in the different signal segments to obtain a target sampling signal.

The invention discloses a temperature sensor, a temperature acquisition device and electronic equipment, in the temperature sensor, a temperature sensing current generation module responds to target temperature change, and provides a first current signal with a positive temperature coefficient for a current conversion module; the current conversion module converts the first current signal into a first voltage signal with a negative temperature coefficient and generates and outputs a second voltage signal to the voltage regulation module according to the first voltage signal, and the voltage value of the second voltage signal is an integral multiple of the voltage value of the first voltage signal; the voltage regulation module receives the second voltage signal and outputs a third voltage signal to the analog-to-digital converter, and the voltage value of the third voltage signal is smaller than that of the second voltage signal; the analog-to-digital converter receives the third voltage signal and outputs a target digital signal, and the target digital signal is used for representing the temperature measured by the temperature sensing front-end circuit. According to the arrangement, the accuracy of temperature detection can be improved, and the temperature sensor is high in accuracy, small in size and low in power consumption.

The invention relates to the technical field of photoelectric detection, in particular to a global self-defined sampling method based on a germanium-silicon photoelectric detector array, which comprises the following steps of: S1, constructing the germanium-silicon photoelectric detector array with an n * t specification, receiving a target optical signal by using each detector unit as a pixel point, converting the target optical signal into an initial current signal, the signal is linearly amplified into a voltage signal through an external transimpedance amplifier; s2, digitalizing the voltage signal into a binary discrete digital signal through a high-speed analog-to-digital converter at the output end of the trans-impedance amplifier; and S3, performing global synchronous sampling to obtain a first group of data, performing repeated sampling in the same mode to obtain multiple groups of data, performing pixel-by-pixel superposition to generate fused data, and performing user-defined setting on the repeated sampling frequency within 1-1024 times. By customizing the number of repeated sampling times and data superposition, adapting to different light intensities and expanding the detection dynamic range, the problems of strong light overexposure and weak light underexposure are solved, the data consistency is guaranteed in combination with global synchronous sampling, and the detection precision and the environmental adaptability are improved.

The invention discloses a logarithmic pixel signal quantization method and module based on gain dynamic adjustment, and an image sensor. The logarithmic pixel signal quantization method comprises the following steps of: converting light current into logarithmic voltage by logarithmic amplification by using a logarithmic response unit; the voltage type comparator compares the logarithmic voltage with a threshold voltage, outputs a gain regulation and control signal for gain configuration of the programmable gain amplifier and input reference voltage switching, enables the programmable gain amplifier to work in different gain modes, and inputs a flag bit to the N-bit analog-to-digital converter; based on the current gain mode, the programmable gain amplifier amplifies the logarithmic voltage and translates the logarithmic voltage into the quantization range of the N-bit analog-to-digital converter to be output; the N-bit analog-to-digital converter samples an output voltage signal of the programmable gain amplifier, combines the output voltage signal with a flag bit, and outputs an N + 1-bit equivalent digital code value signal. According to the invention, high-sensitivity quantization of low-light-intensity signals and high-precision conversion of high-light-intensity signals are realized at the same time.

An analog-to-digital converter, ADC, is provided. The ADC comprises multiple time-interleaved sub-ADCs, a detection circuit, and a calibration circuit. The sub-ADCs are configured to, when the ADC is in a calibration mode, generate a first signal by sampling a calibration signal based on a first clock signal and at least a second clock signal. The first clock signal comprises a phase shift relative to the second clock signal. The calibration circuit is configured to determine a first mismatch between the phase shift and a phase shift threshold based on the first signal. The detection circuit is configured to, when the ADC is in an operation mode, generate a second signal by sampling one of a biased signal to be received by the sub-ADCs or a second calibration signal based on at least one of the first clock signal and the second clock signal. The calibration circuit is configured to determine a second mismatch between the phase shift and the phase shift threshold based on the second signal and calibrate the ADC based on the first and the second mismatch.

The present disclosure generally relates to a test and / or measurement instrument and a method for determining a power of an input signal. The test and / or measurement instrument includes at least one input for receiving an input signal, at least one acquisition circuit, and at least one analysis circuit. The at least one acquisition circuit includes at least one analog-to-digital converter configured to provide a digital signal comprising multiple samples. The at least one analysis circuit is configured to separate different samples of the digital signal into at least two partitions, to transform signal portions of the at least two partitions into frequency domain, to determine for the different transformed signal portions an average part and a variance part, and to determine a constant part of the digital signal by compensating the average part with the variance part.

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

The invention relates to the technical field of power system monitoring, discloses an anti-harmonic PT current monitoring system and method, and aims to solve the problem of secondary side current signal distortion of a voltage transformer caused by power grid harmonic pollution in the prior art. The method comprises the steps of electrifying and initializing a system, starting a high-speed analog-to-digital converter to acquire a voltage signal, executing fast Fourier transform to identify dominant harmonic waves, calculating and configuring a capacitance value of a tunable LC trap unit to suppress specific harmonic waves, and finally outputting a high-fidelity analog voltage signal in direct proportion to fundamental current. The system comprises a current-voltage conversion module, a tunable LC notch filter array, a high-speed analog-to-digital converter, a digital signal processing unit and a microcontroller. According to the technical scheme, dynamic self-adaptive suppression and precise selective harmonic wave blocking of power grid harmonic waves can be realized, low delay and high fidelity characteristics are guaranteed, and the engineering practicability and reliability of the system are improved.

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

The invention relates to the technical field of digital filters, and discloses a quantization sensing wide linear minimum error mode adaptive filter, which performs non-uniform low-bit quantization on an input signal and an expected signal by using a quantization parameter to obtain a corresponding quantization value; constructing a linear factor based on the quantization parameter; based on the non-roundness of the input signal, constructing a normalized correlation matrix of the input signal and the linearized error signal, and constructing a compensation matrix in combination with a linear factor; obtaining input signal quantized values at a current moment and a historical moment, constructing an augmented input signal vector, calculating a product of the augmented input signal vector and the compensation matrix, and constructing a corrected input vector; performing wide linear filtering on the corrected input vector to obtain an output signal, and calculating an error signal in combination with an expected signal quantized value; and updating the weight vector at the next moment by using the corrected input vector and the error signal. According to the invention, by introducing a non-uniform low-bit quantization and deviation compensation mechanism, the cost and energy consumption of the analog-to-digital converter are remarkably reduced, and a relatively low steady-state error is kept.

The invention relates to the technical field of signal acquisition, in particular to a multi-channel signal synchronous acquisition method and system based on an FPGA, and the method comprises the steps: obtaining a multi-channel signal source, connecting a device, and outputting an original analog signal; performing frequency equalization and noise suppression preprocessing on the signal; sampling and correcting a time domain and a frequency domain by using a synchronous acquisition model and an analog-to-digital converter to obtain a corrected digital signal; the storage efficiency is optimized through labeling, block compression and high-speed caching, finally, the data is written into a persistent storage module, and data analysis processing is completed based on a remote instruction. Through time reference adaptive calibration, a distributed clock architecture and a dynamic data flow management strategy, the robustness, expansibility and transmission efficiency of signal acquisition are improved, and the real-time performance and reliability requirements in a complex industrial environment are met.

The invention discloses a deformation rolling stone integrated road slope radar monitoring system and a detection method, and belongs to the field of radar detection, the deformation rolling stone integrated road slope radar monitoring system comprises a signal processing module, a multi-channel radio frequency module and an antenna array module, the multi-channel radio frequency module is connected with the signal processing module through a hardware line, and the antenna array module is connected with the signal processing module. The antenna array module is connected with the multi-channel radio frequency module through a hardware line; the signal processing module comprises a programmable main control chip, a data memory, an analog-to-digital converter and a direct digital frequency synthesizer, a line of the signal processing module is also connected with a camera, and the system also comprises a power supply module for supplying power to the signal processing module, the multi-channel radio frequency module and the camera. According to the deformation and rolling stone integrated road slope radar monitoring system and the detection method, deformation and rolling stone integrated monitoring is realized, two sets of equipment do not need to be arranged, the cost and the arrangement difficulty are reduced, early warning is reliable, the environmental adaptability is high, and the requirement for long-term field road monitoring is met.

The invention provides an alternating-current weak current high-precision detection system and method, and the system comprises a copper-nickel alloy shielding cover which is used for inhibiting space power frequency radiation interference and power system broadband noise, and a magnetic sensitive element which is used for converting the detected magnetic field change into a corresponding initial current signal, the trans-impedance amplifier is used for converting the initial current signal into a voltage signal; the adaptive noise suppression module collects a power frequency fundamental wave reference signal and a harmonic wave reference signal, generates a harmonic wave anti-phase counteracting signal, and performs anti-phase counteracting on real noise of the initial current signal; the analog-to-digital converter is used for converting the voltage signal into a discretized digital signal, and the discretized digital signal comprises a target signal and a random noise signal; and the FPGA coherent demodulation module is used for carrying out cross-correlation operation and narrow-band filtering on the target signal and the random noise signal to separate out a micro-current signal. The technical problems that in the prior art, composite noise covering is limited, the frequency fluctuation adaptability is poor, and microvolt-level signals are difficult to capture are solved.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array to receive current from the columns of the array, the output block comprising a current-to-voltage converter to receive current from one or two columns and convert the current into a voltage, the current-to-voltage converter comprising one or more variable resistors configurable to adjust the range of the voltage; and an analog-to-digital converter to convert the voltage into digital bits.

The invention relates to the technical field of integrated circuit design, and particularly discloses a multi-channel analog-to-digital converter pre-charging buffer, multi-channel analog-to-digital converters share one pre-charging buffer or a pair of pre-charging buffers, and a control switch and an input capacitor of each channel analog-to-digital converter are mutually independent; the analog-to-digital converter of each channel is electrically connected with the output end of one pre-charging buffer or the output end of one pair of pre-charging buffers through the input capacitor and the control switch of the analog-to-digital converter in sequence, and is electrically connected with reference voltage through the input capacitor and the control switch of the analog-to-digital converter in sequence; the input end of the pre-charging buffer or the input end of the pair of pre-charging buffers is electrically connected with the reference power supply. The multi-channel analog-to-digital converter shares one pre-charging buffer or a pair of pre-charging buffers, compared with an existing buffer, only the driving capacity of the output stage needs to be enhanced, other indexes such as bandwidth and gain are kept unchanged, and therefore the overall chip area and power consumption are greatly reduced, and the manufacturing cost is saved.

The present description provides for a method of controlling an analog-to-digital converter. In an example method, the most significant bits are determined by successive approximations. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of a first digital-to-analog converter with a third digital-to-analog converter and by applying a second ramp to the output of the second digital-to-analog converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first digital-to-analog converter and second digital-to-analog converter at the end of the successive approximations.

Aspects of the subject disclosure may include, for example, a digital timing skew compensator, including: a first polyphase adaptive filter bank having a first input and a first output; a first input matrix coupled to the first input of the first polyphase adaptive filter bank; a first subtractor coupled to the first output of the first polyphase adaptive filter bank, wherein the first subtractor removes a first signal generated by the first polyphase adaptive filter bank from digital outputs of sub analog-to-digital converters (ADCs) of a time-interleaved ADC to create a desired signal, wherein the desired signal is coupled to the first input matrix; a modulation matrix that modulates the digital outputs of the sub-ADCs to create a modulated signal vector; a second polyphase adaptive filter bank having a second input and a second output; a second input matrix coupled to the second input of the second polyphase adaptive filter bank; and a second subtractor coupled to the second output of the second polyphase adaptive filter bank, wherein the second subtractor removes a second signal generated by the second polyphase adaptive filter bank from the modulated signal vector to create an error signal, wherein the error signal is coupled to the second input matrix. Other embodiments are disclosed.

The invention provides a current sampling zero offset correction method and device. The current sampling zero-bias correction method comprises the following steps: determining a correction trigger opportunity, wherein the correction trigger opportunity is a moment when an output voltage vector of a power converter is in a zero vector state and a theoretical value of current flowing through a current sampling resistor is zero; sampling a current sampling channel through an analog-to-digital converter at a correction triggering time, and obtaining original sampling data under a zero current condition; processing the original sampling data to obtain a current zero current bias value and updating the stored current bias data variable; a corrected current value is determined based on the updated current bias data variable. By setting the specific correction triggering time and correction mechanism, the current sampling zero bias can be dynamically tracked and corrected online, automatically and in real time in the whole operation process of the driver, adverse effects caused by static deviation and dynamic temperature excursion are overcome, and the control precision and robustness of the system under all working conditions are improved.

The invention discloses a wide-range switch tube leakage current detection method and system, and relates to the technical field of semiconductor device detection, and the method comprises the steps: connecting a to-be-detected NMOS switch tube with a trans-impedance amplifier, and collecting the drain current; the trans-impedance amplifier converts drain current into an output voltage signal V. The switchable feedback resistor at least comprises two feedback branches corresponding to different ranges. When it is detected that the output voltage approaches a negative output saturation threshold, a corresponding gain range is switched; before each measurement period, an analog-to-digital converter is grounded through an analog switch, system offset voltage is sampled, and a digital compensation value of switch tube leakage current is calculated and compensated; rC low-pass filtering and software notch filtering are carried out on the compensated voltage signal, and then sampling is carried out; and comparing the sampling result with a preset threshold value, and outputting a leakage current detection result. According to the invention, the accuracy of the measurement result of the drain current of the NMOS transistor is improved, and the reliability of device performance evaluation is guaranteed.

The invention relates to a metal resonator gyroscope temperature drift online compensation system and method based on parameter real-time identification. The system comprises a metal resonator gyroscope, a field programmable gate array (FPGA), a temperature sensor, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a microcontroller ARM and a memory. The metal resonant gyroscope is used for sensing the external angular velocity; the field programmable gate array FPGA is used for generating an excitation signal and detecting a vibration signal; the temperature sensor is used for detecting the working temperature of the gyroscope in real time; the ADC is used for synchronously converting the collected gyroscope vibration signal, temperature signal and excitation signal; the digital-to-analog converter DAC is used for converting an excitation signal generated by the field programmable gate array FPGA and outputting the excitation signal to the metal resonant gyroscope; the microcontroller ARM is responsible for operating a parameter identification algorithm and compensation calculation; the memory is used for storing initial model parameters, algorithm programs and real-time data. According to the invention, high-precision compensation in a full-temperature zone can be realized, and the zero-bias stability, the scale factor linearity and the environmental adaptability of the gyroscope can be obviously improved.