356 results about "Logic module" patented technology

A decentralized mesh-network platform provides real-time governance, supervision, and audit of large-language-model persona agents in regulated environments such as healthcare. Each computing node hosts processor circuitry, memory, a network interface, and an integrated suite comprising a User-Prompt Interface, Metadata Filter & Enrichment Engine, Persona Role Constructor, Policy Constraint Engine, gating logic module, Supervisor Review Interface, Session Memory Governance Module, Audit Logging Subsystem, cryptographically linked audit ledger, and Fallback Control Module. Devices communicate over a peer-to-peer channel, exchange role-switch tokens, and merge local ledgers into a composite audit graph when connectivity returns. The architecture supports continuous compliance and resilient operation across institutional boundaries, network partitions, and device failures, enabling conversational interaction with heterogeneous medical data while maintaining rigorous credential lineage, policy oversight, and forensic traceability.

The invention discloses an analyzing and editing system and device for high-frame-rate rendering of a PDF document, and the system comprises a file list uploading module which is used for uploading a pdf file and displaying a version historical record list and information; the document analysis logic module is used for reading and analyzing document information, determining a block level sequence of obtained data, deleting useless elements, and carrying out content sorting and splicing according to a layout; the pdf original document display module is used for executing pdf document title display operation, document display page cutting operation, document directory generation operation and document analysis display result operation in original document uploading, and the document directory generation operation comprises the steps of capturing multi-level digital numbers of documents, classifying number types according to matching results of capture groups in regular expressions, and storing the classified numbers in a database; and then numbering processing is carried out through a specified hierarchy mapping rule, and finally a file directory number is obtained. The problems that a traditional tool is inaccurate in analysis, low in editing efficiency and poor in professional adaptation can be effectively solved.

The invention discloses a debugging system and a debugging method of an RISC-V architecture, and relates to the field of processor debugging, the debugging system comprises a debugging host, a transport layer interface, a debugging module, a debugging logic module in a processor core and a monitoring module, and all the components are in communication connection in sequence. According to the invention, by supporting an RV32 / RV64 double-word-length processor, being compatible with a U / S / M full privilege level operation mode and adapting to various mainstream open-source RISC-V cores and self-defined cores, compared with the existing scheme only supporting a single architecture variant, the method does not need to reconstruct debugging logic for different core types, reduces the core adaptation cost, does not need to customize a debugging instruction or a tool chain process, and has the advantages that the debugging efficiency is improved, and the debugging cost is reduced. Through the register and protocol standardization, the method has high compatibility, and the cross-platform debugging cost is reduced.

An energy-conscious workflow planning system based on LLM with dynamic resource allocation, consisting of: a workflow input interface configured to receive workflow-directed acyclic graphs (DAGs), energy budget constraints, system performance constraints, and natural language requests from human operators; a large language model (LLM) logic module connected to the workflow input interface and configured to analyze the workflow specifications and system constraints in natural language, generate energy-conscious planning recommendations based on the analyzed workflow specifications, and provide explainable planning rationales in natural language; a reinforcement learning-based scheduling unit connected to the LLM reasoning module and configured to: receive scheduling recommendations from the LLM reasoning agent, fine-tune task-resource assignments by dynamically adapting to runtime variations, and perform online resource redistribution under runtime variability; an energy monitoring unit configured to: continuously monitor CPU and GPU utilization in heterogeneous clusters, track power consumption and thermal limits per node, and generate energy profiles for system components; a multi-objective optimization engine configured to: perform a Pareto-optimal scheduling analysis that balances energy consumption, lead time and reliability, apply statistical and AI-supported trade-off analyses and ensure optimal resource allocation based on Pareto frontier analysis; a dynamic resource allocation unit configured to: use predictive models that incorporate LLM inferences and feedback from reinforcement learning, reassign tasks between nodes and clusters while minimizing energy consumption and improving system throughput based on the predictive models; a performance optimization module configured to optimize scheduling decisions using multi-criteria optimization analysis; and a user interface that allows human operators to override and refine planning strategies in real time based on verifiable planning reasons.

The invention relates to the technical field of endoscope video processing and intelligent edge computing, in particular to an endoscope video enhancement processing intelligent edge computing system. Comprising a data acquisition module which is used for acquiring an original video frame sequence of edge endoscope equipment in real time; the feature extraction module is used for determining an instantaneous feature vector representing the dynamic change of the operation scene; the criticality quantification module is used for quantizing and generating a surgical event criticality score; the tuning logic module is used for generating a discrete and stable calculation normal form switching instruction; the assembly line switching module is used for responding to the calculation normal form switching instruction and executing an asynchronous weight preheating strategy; the utility evaluation module is used for constructing a dynamic utility function to evaluate system performance; and the threshold value correction module is used for performing closed-loop correction on the high-criticality threshold value by adopting a gradient rising strategy. According to the method, the stability of system decision making is enhanced, the smooth transition of the video processing flow among different calculation paradigms is ensured, and the robustness of the system is improved.

The invention relates to the technical field of water and soil conservation and ecological restoration, in particular to an ecological slope water and soil loss monitoring and restoring system and method.The system comprises a monitoring and restoring node, a monitoring and restoring node and a monitoring and restoring node, the monitoring and restoring node is internally provided with a double-micropore channel for measuring the conductivity of a water sample in a layered mode, and a pore water pressure sensor and a pressure release valve are used for conducting pore pressure monitoring and micro pressure release; a double-verification logic module is built in, two-stage necessity verification and two-stage effectiveness evaluation are achieved, and then the instability risk is accurately judged and self-adaptive repair is achieved. The ecological slope water and soil loss monitoring and repairing system and method solve or at least relieve the problems that an existing system is difficult to distinguish transient disturbance and real instability precursor and lacks intervention effect evaluation and self-adaptive optimization, the instability precursor and disturbance can be accurately distinguished, intervention can be effectively evaluated, self-adaptive optimization is achieved, and the ecological slope water and soil loss monitoring and repairing system and method are provided. And the intelligence, intervention credibility and long-term reliability of the system are improved.

The invention relates to a laser automatic frequency locking control system and method based on cold atom feedback and a matched spectrum, the system comprises a laser module, a spectrum module, a photoelectric detector, a modulation-demodulation module, a digital PID controller and a data acquisition and operation platform, and the output end of the laser is connected with the spectrum module; the detection light output by the spectrum module enters the modulation-demodulation module after passing through the photoelectric detector; an output signal of the modulation-demodulation module enters a digital PID controller, and the digital PID controller is connected with a laser for frequency scanning control and is in two-way communication with a data acquisition and operation platform through a data interface; the data acquisition and operation platform comprises a cross-correlation algorithm processing module, a frequency control logic module, a cold atom feedback processing module and an abnormity management module, and is used for calculating, feeding back, controlling and monitoring the system operation state in real time and completing the automatic frequency locking process. According to the invention, the accuracy of frequency locking point identification and the frequency locking efficiency are improved; and automatic relocking can be achieved, and long-term stable frequency locking operation is guaranteed.

The invention provides a rich text editor component, a structured exporting method and a content editing system, and relates to the technical field of computers. According to the method, a componentization packaging module is used for packaging a rich text editor core library into a single file component based on a front-end componentization framework and completing initialization and destruction of an editor instance in the life cycle of the single file component; the attribute parameter module is used for defining and receiving configuration parameters from the upper calling component, and the configuration parameters at least comprise an editor mode type, a content export format and a remote content address; the core logic module is used for realizing key operation logic of the editor; and the business editor module is used for calling the rich text editor component in a declarative mode in a business application page, so that rapid integration without compiling bottom layer codes is realized. According to the embodiment of the invention, the development efficiency and function flexibility of the rich text editor can be improved.

A memory controller (MC) and a microcontroller unit (MCU) chip are disclosed. The MC is obtained by adding a smart load control (SLC) module to an MC architecture with an ECC logic module. When a CPU is reading contents from first memory, the ECC logic module can accurately identify soft failure locations and correct 1, 2 or more bit errors, and when errors exceeding the error correction ability of the ECC logic module, the SLC module can select a suitable error correction mode for handling the soft failures in the first memory based on conditions of different ECC errors and soft failure locations as well as on the system's error correction need.

The invention discloses a general data exchange system based on a configurable label structure, which relates to the technical field of data processing and information integration, and comprises a parameter module used for establishing an identity authentication mechanism of two exchange parties; the business document module is used for establishing a data structure definition based on a preset exchange demand; the receipt logic module is used for carrying out logic analysis and code decoupling on the data structure definition, generating a marked language script code and an execution instruction, constructing an execution matrix and realizing mapping between a database physical field and a memory logic variable; and the standard adaptation module is used for comparing and checking the content of the generated data and feeding back a checking result to the parameter module to correct the exchange rule and parameter configuration. A more intelligent logic separation strategy is implemented through structural insight, data reading, writing and transmission are cooperatively controlled, complete decoupling of service logic and program codes is achieved through a nested tag structure, and flexibility, universality and maintenance efficiency of data exchange are optimized.

The invention discloses an automatic sealing detection and drainage device and method for an integrated pressure refueling connector, and belongs to the technical field of aviation ground support equipment. According to the device, a detection and drainage function module is highly integrated in a pressure refueling joint body, and the device mainly comprises an overturning covering and sealing module, an embedded detection and gas circuit module and a control and logic module; the core of the device is that a detection cover which can be movably overturned automatically covers the end part of the joint before refueling to form a closed detection cavity, then inflation and pressure maintaining are carried out through a built-in micro gas circuit, the sealing performance is automatically judged according to pressure attenuation or flow change, and the interior of the joint is purged and drained by utilizing detected gas pressure. According to the invention, rapid and automatic self-examination and maintenance of the pressure refueling joint before use are realized, operation with diseases is fundamentally avoided, the safety and reliability of aviation fuel refueling operation are remarkably improved, and meanwhile, digital management of the equipment state is realized.

A short-circuit protection circuit of a half-bridge driving chip relates to the field of short-circuit protection and integrated circuit design, and comprises a pre-driving module for generating a high-side signal and a low-side signal; the half-bridge module is driven, a high-side MOS receives a high-side signal, and a low-side MOS receives a low-side signal; the gate source hardware clamping module is used for carrying out voltage clamping on the high-side MOS when over-current of the over-ground short circuit of the high-side MOS is detected; the phase voltage short-circuit protection module is used for controlling the overcurrent time when the high-side MOS short circuit is over-current, and sending a fault signal to the logic module when detecting that the high / low-side MOS short circuit is over-current; the bus over-current protection module is used for sending a fault signal to the logic module when bus over-current is detected; and the logic module judges whether the short-circuit protection circuit enters a protection state according to the fault signal. According to the invention, the response speed and the protection mechanism are intelligently switched in real time in different overcurrent fault scenes through the three-stage protection circuit, and the circuit has the characteristics of high sensitivity, fast response speed and strong anti-interference capability.

According to the memory controller and the microcontroller chip provided by the invention, on the basis of a memory controller architecture with an ECC (Error Correction Code) verification logic module, an intelligent copying control module is additionally added, and when a CPU (Central Processing Unit) reads corresponding contents in a first memory, the corresponding contents in the first memory are copied; according to the method, the soft failure position can be accurately identified through the ECC verification logic module, errors of 1 bit or 2 bit or several bits can be corrected, and when the error correction capability range of ECC verification is exceeded, the error correction requirements of the soft failure position and the system can be corrected by the intelligent copy control module according to the conditions of different ECC verification errors and the condition of the soft failure position. Different error correction modes are selected to process the soft failure in the first memory, and it is not necessary to generate reset to destroy coherent execution of a program when the error correction capability range of ECC verification is exceeded every time, so that quick correction of soft failure errors is realized under different soft failure conditions, the system operation coherence is improved, and the error correction efficiency is improved. And high reliability of system operation is considered, and various reliability demand scenes are covered.

The invention discloses a switching communication device, a switching communication method and a server, relates to the technical field of computers, and realizes equipment-level decoupling and resource pooling basis by actively managing a GPU (Graphics Processing Unit) through a second interface configured to be in a root complex mode. The on-chip management system and the switching logic module form a control core, a data switching strategy is dynamically executed, and conversion from passive forwarding to autonomous management is achieved. And the virtual port module performs software definition and dynamic allocation on network resources, so that the flexibility of resource utilization is improved. Meanwhile, MAC ports in two modes of direct connection and exchange are supported, so that the device can flexibly construct a high-performance direct connection network or a large-scale exchange network, and the limitation of fixed topology is broken through. And the data processing module ensures high efficiency of data conversion between different interface protocols. According to the device, the communication efficiency and schedulability between the GPUs are improved by integrating high-speed exchange, intelligent management, resource virtualization and flexible networking capabilities.

A computing core particle, a computing chip, and a computing system are provided. Provided is a computing core particle, characterized in that the computing core particle comprises: a storage module, the storage module comprising a plurality of storage layers; the logic module comprises one or more logic layers, each logic layer in the one or more logic layers comprises a control core and a plurality of computing cores, and the control core of each logic layer is connected with the plurality of computing cores of the same logic layer; each computing core of each logic layer is connected with the adjacent computing core; wherein the plurality of storage layers and the one or more logic layers are vertically stacked, and each of the plurality of computing cores of each logic layer is connected to one or more storage layers of the plurality of storage layers.

The invention belongs to the technical field of computer aided design and mechanical engineering, and relates to a parameterized three-dimensional automatic modeling and assembling system and method for a rolling bearing. The system comprises a parameter input module used for obtaining bearing design parameters; the part modeling module is used for generating an inner ring model, an outer ring model, a rolling body model and a retainer model which comprise preset assembly reference surfaces according to the parameters; the assembly logic module is used for automatically positioning the respective three-dimensional models of the multiple parts of the rolling bearing in a three-dimensional space and constructing a complete bearing assembly so as to generate a complete rolling bearing; and the auxiliary function module is used for providing model file management, modeling process visualization and data output functions. The method has the beneficial effects that the traditional dependence on a solid geometric surface is replaced by abstract association of the reference surface and the coordinate system, and high automation, stabilization and parameterization of the modeling and assembling process are realized.

The invention relates to the technical field of online material performance test instruments, and discloses a sensor pulse pressure fatigue test closed-loop control system based on signal drift compensation, which comprises a load excitation execution module, a signal feedback acquisition module and a closed-loop control logic module, the closed-loop control logic module selects a phase-locked characteristic observation window by calculating a load first-order derivative, extracts a dynamic gain coefficient reflecting the response characteristic of a controlled test object in the observation window, and inputs the dynamic gain coefficient into a filter to generate a characteristic variable; the variable is compared with the standard response envelope line, the deviation is calculated, the compensation factor is calculated and superposed to the driving instruction, the real-time correction of the output gain is realized, and through the identification and active compensation of the signal drift, the sensing deviation caused by the structural degradation of the sensitive component is effectively eliminated, and the sensing consistency of the test process is maintained.

A symbolic execution kernel for artificial general intelligence (AGI) and artificial superintelligence (ASI) systems is disclosed. The kernel comprises a cognitive logic module for constraint-based symbolic instruction execution, a cryptographic arbitration engine for ethical branch verification, and a runtime firewall for threat detection and symbolic graph mutation neutralization. Symbolic instructions are processed as constraint-satisfaction problems verified by satisfiability modulo theory solvers and cryptographically sealed for integrity. Behavioral sequences are preserved using Merkle hash trees, and multimodal inputs including electroencephalography signals undergo symbolic verification. Zero-knowledge proofs, dual-kernel consensus, and rollback logic provide resilience against faults and ethical drift. The architecture achieves arbitration within five microseconds and ensures lawful and deterministic execution under hardware or network compromise.

Systems and methods for a new field programmable gate array (FPGA) architecture that is optimized for machine learning (ML) applications are provided. Such ML applications can specifically include, for example, artificial neural networks and deep neural networks. Various embodiments enable the design of faster and more power efficient hardware accelerators for machine learning algorithms, compared to existing FPGAs in the market. This is made possible by hard systolic matrix multiplier blocks, hard activation blocks and soft ML-centric configurable logic blocks. The matrix multiplier blocks are connected to field programmable interconnect resources to enable creation of larger matrix multipliers. The hard matrix multipliers and the hard activation blocks have programmable interconnects between them and neighboring memory or compute blocks on the device.

The invention discloses a graphic editing system and method based on a pluggable interaction driving framework, and belongs to the technical field of computer application. The system comprises a driver manager module used for maintaining a driver registry and managing the life cycle of an interactive driver; the shared service context module is used for providing singleton services such as a graphic service, an event service, a cursor service and a selection service; a plurality of interaction driving modules, each of which packages a graphic interaction behavior and realizes a uniform driving interface; and the graphic data model module adopts an immutable data mode. According to the method, interaction logic is modularized and pluggable and is decoupled from core business logic, so that the technical problems that a traditional graphic editing system is rigid in architecture, difficult to expand and maintain and serious in interaction behavior coupling are solved, and the expandability, maintainability, development efficiency and flexibility during operation of the system are remarkably improved.

A method for conveying a pallet through a pallet sorting system that includes receiving a pallet at a first position. A first set of pallet data is sensed from first sensors, where the first set of pallet data is non-image data. A second set of pallet data is sensed by image sensors. A logic module receives the first set of pallet data and the second set of pallet data. A subset of pallet data is selectively communicated to a machine learning module, which determines a third set of pallet data. A conveyance path is determined based at least on the third set of pallet data.

1. The name of the design product: graphical user interface of configuration gas fire extinguishing controller and fire alarm controller for electronic equipment. 2. The use of the design product: for electronic equipment. 3. The design points of the design product: in the graphical user interface. 4. The picture or photo that best shows the design points: design 1 front view. 5. Design 1 is designated as the basic design. 6. The use of the graphical user interface: adjustment configuration of functions of the fire alarm system. 7. The human-computer interaction mode of the graphical user interface: design 1 front view shows the interface of the new device of project programming of the fire alarm system, by clicking the drop-down arrow of the "device type" column box, design 1 change state diagram 1 is entered to select the device type; after selecting the device type, by clicking the "new" button in design 1 front view, design 1 change state diagram 2 showing the "controller" module is entered. Design 2 front view shows the interface of the "loop" module of project programming of the fire alarm system, by clicking the "point view" button on the right side of an item, design 2 change state diagram is entered. Design 3 front view shows the interface of the "controller" module of project programming of the fire alarm system, by clicking the "gas extinguishing controller" button, design 3 change state diagram is entered. Design 4 front view shows the interface of the "linkage logic" module of project programming of the fire alarm system, by clicking a check box in "zone A", design 4 change state diagram 1 is entered; by selecting "linkage equation" in the column box below "linkage mode", design 4 change state diagram 2 is entered; by clicking the "details" on the right side of a label (for example, general linkage equation 001), design 4 change state diagram 3 is entered. Design 5 front view shows the interface of the "main mapping list" module of "Modbus" of project programming of the fire alarm system, by clicking the "backup mapping list" button, design 5 change state diagram is entered, and design 5 front reference diagram is used to show that design 5 front view can have a drop-down interface. Design 6 front view shows the interface of the "database upgrade and download" module of the connected device of the fire alarm system, by clicking the "upgrade controller firmware" button, design 6 change state diagram 1 is entered; by clicking the "history record export" button, design 6 change state diagram 2 is entered. 8. Other circumstances that need to be explained: other views are omitted. The symbol "X" in the interface views of design 1 to design 6 indicates that the content such as text, symbol, icon, etc. can be changed or replaced.

The invention provides a circuit aging monitoring device and method based on a double-section delay chain and signal upset detection. The circuit aging monitoring device comprises a data upset detection module, a double-section buffer delay chain, a rising edge sampling logic module, a signal comparison module and a falling edge anti-burr judgment output logic module. The data flipping detection module monitors flipping of the input signal and generates an enabling control signal; the double-section buffer delay chain applies two-stage configurable delay to an input signal and outputs signals with different delay degrees; the rising edge sampling logic module is used for sampling and latching each path of signal; the signal comparison module compares the sampling signals and generates a time sequence margin intermediate signal; and the falling edge anti-burr judgment output logic module latches the intermediate signal at the falling edge of the clock and updates the output state only when the enabling is effective.

This application provides a chip structure and a pin multiplexing method in the chip. The chip structure includes: at least one IP module, at least one GIPO pin, and at least one logic module to be tested; at least some IP modules are equipped with at least one pin multiplexing unit and at least one DFT dedicated test interface; each floating pin in the IP module is connected to a corresponding pin multiplexing unit in the IP module; each floating pin is also used to connect to an external test module through a corresponding DFT dedicated test interface; each logic module to be tested is connected to the pin multiplexing unit of the IP module or to the GIPO pin through a data transmission interface; through the design of this chip structure, the floating pins in the IP module can be multiplexed; thereby, DFT testing of the logic module can be achieved using the floating pins, which can reduce the number of GPIO pins multiplexed, improve DFT testing efficiency, shorten testing time, and reduce testing costs.

The present application relates to the technical field of display, and provides a pixel circuit, a pixel array, a display panel, and a display apparatus. The pixel circuit comprises: a digital logic module, configured to generate a pulse width modulation signal; a switch module, connected to the digital logic module; and a driving transistor, connected to the switch module. The digital logic module can control the switch module by means of the pulse width modulation signal, so as to control the on-off of the driving transistor, thereby controlling the brightness of a light-emitting device. The technical solution in the present application can reduce the voltage drop loss of the pixel circuit and reduce the area occupied by the pixel circuit.

The application relates to the technical field of multi-camera photography cloud platform control, and discloses a multi-camera photography cloud platform control system, which comprises a central control host, at least one cloud platform sub-node and a double-channel communication link. The central control host comprises a state machine director logic module, a predictive verification engine, a dynamic path re-planning module and a state transition readiness verification module. The predictive verification engine continuously performs kinematics simulation and safety verification on all potential state transitions in the background. If it is detected that there is a risk of a slip between the cloud platforms, the dynamic path re-planning module will generate a corrected safe motion path. The state transition readiness verification module queries the internal readiness state of the target cloud platform sub-node before actually executing the state transition, so as to ensure that parameters such as focusing and exposure are ready, and the transition can be executed. The application realizes the automatic, high-safety and high-picture-quality collaborative control of the multi-camera photography cloud platform, and improves the professional director production efficiency and picture quality.

The invention provides a method for detecting defects of a vibration damper of a power transmission line through an unmanned aerial vehicle. According to the detection method, a data acquisition module, a deep learning detection module and a subsequent logic module are arranged; the data acquisition module obtains related data of a working site through an unmanned aerial vehicle and inputs the related data into the deep learning detection module; the deep learning detection module is improved on the basis of a Yolov12 model, performs deep learning and training through multi-scale fusion enhancement, an adaptive data enhancement strategy, Backbone network improvement, an IoU-based adaptive positioning loss function and category and confidence joint loss, and is used for analysis processing; the deep learning detection module identifies the damper and related objects thereof from the input image, and transmits a detection result to the subsequent logic module; and the subsequent logic module analyzes the detection result and outputs the state information of the damper in the current image so as to judge whether the damper has the defects such as corrosion, damage, falling, loosening or slippage or not.

Disclosed in the present application are a packet sending apparatus and receiving apparatus. The packet sending apparatus comprises: a first packet sending module (110), a first on-chip cache (120), a first packet receiving module (130), and a first processing logic module (140), wherein the first packet sending module (110) is used for sending, on the basis of a preset packet transmission window, target packets corresponding to packet tasks, and recording sending information of the target packets; the first packet receiving module (130) is used for receiving response packets of the target packets, and updating a first bitmap to the first on-chip cache (120) when the response packets carry the first bitmap, wherein the first bitmap stores identification fields used for indicating the reception status of the target packets; the first processing logic module (140) is used for generating a retransmission request on the basis of the first bitmap and the sending information when packet retransmission is required; and the first packet sending module (110) is further used for generating a retransmission packet on the basis of the retransmission request and sending the retransmission packet.

The invention discloses a PUF (Physical Unclonable Function) circuit based on a memristor cellular automaton and a use method thereof, and belongs to the technical field of integrated circuit design and information security, the circuit comprises a first cellular initialization module, a second cellular initialization module, 2N cellular node modules, 2N-bit excitation signal input terminals, 2N-bit response signal output terminals, and power supply terminals VCC, VDD, VEE and GND, the 2N cellular node modules are connected end to end to form an annular array, N is an integer which is a positive integer multiple of 4, and each cellular node module comprises a Rule30 logic module and a cellular module, so that the problems of high hardware overhead, poor expandability and insufficient attack resistance of a traditional PUF (Physical Unclonable Function) are effectively solved; the circuit structure is simplified; the hardware resource consumption is reduced; and the flexible expansion of response bits is supported.

The DRAM temperature monitoring self-refresh circuit and the DRAM provided by the embodiments of the present disclosure comprise: a self-refresh enabling module, which outputs a clock signal to a reference voltage generating module and a logic module upon receiving a self-refresh enabling signal; the reference voltage generating module determines a first clock sampling signal according to the received clock signal, and generates a reference voltage to a comparison module according to the first clock sampling signal; the comparison module outputs a comparison signal to the logic module according to the reference voltage and a diode voltage; the logic module generates a sampling signal to collect the first clock sampling signal of the reference voltage generating module at a first time according to the clock signal and the comparison signal when the comparison signal is at a high level, so as to generate a temperature identification signal according to the first clock sampling signal, and determine a chip refresh clock according to the temperature identification signal and the clock signal, and generates a reset signal to the reference voltage generating module at a second time, so as to reset the first clock sampling signal of the reference voltage generating module.