1438 results about "Gate array" patented technology

The invention provides a circuit board fault diagnosis method and system based on artificial intelligence, and relates to the technical field of circuit board fault diagnosis, and the method comprises the steps: constructing a three-dimensional electromagnetic field simulation model of a circuit board, setting a plurality of virtual sensing probes in the three-dimensional electromagnetic field simulation model, and generating an electromagnetic field distortion distribution diagram; dividing a fault sensitive area of the circuit board based on the electromagnetic field distortion distribution diagram, outputting a performance degradation rate of each functional area of the circuit board, and generating a fault risk assessment matrix according to the performance degradation rate; performing function reconstruction on the circuit board according to the fault risk assessment matrix, establishing a dynamic fault-tolerant mechanism of the circuit board, generating a task load distribution strategy based on the dynamic fault-tolerant mechanism, and deploying the task load distribution strategy to a field programmable gate array of the circuit board. And self-repairing the circuit board by adjusting the logic structure of the field programmable gate array, verifying the repairing effect and outputting a diagnosis report.

The invention discloses an inference method and system, computer equipment and a storage medium. The method is applied to a target system comprising a central processing unit (CPU), a graphic processing unit (GPU) and a field programmable gate array (FPGA), and comprises the following steps: in response to a request of a target reasoning service, the CPU transmits a target input of the target reasoning service to the GPU; the GPU performs calculation of a pre-filling stage on target input based on a network structure and weight parameters of the large language model to obtain first data including an intermediate calculation result and a final calculation result of the pre-filling stage, and transmits the first data to the CPU; the CPU transmits the first data to the FPGA; the FPGA performs calculation in a decoding stage based on a network structure of a large language model, a weight parameter and the first data to obtain second data and transmits the second data to the CPU; and the CPU takes the second data as the output of the target reasoning service. According to the method, the target reasoning service can be deployed to the GPU and the FPGA in stages, the target reasoning service is completed in a cooperative operation mode, and hardware resources of the GPU and the FPGA are fully utilized.

The present application relates to the technical field of servers. Disclosed are a server system and a communication method therefor. The server system comprises: at least one first processor board and a host server, wherein the at least one first processor board is in communication connection with the host server by means of a switching network; the first processor board comprises a first field programmable gate array chip and a first processor chip; the first field programmable gate array chip and the first processor chip are packaged and interconnected; the host server is configured to transmit host data to the first field programmable gate array chip by means of the switching network; and the first field programmable gate array chip is configured to process the host data, receive request data which is sent by means of the first processor chip, generate a communication protocol message on the basis of the processed host data and the request data, and transmit the communication protocol message to a destination processor board by means of the switching network. By means of the present application, pooling acceleration of a server system is realized, thereby realizing efficient layout of computing power resources.

Aspects of the present disclosure include methods for spectrally resolving light from fluorophores in a sample. Methods according to certain embodiments include detecting light with a light detection system from a sample having a plurality of fluorophores having overlapping fluorescence spectra and spectrally resolving light from each fluorophore in the sample with a generalized least squares algorithm. In some embodiments, methods include estimating the abundance of one or more of the fluorophores in the sample, such as on a particle. In certain instances, methods include identifying the particle in the sample based on the abundance of each fluorophore and sorting the particle. Methods according to some embodiments includes spectrally resolving the light from each fluorophore by calculating a spectral unmixing matrix for the fluorescence spectra of each fluorophore. Systems and integrated circuit devices (e.g., a field programmable gate array) for practicing the subject methods are also provided.

The invention discloses a startup method, a shutdown method, a logic device, a server and a readable storage medium, the logic device is located in the server, the logic device is in communication connection with a field programmable gate array of the server, and after the server is powered on, the logic device is triggered to be reloaded by firmware; after firmware reloading is completed, a standby component of the server is powered on, and the state of the standby component is monitored; after it is monitored that the field programmable gate array is started, level information is transmitted to the field programmable gate array; and after the standby time sequence control is finished, performing power-on time sequence interaction with the field programmable gate array under the condition of receiving a power-on signal, and performing power-on processing on the processor. The method and the device have the technical effects that the startup action can be realized only by performing the standby time sequence and the power-on time sequence on the logic device and the field programmable logic gate array, and decoupling of the startup and shutdown of the server and the substrate management controller is realized, so that the startup and shutdown of the server are accelerated.

The invention relates to the field of intelligent operation and maintenance of a high-speed railway overhead line system, provides a machine learning-based optimization method and system for dropper arrangement of the high-speed railway overhead line system, and aims to solve the problems of insufficient pantograph-catenary coupling stability and relatively low abrasion uniformity of the overhead line system. The method comprises the steps that contact force space distribution characteristics of a pantograph and a contact net are collected, and contact force balance constraint conditions are generated; constructing a line parameter compensation mechanism by combining the track ultrahigh value, the vertical curve curvature and the elevation data of the suspension point acquired by the laser scanner, and outputting a compensation three-dimensional coordinate of the suspension point of the overhead line system; a programmable gate array is adopted to implement parallel acceleration on neural network weight calculation and space coordinate transformation, contact force constraint and compensation coordinates are iteratively processed, and dropper arrangement parameters are generated; based on the segmented tension value and the node offset compensation value, driving equipment to finish accurate adjustment and positioning installation of the dropper. According to the technical scheme provided by the invention, the pantograph-catenary coupling stability and the wear uniformity of the catenary are improved.

Methods to add an “Admission Control / Access Control” system to control access to a “Software-Defined-Deterministic Industrial Internet of Things” (SDD-IIoT) network are described. The SDD-IIoT comprises a “Software Defined Networking” (SDN) control-plane, and many “Software-Defined-Deterministic Wide Area Networks” (SDD-WANs). The SDN control-plane comprises 3 layers of “Zero Trust Architectures”, i.e., rule-based “Attribute-Based Access Control” (ABAC) systems, where subjects can request access to resources. A controller's “Knowledge-Base” consists of a set of facts and rules, which an inference-engine processes to make access decisions. Each SDD-WAN comprises a low-complexity deterministic forwarding-plane, with many simple deterministic packet switches (D-switches), realized with “Field Programmable Gate Arrays” (FPGAs). The forwarding-plane implements “Authenticated Encrypted Deterministic Channels” (AEDCs or D-flows) directly in hardware in layer-3, using Quantum Safe ciphers. Each D-flow has a deterministic data-rate requirement, with delay and jitter requirements. The D-switches can forward encrypted data, according to pre-defined periodic (repeating) deterministic schedules. For a packet to be accepted at the destination, it must be successfully decrypted at the destination in layer-3, using a Quantum Safe cipher. Malicious packets from cyber-attackers will fail the decryption process in layer-3, and thus be detected and removed. Each enterprise has an “Enterprise-Controller”, to control access to its private resources (i.e., computers, data-bases, etc), with an extensive knowledge base of rules. Each SDD-WAN has a “WAN-Controller”, to control the communications between enterprises over the SDD-WAN. If an Enterprise-Controller or WAN-Controller approves a request to establish a new D-flow, the SDN control-plane will download deterministic schedules and secret keys to the D-switches in the forwarding-plane. An IIoT-Controller will control the communications between different SDD-WANs. In an IIoT deployment, there may be 10s of WAN-Controllers, each with 100s of Enterprise-Controllers. These collaborative controllers work together, to control access to the bandwidth of the SDD-IIoT. They can achieve exceptionally-strong cyber-security, where the expected number of successful cyber-attacks per year from external cyber-attackers with Quantum Computers, can be reduced to zero. The SDD-IIoT can achieve security comparable to that offered by “Quantum Key Distribution” (QKD) networks in practice, determined by the computational hardness of cracking Quantum Safe ciphers. The SDD-IIoT can save the industry 10s . . . $100s of billions (US dollars) per year, by exploiting low-cost FPGAs, providing a powerful incentive to innovate layer-3 of the Internet.

The invention discloses an intelligent optimization driving electromagnetic information metasurface multi-dimensional dynamic regulation and control system, solves the problem that the function solidification of an existing metasurface is difficult to dynamically adjust, and belongs to the crossing field of electromagnetic metamaterials and intelligent control technologies. The method comprises the steps that a sensor network collects environment multi-dimensional information of a programmable metasurface unit in real time; the controller processes the environment multi-dimensional information to obtain a multi-dimensional sensing result; the multi-dimensional interaction layer inputs design parameters, the intelligent decision-making layer combines the design parameters and a multi-dimensional perception result to construct a target joint optimization model, reverse design is carried out on the super-surface array coding sequence, and a display array coding pattern and a three-dimensional radiation pattern / two-dimensional radiation pattern are obtained according to the designed super-surface array coding sequence; displaying on the multi-dimensional interaction layer; and the controller performs real-time electromagnetic response reconstruction and 1-bit or 2-bit phase modulation on the programmable metasurface unit through the field programmable gate array according to the designed metasurface array coding sequence.

The provided is a stream processing-based non-blocking oriented FAST and rotated BRIEF (ORB) feature extraction accelerator implemented by a field programmable gate array (FPGA), which mainly includes two innovations: A stream processing-based non-blocking hardware architecture and a cache management algorithm are provided. The accelerator precisely controls and buffers each column of an rBRIEF descriptor computation window by using an algorithm, allowing to receive a new input pixel stream while computing a descriptor, thereby achieving non-blocking processing. An efficient hardware sorting design embedded in an accelerator is provided. Based on a count sorting algorithm, minimal resources are used to implement rBRIEF sorting on hardware, and the rBRIEF sorting is embedded in the accelerator. The accelerator ensures quality of a feature point while achieving high-speed feature point extraction, without significantly reducing accuracy of ORB_SLAM and other algorithms.

The invention relates to a software and hardware SOC (System On Chip) verification system and method based on EDA (Electronic Design Automation) and an FPGA (Field Programmable Gate Array), and belongs to the field of SOC chip verification. The software part comprises an SOC UVM TESTBENCH SOC verification platform, a disk network disk and a T CP protocol client side; and the hardware part mainly comprises a TCP (Transmission Control Protocol) SERVER protocol server side and a SOCTOP (System On Chip Over Programmable). The method is characterized in that advantages of EDA verification and FPGA prototype verification are combined, cross-platform accelerated verification of the SOC chip is realized, the verification period of the chip is shortened, and the verification quality of the chip is improved.

The invention discloses an automatic machine learning collaborative optimization method based on hardware perception. The method is used for design of an integrated learning field programmable gate array accelerator in edge artificial intelligence. The method aims at solving the balance challenge between algorithm performance and hardware resource consumption. The method comprises the following steps: defining a joint optimization space containing algorithm hyper-parameters and FPGA hardware configuration parameters; a collaborative optimization objective function is established, the function is determined by algorithm performance indexes and predicted FPGA hardware resource occupancy, and resource prediction quantifies hardware influence according to algorithm hyper-parameters; and searching according to the objective function in the joint optimization space by utilizing an AutoML optimization algorithm so as to identify the optimal configuration of the balance performance and resources. According to the method, the problems of low resource efficiency and high development cost caused by separate optimization of an algorithm and hardware in the prior art are effectively solved, balanced design is realized, automation is enhanced, and complexity is reduced.

The invention discloses a communication simulation device for simulating a front-end chip in a battery management system, and relates to the technical field of communication testing, the communication simulation device comprises a micro-control unit, a field programmable logic gate array and a daisy chain conversion module which are connected in sequence; the field programmable logic gate array is used for simulating a register of an analog front-end chip in the battery management system and a daisy chain communication time sequence based on the register configuration parameters; the micro-control unit is used for communicating with an upper computer, receiving a register configuration parameter modification instruction of the upper computer, and modifying register configuration parameters in the field programmable logic gate array according to the register configuration parameter modification instruction; the register configuration parameters in the field programmable logic gate array are uploaded to the upper computer; and the daisy chain conversion module is used for communication between the field programmable logic gate array and the tested battery control unit. According to the invention, the test safety can be improved.

The invention provides a laser ranging device based on an FPGA (Field Programmable Gate Array) and a single photon avalanche diode. The device is characterized in that the distance measuring device is composed of a field programmable logic gate array calculation core (1), a quenching circuit (2), a single photon avalanche diode (3), a pulse laser driving circuit (4), a pulse laser (5) and an optical lens system (6), and the field programmable logic gate array calculation core (1) comprises time digital conversion logic (11) and calculation logic (12). Wherein the time-to-digital conversion logic comprises correction algorithm logic (111) and carry chain logic (112). According to the invention, a single photon avalanche diode and a dark counting correction algorithm are combined to solve the problems of low precision, low linearity and short measurement distance of the existing distance measurement device. The method can be used for detecting the distance by laser, and can be widely applied to the fields of automotive electronics, medical treatment, industrial robots, national defense, aerospace and the like.

The invention specifically relates to a radar system for realizing communication and inductance integration, and the system comprises a field programmable gate array signal processing assembly which is used for generating an initial local oscillation signal and a customized initial emission waveform according to a control instruction of an upper computer, and outputting the initial emission waveform to an emission assembly, outputting the initial local oscillation signal to a local oscillation system component; the transmitting component is used for modulating a self-defined initial transmitting waveform, then generating a target transmitting signal and transmitting the target transmitting signal; the receiving component is used for receiving the reflected signal and modulating the reflected signal; the local oscillation system component is used for performing frequency conversion processing on the initial local oscillation signal and outputting a first LO signal subjected to up-conversion processing to the transmitting component, so that the transmitting component modulates the first LO signal and a customized initial transmitting waveform; and outputting the second LO signal subjected to down-conversion processing to a receiving component, so that the receiving component modulates the second LO signal and the reflected signal.

The embodiment of the invention provides a broadband signal dynamic generation method and system based on multiple clock sources, and the method comprises the steps: monitoring a target frequency in real time through a field programmable gate array, and automatically switching to a corresponding target clock source based on a frequency band to which the target frequency belongs; correcting the phase difference corresponding to the new and old target clock sources through a phase compensation register when the target clock sources are switched, and loading a compensation value to a phase offset register of a direct digital frequency synthesis chip; a fundamental waveform of a broadband signal is generated based on a direct digital frequency synthesis chip, multiple harmonic components are superposed through a fractional accumulation method, and each harmonic amplitude is independently controlled through a look-up table method; an output signal of the power amplifier is collected through the analog-to-digital converter, error information of the actually measured waveform and the theoretical waveform is extracted, the phase offset register and the harmonic amplitude look-up table coefficient are dynamically corrected, and a target broadband signal is output. Unification of broadband coverage, high resolution and quick response is realized.

A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data is provided. Particularly, a genomics analysis platform for executing a sequence analysis pipeline is provided. The genomics analysis platform includes one or more of a first integrated circuit, where each first integrated circuit forms a central processing unit (CPU) that is responsive to one or more software algorithms that are configured to instruct the CPU to perform a first set of genomic processing steps of the sequence analysis pipeline. Additionally, a second integrated circuit is also provided, where each second integrated circuit forming a field programmable gate array (FPGA), the FPGA being configured by firmware to arrange a set of hardwired digital logic circuits that are interconnected by a plurality of physical interconnects to perform a second set of genomic processing steps of the sequence analysis pipeline, the set of hardwired digital logic circuits of each FPGA being arranged as a set of processing engines to perform the second set of genomic processing steps. A shared memory is also provided.

The invention provides a chip aging test system and method based on a field programmable gate array, and the system is characterized in that a drive control panel comprises a processor module, a communication interface module, and an external connector module; the external connector module comprises a first connector and a second connector; the processor module is used for receiving a test instruction sent by the upper computer through the communication interface module, generating a test signal and a control signal, and receiving a test result acquisition instruction sent by the upper computer after the communication interface module sends response information to the upper computer; the first end of the processor module is also used for sending the interrupt information to an upper computer through the communication interface module and displaying the interrupt information; and the third end of the processor module is connected with the second connector and is used for outputting the control signal to the test board. Test signals are output to multiple groups of tested chips of the test board in parallel through the first connector, the second connector controls the test sequence of the to-be-tested chips on the test board, and hundreds of chips are driven by a single drive board and used for aging test.

The invention discloses a digital frequency band protection method for an integrated radio frequency system, belongs to the technical field of integrated radio frequency integration, and is used for performing receiving protection processing and transmitting protection processing on signals in a digital signal processing stage between a broadband radio frequency transceiving subsystem and a signal processing subsystem in the integrated radio frequency system. According to the method, from the aspect of frequency division multiplexing, required signal frequency points are selected through the configurable band-pass filter bank for subsequent processing, and frequency points interfering other load systems are filtered through the configurable band-stop filter bank, so that the frequency band protection function of the integrated radio frequency system is achieved, and guarantee is provided for multi-load cooperative work; meanwhile, through flexible implementation of a field programmable gate array (FPGA) device, the method can multiplex a hardware platform with a broadband radio frequency transceiving subsystem or a signal processing subsystem, and the problem that independent equipment must be adopted in a traditional electromagnetic signal processing method is solved.

The invention discloses a wind-feeling-free radiation type five-constant air conditioner multi-target self-adaptive optimization method and system, and belongs to the technical field of digital monitoring. A personnel density heat and humidity load model and a building heat and humidity response RC network model are established, long and short term memory neural network training is combined, and a humidity load increment rate and a temperature rising rate prediction value are output; a non-dominated sorting genetic algorithm is utilized to dynamically adjust temperature and humidity control weights, an optimal parameter combination is generated, and LSTM parameters are optimized through incremental learning; edge computing nodes are deployed, and LSTM reasoning and NSGA-II non-dominated sorting operation is accelerated by means of a tensor reasoning engine and a field-programmable gate array; a double-time scale strategy is adopted, a quick response layer directly outputs a control quantity during load fluctuation, a deep optimization layer is started to synchronously optimize energy efficiency and comfort after stabilization, energy efficiency is saved, real-time response in a personnel sudden increase scene is realized, algorithm time is compressed to match personnel sudden increase time scale, and energy efficiency and comfort are synchronously improved.

The invention relates to the technical field of fuel cell monitoring and health management, and discloses an intelligent cooperative high-power proton exchange membrane fuel cell life prediction and fault diagnosis method and system, and the method comprises the following steps: S1, collecting multi-dimensional data of a stack key region in real time through a distributed sensing array; s2, removing noise and abnormal values of the collected data, and carrying out feature extraction; s3, constructing a dual-model collaborative prediction framework; s4, inputting the real-time features into the double models; s5, generating a maintenance strategy and early warning; according to the invention, special hardware accelerators such as a graphic processing unit or a field-programmable gate array are integrated on the edge computing module, so that the processing speed and efficiency of high-frequency and multi-source sensor data at a local end are remarkably improved; a distributed computing framework is adopted in a cloud analysis module to process mass feature data transmitted by an edge end, so that the capability and scale of the system for performing deep analysis on the health state of the fuel cell, accurately predicting the remaining service life and quickly tracing the fault are enhanced.

A field programmable gate array includes a configurable interconnect structure connecting logic blocks that implement circuitry to: receive input data including data values organized into rows and columns, each row having N data values; selecting R [i] unmasked data values of a row of the input data according to the mask and the index i of the row; selecting N-R [i] unmasked data values of the other line of the input data according to the mask and the index of the other line; merging R [i] unmasked data values of the row and N-R [i] data values of the other row into a combined data vector of N data values; and calculating R [i] normalized values based on the R [i] unmasked data values of the combined data vector and calculating N-R [i] normalized values based on the N-R [i] data values of the combined data vector to generate N normalized data values.

The invention discloses a data acquisition system and method in a CT (Computed Tomography) system, the system comprises a control end and an acquisition end, a first FPGA (Field Programmable Gate Array) module and a second FPGA module are respectively arranged in the control end and the acquisition end, a forward error correction coding module and a data transmitting module are arranged in the first field programmable gate array FPGA module, and a forward error correction decoding module and a data receiving module are arranged in the second field programmable gate array FPGA module; wherein when the control end sends control command data to the acquisition end, the forward error correction encoding module encodes the control command data and then sends the control command data to the forward error correction decoding module through the data sending module, so that the second forward error correction module recovers the encoded control command data; and the data receiving module receives the recovered data. A data forward error correction technology is added to serial communication, so that a receiver does not receive wrong data, and the defects of related technologies are overcome.

An optical transceiver includes an electro-optic front end; a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) connected to the electro-optic front end; and one or more Field Programmable Gate Arrays (FPGAs) connected to the DAC and the ADC, wherein the one or more FPGAs are connected to one or more of a local memory and a remote storage for loading FPGA bit files, and wherein the one or more FPGAs are loaded with a forward error correction (FEC) encoding app and a FEC decoding app. The FEC encoding app and the FEC decoding app can be selected based on any of an optical application and a standard compliance requirement.

The invention provides an accelerator determination method based on a field-programmable gate array, an image processing method, equipment and a storage medium, which can be applied to the technical field of image compression. The accelerator determination method based on the field programmable gate array comprises the steps that a fusion factor list is determined according to the number of fusion units corresponding to a network model, the fusion factor list comprises a plurality of fusion factors, and the fusion factors represent the number of the fusion units needed for fusing the fusion units in the network model into a fusion structure; under the storage constraint and bandwidth constraint of the field programmable gate array, determining a target fusion factor from the plurality of fusion factors according to the image data block parameters and the fusion network parameter sets respectively corresponding to the plurality of fusion factors; and according to the target fusion factor and the fusion network parameter set corresponding to the target fusion factor, performing parameter mapping on the field programmable gate array to obtain an accelerator for realizing image compression.

The invention belongs to the technical field of optical fiber gas sensing, and discloses an optical fiber photoacoustic gas sensing system and method suitable for a low-pressure environment. The system comprises a programmable logic gate array circuit, a distributed feedback laser, a laser transmission optical fiber, an optical fiber photoacoustic sensing probe, a super-radiation light-emitting diode light source, an optical fiber circulator and a spectrograph. The air pressure is monitored according to the linear relation between the resonance frequency of the cantilever beam and the ambient air pressure, the characteristic that the acoustic sensitivity at the resonance position of the cantilever beam is enhanced under the low air pressure is utilized to make up for signal attenuation in the photoacoustic excitation process, and the sensitivity is corrected in combination with the air pressure measured by the cantilever beam. Therefore, high-precision and high-sensitivity detection of trace gas in a low-pressure environment is realized. The system only adopts a single cantilever beam and a single demodulator, has the functions of gas pressure and gas concentration detection, and can realize accurate detection of trace gas in a gas pressure change environment. And an all-fiber scheme is adopted, so that intrinsic safety is realized, and remote measurement and multi-point network group detection are easy.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

A multi-channel analog-digital converter (ADC) subsystem for test device such as a spectrum analyzer may include multiple multi-channel ADCs to receive down-converted signals and convert the received signals to digital output signals, a field programmable gate array (FPGA) to select one or more ADCs based on a frequency, a bandwidth, and / or a signal type of each received signal and a characteristic of each ADC, and an ADC sample clock to provide a clock signal to the selected ADCs. Characteristics of the ADCs may include a resolution, a signal-to-noise-and-distortion ratio (SINAD), an effective number of bits (ENOB), a signal-to-noise ratio (SNR), a total harmonic distortion (THD), a total harmonic distortion plus noise (THD+N), and / or a spurious free dynamic range (SFDR).

A hardware apparatus for isolated virtual environments includes graphics processing unit comprising a first dedicated memory and a first plurality of processing cores, a central processing unit comprising a second dedicated memory and a second plurality of processing cores, a field programmable gate array comprising a third dedicated memory, a control and data bus assembly connecting the field programmable gate array, the central processing unit, and the graphics processing unit, and a hypervisor located on a non-volatile memory of the hardware apparatus, the hypervisor configured to create one or more virtual machines by isolating the graphics processing unit, the central processing unit and the field programmable gate array.

The invention discloses a system-on-chip, a system-on-chip configuration method and electronic equipment. The system on chip comprises a multi-core RISC-V processor and a field programmable gate array (FPGA), the FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after the initial configuration is completed by power-on starting; the multi-core RISC-V processor is configured to start a bootloader according to the initial configuration completion signal, and the bootloader is configured to start the bootloader according to the initial configuration completion signal; under the condition that an FPGA reconfiguration event occurs, a reconfiguration request signal is sent to the FPGA; the FPGA is further configured to set a storage position to obtain new configuration data, and after reconfiguration is completed, a reconfiguration completion signal is sent to the multi-core RISC-V processor; the multi-core RISC-V processor is further configured to execute system interface reinitialization and / or configuration parameter updating according to the reconfiguration completion signal. According to the scheme of the invention, a bidirectional configuration mechanism between the FPGA and the RISC-V is realized based on the standardized interaction signal, and the dynamic configuration / upgrading requirements of system functions are fully met.

The invention discloses a method and a system for debugging and running a brain-like computing chip, compared with the prior art, the system comprises an upper computer and a lower computer, the upper computer and the lower computer are connected through a transmission control protocol to improve the reliability of communication transmission, a command buffer module is introduced into the upper computer, and the command buffer module is connected with the lower computer. The upper computer packages communication data and a command header and puts the communication data and the command header into a command buffer module, so that one-time connection between the upper computer and the lower computer is realized, the overhead of multiple times of connection is reduced, and the communication efficiency is improved; in the lower computer, a sending module and a receiving module of a field programmable gate array based on a first-in first-out queue and a handshake mechanism play a role in buffering communication data, congestion control of the communication data is realized, and communication complexity is reduced.