1588 results about "Gate array" patented technology

A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell area. The conductivity and drive strength of the dual gate device may be selectively tuned through independent processing of manufacturing parameters to provide an asymmetric circuit response for the device or a symmetric response as dictated by the circuit application.

Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a logic block, a plurality of in-block accessible registers. A register-feeding multiplexer means may be provided for allowing each of the plural registers to equivalently capture and store a result signal output by the corresponding, base LUT of the plural registers. Registerable, primary and secondary feedthroughs may be provided for each base LUT so that locally-acquired input signals of the LUT may be fed-through to the corresponding, in-block registers for register-recovery purposes without fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage, input switch matrix (ISM) may be further provided for acquiring and routing input signals from adjacent, block-interconnect lines (AIL's) and/or block-intra-connect lines (e.g., FB's) to the base LUT's and/or their respective, registerable feedthroughs. Techniques are disclosed for utilizing the many in-block registers and/or the registerable feedthroughs and/or the multi-stage ISM's for efficiently implementing various circuit designs by appropriately configuring such register-intensive FPGA's.

A multi-function health monitor is capable of performing a resting 12-lead ECG test, an ECG stress test, a 24-hour holter monitor evaluation and or a 30-day MCT monitoring. Using only 3 electrodes, the multifunction health monitor derives 6 channels (Limb leads & Augmented leads) of data with the noise cancellation (ground) effect of a virtual dynamic RL electrode. An electrode resistivity measurement system quantifies and may compensate for increasing resistance the electrodes and the patient that results from the length of time the electrodes are installed on a patient. The multi-function health monitor can provide data analysis through the gate array as the data is acquired. Data may also be stored for remote analysis as well as for transmission to remote stations upon occurrence of one or more threshold events. Parameters for threshold events may be adjusted remotely to obviate the need for a patient to travel for system adjustment.

The Field Programmable Instrument Controller (FPIC) is a stand-alone low to high performance, clocked or unclocked multi-processor that operates as a microcontroller with versatile interface and operating options. The FPIC can also be used as a concurrent processor for a microcontroller or other processor. A tightly coupled Multiple Chip Module design incorporates non-volatile memories, a large field programmable gate array (FPGA), field programmable high precision analog to digital converters, field programmable digital to analog signal generators, and multiple ports of external mass data storage and control processors. The FPIC has an inherently open architecture with in-situ reprogrammability and state preservation capability for discontinuous operations. It is designed to operate in multiple roles, including but not limited to, a high speed parallel digital signal processing; co-processor for precision control feedback during analog or hybrid computing; high speed monitoring for condition based maintenance; and distributed real time process control. The FPIC is characterized by low power with small size and weight.

There is provided a hardware device for monitoring and intercepting data packetized data traffic at full line rate. In preferred high bandwidth embodiments, full line rate corresponds to rates that exceed 100 Mbytes/s and in some cases 1000 Mbytes/s. Monitoring and intercepting software, alone, is not able to operate on such volumes of data in real-time. A preferred embodiment comprises: a data delay buffer (208) with multiple delay outputs (216); a search engine logic (210) for implementing a set of basic search tools that operate in real-time on the data traffic; a programmable gate array (206); an interface (212) for passing data quickly to software sub-systems; and control means for implementing software control of the operation of the search tools. The programmable gate array (206) inserts the data packets into the delay buffer (208), extracts them for searching at the delay outputs and formats and schedules the operation of the search engine logic (210). One preferred embodiment uses an IP co-processor as the search engine logic.

A system and a method is provided for the detection and capture, and in particular for an ultra high speed detection and capture, of transients in input voltages by an intelligent electronic device. The system and method detects transients for input voltages in either phase to phase or phase to neutral measurements and permits a user to set threshold levels for detecting transients in input voltages. In an embodiment, the system and method further provides a field programmable gate array as a controller for managing transient detection. The field programmable gate array includes a state machine for determining the state of the sampled signal with respect to a threshold level at a specified waveform sample period.

A method and apparatus for processing data within a programmable gate array begins when a fixed logic processor that is embedded within the programmable gate array detects a custom operation code. The processing continues when the fixed logic processor provides an indication of the custom operational code to the programmable gate array. The processing continues by having at least a portion of the programmable gate array, which is configured as a dedicated processor, performing a fixed logic routine upon receiving the indication from the fixed logic processor.

A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

The invention discloses a self-adaptive predistortion method, which comprises the steps: collecting emission data and feedback data, calculating loop delay according to the emission data and the feedback data, carrying out time unifying to input signals according to the loop delay, compensating collected delay of the emission data and the feedback data according to the loop delay, estimating a predistortion model parameter, constructing a matrix according to the set predistortion model parameter, calculating a predistortion parameter corresponding to a power amplifier, adopting a curve fitting method to sample and quantize the predistortion parameter to obtain an LUT table, modifying the predistortion parameter in a digital predistorter according to the LUT table, carrying out digital predistortion to the input signals according to an LUT address and the predistortion parameter which is modified, and generating the LUT address according to the amplitude of the input signals. The technical scheme of the invention saves the hardware implementation cost and can be realized in an FPGA (programmable gate array) easily.

A field programmable gate array assembly (100, 200, 300) offers the unique functionality typically reserved for custom ICs and application specific integrated circuits (ASICs) with the flexibility of a programmable gate array. This is accomplished by modifying a package for a programmable IC (102), such as a programmable gate array, to electrically and mechanically couple to another IC (104). The preferred electrical and mechanical coupling occurs by stacking the IC on the programmable IC.

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

A method of fault tolerant operation of field programmable gate arrays (FPGAs), whether as an embedded portion of a system-on-chip or other application specific integrated circuit, utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into a self-testing area and a working area. Within the self-testing area, programmable interconnect resources of the FPGA are tested for faults. Upon the detection of one or more faults within the interconnect resources, the faulty interconnect resources are identified and a determination is made whether utilization of the faulty interconnect resources is compatible with an intended operation of the FPGAs. If the faulty interconnect resources are compatible with the intended operation of the FPGA, utilization of the faulty interconnect resource is allowed to provide fault tolerant operation of the FPGA. If the faulty interconnect resources are not compatible with the intended operation of the FPGA, on the other hand, a multi-step reconfiguration process may be initiated which attempts to minimize the effects of each reconfiguration on the overall performance of the FPGA. In an alternate embodiment, the entire FPGA may be configured as one or more self-testing areas during off-line testing, such as manufacturing testing.

A bus macro for use as a routing resource for partial reconfiguration of a field programmable gate array (FPGA) with a design that has interdesign routing with at least one other design programmed into the FPGA comprises: at least one row of bus lines disposed within the FPGA between at least two design areas; a first set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from a first design area to a second design area of the FPGA according to a first routing configuration embedded in the first design area; and a second set of gates disposed within the FPGA for controlling a routing of signals over the at least one row of bus lines from the second design area to the first design area of the FPGA according to a second routing configuration embedded in the second design area. A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA is also disclosed utilizing at least one bus macro.

A master-slave type flip-flop circuit consisting of a master latch and a slave latch, wherein the master latch comprises: a first clocked inverter to which data are input and a first latch circuit configuring a closed circuit with a first inverter and a second clocked inverter so that an output of the first clocked inverter is input to the first inverter and; the slave latch comprises: a transmission gate to which an output from the first latch circuit is input and a second latch circuit configuring a closed circuit with a second inverter and a third clocked inverter so that an output of the transmission gate is input to the second inverter, respective components configuring the master latch and the slave latch are configured with Sea Of Gate (hereinafter to be referred to as SOG) configuring a gate array, a basic cell of the SOG consists of triplely arrayed N-type transistors and corresponding triplely arrayed P-type transistors, the triplely arrayed N-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size and the triplely arrayed P-type transistors consist of double-arrayed normally sized main transistors and one auxiliary transistor sized smaller than in a normal size.

The present invention belongs to the automatic driving technical field and relates to an expressway-based embedded integrated automatic driving controller. The expressway-based embedded integrated automatic driving controller comprises an automatic driving sensing unit, a vehicle vertical and horizontal action control module, a driving mode switching control module and a human-computer interaction control module which are all integrated on a programmable gate array; the programmable gate array comprises at least a data transmission interface, a control signal transmission interface and a human-computer interaction interface, wherein the data transmission interface carries out data interaction with an environment sensor and a vehicle speed sensor, the control signal transmission interface can transmit control instructions to an execution unit, and the human-computer interaction interface transmits signals to a human-computer interaction system. A whole set of automatic driving system with functions such as sensing integration, path planning, decision planning and control is integrated into an embedded controller, so that the expressway-based embedded integrated automatic driving controller can be realized, and automatic driving functions such as adaptive navigation, lane keeping, autonomous lane changing, autonomous overtaking, autonomous acceleration, emergency braking and automatic pull over can be realized, and the size of the automatic driving system can be greatly decreased, and the power consumption of the system is decreased. The controller is easy to realize mass production.

The invention discloses a field-programmable gate array (FPGA) configuration file update device. A microprocessor/microcontroller imports an FPGA configuration file from an external memory through a universal plug and play interface, and transmits the FPGA configuration file to an FPGA chip; the FPGA chip converts the FPGA configuration file into a data format capable of being identified by a nonvolatile memory, transmits the converted FPGA configuration file to the nonvolatile memory for storage, and updates the FPGA configuration file; and after a digital system is electrified again, the FPGA chip automatically reads the updated configuration file stored in the nonvolatile memory to realize automatic loading and normal operation. In the device, only when the FPGA configuration file needs to be updated, a new FPGA configuration file is written into the nonvolatile memory so as to realize the requirement of online configuration; and meanwhile, the microprocessor/microcontroller provides the interface for the external memory and reads the FPGA configuration file into the personal memory, and then the FPGA configuration file is written into the nonvolatile memory so as to realize the update of the FPGA configuration file and avoid the limitation of a special downloading line.

The real-time measuring device and measuring method for the draft of a navigable ship according to the present invention are composed of a detection door, an automatic lifting control device for the detection door and a data acquisition and processing device; the detection door is a mounting frame, and the detection door is composed of The automatic lifting control device controls it to reach a predetermined depth position below the water surface, and is placed below the water surface that the navigable ship will pass through. An array of ultrasonic ranging sensors is installed on it, and the front of the ultrasonic ranging sensor is upward; The distance sensor array measures the vertical distance from the bottom surface of the entire ship to the detection door mounting frame, and all the measurement data constitute a data set C; then according to the installation depth H of the ultrasonic ranging sensor array on the detection door mounting frame, the water depth at the bottom of the ship will be obtained The data set D, where D=H-C; then find the maximum value in the data set D, which is the draft Dmax of the navigable ship, that is, Dmax=MAX(D).

The invention provides a test method for field programmable gate array single particle effect, relating to an integrated circuit technology. The invention comprises the following steps: 1) the package of FPGA is removed, and FPGA is arranged on a test circuit board; 2) FPGA is configured, and then SRAM data are read back and recorded; 3) the test circuit board is arranged in a test room and a particle source emits single particles to bombard FPGA; 4) SRAM data are read back and recorded; 5) data of steps 2) and 4) are compared, and reversed digits of SRAM are determined; 6) when the reversal times reach a preset value or after the period of time without reversal reaches a preset time value, the particle source is changed, FPGA is electrified again, the FPGA is confirmed to return to the initial state, and then steps 3) and 5) are repeated; 7) the data are processed: the reversal section of the LET value is calculated and a reversal curve is generated. The method can precisely test the impact of the single particle effect and eliminate external interferences, thus ensuring the correction and reliability of the test results.

A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested. Upon successful testing, the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories. A design integrator may review the memory designs output and further integrate the memory, its timing, testing, etc. with other blocks and functions of the integrated circuit.

The invention relates to the medical slice imaging and nuclear-imaging field, in particular to a first-group board card, a signal buffering unit, a second-group receiving board card, a data buffering unit, a reference clock 17, a clock adjusting unit and an on-site programmable gate array that are used for a conforming system in a positron slice scanning device; the method is characterized in that the on-site programmable gate array is utilized to judge the time, the position and the energy among all matters, and two matters that pass through the judging and selecting regulations form a conforming case. By inducting the on-site programmable gate array, the case information captured by a front-end detector module of a PET apparatus can be processed fast and high-efficiently by compiling hardware description language, so as to ensure whether the conforming matters happen or not. The method is an improvement of the process of the prior PET conforming system. The method can finish the process of the conforming system high-efficiently and fast by using a piece of FPGA and can lead the system not to be inducted into the dead time while the high system sensitivity is obtained.