749 results about "Gate array" patented technology

The embodiment of the invention provides a broadband signal dynamic generation method and system based on multiple clock sources, and the method comprises the steps: monitoring a target frequency in real time through a field programmable gate array, and automatically switching to a corresponding target clock source based on a frequency band to which the target frequency belongs; correcting the phase difference corresponding to the new and old target clock sources through a phase compensation register when the target clock sources are switched, and loading a compensation value to a phase offset register of a direct digital frequency synthesis chip; a fundamental waveform of a broadband signal is generated based on a direct digital frequency synthesis chip, multiple harmonic components are superposed through a fractional accumulation method, and each harmonic amplitude is independently controlled through a look-up table method; an output signal of the power amplifier is collected through the analog-to-digital converter, error information of the actually measured waveform and the theoretical waveform is extracted, the phase offset register and the harmonic amplitude look-up table coefficient are dynamically corrected, and a target broadband signal is output. Unification of broadband coverage, high resolution and quick response is realized.

The invention provides a chip aging test system and method based on a field programmable gate array, and the system is characterized in that a drive control panel comprises a processor module, a communication interface module, and an external connector module; the external connector module comprises a first connector and a second connector; the processor module is used for receiving a test instruction sent by the upper computer through the communication interface module, generating a test signal and a control signal, and receiving a test result acquisition instruction sent by the upper computer after the communication interface module sends response information to the upper computer; the first end of the processor module is also used for sending the interrupt information to an upper computer through the communication interface module and displaying the interrupt information; and the third end of the processor module is connected with the second connector and is used for outputting the control signal to the test board. Test signals are output to multiple groups of tested chips of the test board in parallel through the first connector, the second connector controls the test sequence of the to-be-tested chips on the test board, and hundreds of chips are driven by a single drive board and used for aging test.

The invention discloses a wind-feeling-free radiation type five-constant air conditioner multi-target self-adaptive optimization method and system, and belongs to the technical field of digital monitoring. A personnel density heat and humidity load model and a building heat and humidity response RC network model are established, long and short term memory neural network training is combined, and a humidity load increment rate and a temperature rising rate prediction value are output; a non-dominated sorting genetic algorithm is utilized to dynamically adjust temperature and humidity control weights, an optimal parameter combination is generated, and LSTM parameters are optimized through incremental learning; edge computing nodes are deployed, and LSTM reasoning and NSGA-II non-dominated sorting operation is accelerated by means of a tensor reasoning engine and a field-programmable gate array; a double-time scale strategy is adopted, a quick response layer directly outputs a control quantity during load fluctuation, a deep optimization layer is started to synchronously optimize energy efficiency and comfort after stabilization, energy efficiency is saved, real-time response in a personnel sudden increase scene is realized, algorithm time is compressed to match personnel sudden increase time scale, and energy efficiency and comfort are synchronously improved.

The invention relates to the technical field of fuel cell monitoring and health management, and discloses an intelligent cooperative high-power proton exchange membrane fuel cell life prediction and fault diagnosis method and system, and the method comprises the following steps: S1, collecting multi-dimensional data of a stack key region in real time through a distributed sensing array; s2, removing noise and abnormal values of the collected data, and carrying out feature extraction; s3, constructing a dual-model collaborative prediction framework; s4, inputting the real-time features into the double models; s5, generating a maintenance strategy and early warning; according to the invention, special hardware accelerators such as a graphic processing unit or a field-programmable gate array are integrated on the edge computing module, so that the processing speed and efficiency of high-frequency and multi-source sensor data at a local end are remarkably improved; a distributed computing framework is adopted in a cloud analysis module to process mass feature data transmitted by an edge end, so that the capability and scale of the system for performing deep analysis on the health state of the fuel cell, accurately predicting the remaining service life and quickly tracing the fault are enhanced.

The invention discloses a data acquisition system and method in a CT (Computed Tomography) system, the system comprises a control end and an acquisition end, a first FPGA (Field Programmable Gate Array) module and a second FPGA module are respectively arranged in the control end and the acquisition end, a forward error correction coding module and a data transmitting module are arranged in the first field programmable gate array FPGA module, and a forward error correction decoding module and a data receiving module are arranged in the second field programmable gate array FPGA module; wherein when the control end sends control command data to the acquisition end, the forward error correction encoding module encodes the control command data and then sends the control command data to the forward error correction decoding module through the data sending module, so that the second forward error correction module recovers the encoded control command data; and the data receiving module receives the recovered data. A data forward error correction technology is added to serial communication, so that a receiver does not receive wrong data, and the defects of related technologies are overcome.

The invention discloses a system-on-chip, a system-on-chip configuration method and electronic equipment. The system on chip comprises a multi-core RISC-V processor and a field programmable gate array (FPGA), the FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after the initial configuration is completed by power-on starting; the multi-core RISC-V processor is configured to start a bootloader according to the initial configuration completion signal, and the bootloader is configured to start the bootloader according to the initial configuration completion signal; under the condition that an FPGA reconfiguration event occurs, a reconfiguration request signal is sent to the FPGA; the FPGA is further configured to set a storage position to obtain new configuration data, and after reconfiguration is completed, a reconfiguration completion signal is sent to the multi-core RISC-V processor; the multi-core RISC-V processor is further configured to execute system interface reinitialization and / or configuration parameter updating according to the reconfiguration completion signal. According to the scheme of the invention, a bidirectional configuration mechanism between the FPGA and the RISC-V is realized based on the standardized interaction signal, and the dynamic configuration / upgrading requirements of system functions are fully met.

The invention provides a bottom dead center position self-adjustment control method and system for servo stamping equipment, and the method employs a double-speed cooperation architecture of a field programmable gate array (FPGA) and a micro control unit (MCU): the FPGA carries out the high-frequency collection and preprocessing of position, direction, current, temperature, vibration and acceleration signals in a bottom dead center core region, and transmits the signals to the MCU at a low time delay; the MCU executes bottom dead center reference calibration and transmission chain back clearance recognition, constructs a comprehensive error in combination with Kalman filtering state estimation, solves the compensation amount in a rolling mode based on model predictive control (MPC), and writes the compensation amount into a servo driver fine adjustment motion curve through a bus in cooperation with dynamic dead zone control, so that the position of a bottom dead center is stably converged for a long time, and the stamping precision and consistency are improved.

An OpenCL-defined scalable runtime-flexible programmable accelerator architecture for accelerating convolutional neural network (CNN) inference in cloud / edge computing is provided, referred to herein as Systolic-CNN. Existing OpenCL-defined programmable accelerators (e.g., field-programmable gate array (FPGA)-based accelerators) for CNN inference are insufficient due to limited flexibility for supporting multiple CNN models at runtime and poor scalability resulting in underutilized accelerator resources and limited computational parallelism. Systolic-CNN adopts a highly pipelined and paralleled one-dimensional (1-D) systolic array architecture, which efficiently explores both spatial and temporal parallelism for accelerating CNN inference on programmable accelerators (e.g., FPGAs). Systolic-CNN is highly scalable and parameterized, and can be easily adapted by users to efficiently utilize the coarse-grained computation resources for a given programmable accelerator. In addition, Systolic-CNN is runtime-flexible and can be time-shared to accelerate a variety of CNN models at runtime without the need to recompile the programmable accelerator kernel hardware or reprogram the programmable accelerator.

A chip package includes a ball-grid-array (BGA) substrate; a first metal bump at a bottom of the ball-grid-array (BGA) substrate, wherein the first metal bump comprises tin; a field programmable chip package over and coupling to the ball-grid-array (BGA) substrate, wherein the field programmable chip package comprises a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip therein and a second metal bump at a bottom of the field programmable chip package and bonded to a top of the ball-grid-array (BGA) substrate; and a memory chip package under and coupling to the ball-grid-array (BGA) substrate, wherein the memory chip package comprises a first non-volatile memory (NVM) integrated-circuit (IC) chip therein and a third metal bump at a top of the memory chip package and bonded to the bottom of the ball-grid-array (BGA) substrate.

The invention relates to the technical field of geographic information systems, in particular to a GIS buffer zone parameter inference method based on deep learning, and the method comprises the following steps: obtaining a natural language instruction input by a user; analyzing the natural language instruction to extract a geographic entity keyword and a fuzzy description word; based on the fuzzy description word, determining an initial distance parameter through a pre-trained language-space mapping model; querying a spatial database based on the geographic entity keyword to obtain geographic entity attributes; according to the geographic entity attribute, correcting the initial distance parameter to obtain a corrected distance parameter; a field programmable gate array (FPGA) is used for carrying out parallel calculation on the spatial relation matrix to generate an optimized buffer area; and outputting the optimized buffer area. According to the method, the FPGA is introduced to carry out parallel calculation of the spatial relation matrix, so that the data processing speed and the energy efficiency ratio are remarkably improved, and the real-time generation of the buffer area is realized.

The invention relates to the technical field of field programmable gate array physical optimization, and discloses a field programmable gate array multi-resource division method, device and equipment, the method comprises the following steps: generating a hypergraph comprising vertexes and hyperedges based on a netlist, the hypergraph comprising one or more types of resources; carrying out first partition division on the hypergraph, and carrying out multi-level vertex combination; partitioning the hypergraph of the maximum merging hierarchy, dividing vertexes in the maximum merging hierarchy to each partition, and carrying out the following processing on the hypergraph of each hierarchy from the maximum merging hierarchy to the minimum merging hierarchy: moving a first vertex between the partitions in the target merging hierarchy, and meeting the multi-resource constraint of the partitions in the moving process; splitting the vertexes in the target merging hierarchy into the vertexes of the previous hierarchy of the target merging hierarchy; until a first hypergraph is obtained; moving a first vertex in the first hypergraph to obtain a first partitioning result; and carrying out partition division again until the position of each functional module is determined.

Systems and methods for direct-to-RF (radio frequency) software-defined radio implementation of an active load-pull system are provided. A system may include a controller, a primary field-programmable gate array (FPGA) to control and collect waveform data from vector signal analyzers (VSAs), each comprising an analog-to-digital converter (ADC) connected to an ADC signal-conditioning circuit to directly capture RF measurements of an input signal at an RF fundamental frequency of test and harmonics, each ADC signal-conditioning circuit altering a signal amplitude and isolating a wanted RF frequency of measurement at either the RF fundamental frequency of test or a harmonic to be received by its ADC, first and second couplers generating each input signal by extracting forward and reverse traveling waves at RF from input and output ports of a device under test (DUT), the VSAs capturing the input signals directly at the RF fundamental frequency of test or a harmonic.

A system and method for deploying machine learning models with consistent fixed-point arithmetic processing. A computing device in a vehicle receives a trained machine learning model that was trained using training images processed with fixed-point arithmetic operations. The computing device receives images from a camera and processes the received images using fixed-point arithmetic operations that are consistent with those used during training. The machine learning model is executed using the processed images to detect objects such as vehicles, pedestrians, persons on bikes, stop lights, or stop signs. The computing device may comprise specialized hardware including a graphics processing unit (GPU), digital signal processing hardware decoder, or single-purpose hardware decoder such as an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The system may generate alerts or determine vehicle operation changes based on detected objects, and may operate in surveillance mode when the vehicle is parked.

The invention discloses a switch cabinet anti-explosion multi-parameter rapid identification and alarm method, and relates to the technical field of power equipment safety, and the method comprises the steps: obtaining a known switch cabinet historical fault record, analyzing the attribute preference and occurrence rule of different faults, constructing a multi-modal time sequence fault diagnosis model, and generating a fault knowledge base; operating parameters are monitored in real time, a field programmable gate array is used for solidifying primary judgment logic, and if the current change rate and the arc light signal intensity exceed preset threshold values at the microsecond level at the same time, a primary fault trigger signal is generated; the edge intelligent calculation unit automatically extracts the original data of the multi-source heterogeneous sensor in a set time window before and after the triggering moment, and substitutes the original data into the multi-modal time sequence fault diagnosis model to obtain a diagnosis result and a risk level of a known switch cabinet fault; and in combination with the multi-modal time sequence fault diagnosis model, executing a layered response mechanism. The beneficial effect of the invention is that the fault loss is reduced.

The invention discloses a market information data management method and device and a storage medium, and relates to the technical field of data processing, and the method comprises the steps: receiving a market information data flow transmitted by a market information source based on a market information convergence layer, and obtaining market information data meeting the processing requirements; inputting the market information data meeting the processing requirements into a field programmable gate array; and performing multi-source data fusion processing on the market information data through the field programmable gate array to generate a unified convergence market information flow. The technical effect of improving the richness of the market data is achieved.

The invention relates to the field of image processing, in particular to an infrared image bilateral filtering method based on field programmable gate array (FPGA) optimization, which comprises the following steps: acquiring data through a hierarchical architecture of'on-chip BRAM cache + distributed register cache ', intercepting pixels in combination with a sliding window, calculating a spatial weight by using an LUT look-up table, and logically calculating a gray scale weight in real time. And carrying out weighted summation and normalization output. According to the method, the processing delay of the infrared image with the resolution of 1024 * 1024 is reduced to be less than 50ms, the frame rate is increased to be more than 60fps, and the method is suitable for a real-time target recognition scene. Through the combination of the optimized bilateral filtering algorithm and the efficient hardware architecture, the processing delay is remarkably reduced, the real-time processing of the high-resolution infrared image is realized, and the real-time performance is remarkably improved.

The invention discloses a chip prototype verification method and device, a medium and a product, relates to the technical field of chip design, is applied to a hardware debugger of a simulation test tool, and comprises the following steps: analyzing a capability maturity model script; the analyzed script and the execution mode switching condition are sent to a central processing unit of the field programmable gate array, so that the central processing unit determines a current execution mode according to the analyzed script and the execution mode switching condition; test case codes of different execution modes in the capability maturity model script are stored in different data areas of a preset memory pool respectively, so that a central processing unit obtains the corresponding test case codes based on the current execution mode, verification data are generated according to the test case codes and peripheral equipment of a pre-configured chip, and the verification data are stored in the preset memory pool; returning the verification data to a hardware debugger of the simulation test tool; and generating a prototype verification report based on the verification data and the expected data to complete chip prototype verification. And chip prototype verification can be realized by dynamically switching verification modes.

A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

The invention discloses a domestic heterogeneous chip dynamic power consumption cooperative scheduling method oriented to a vehicle-mounted environment, and aims to solve the problem of system energy efficiency optimization caused by strict limitation of power supply and heat dissipation resources, dynamic mixing of calculation tasks and unique power consumption characteristics of domestic chips in the vehicle-mounted environment. The method is based on a vehicle-mounted heterogeneous computing platform comprising a domestic central processing unit, a field programmable gate array and a memory, and is realized through a closed-loop scheduling process executed by the central processing unit. According to the method, global, dynamic and collaborative power consumption management of domestic heterogeneous chip resources is realized, and the overall energy efficiency and the operation reliability of the system are remarkably improved on the premise of ensuring the real-time performance and the performance of a vehicle-mounted task.

A telecommunications switch-type platform positioned between a private-branch exchange and a data network dynamically hosts artificial-intelligence agents that interpret, transcribe, translate and transliterate live call traffic while the session is in progress. Machine-readable instructions stored in local memory instantiate, migrate and terminate the agents on demand across dedicated processing resources such as field-programmable gate arrays, application-specific integrated circuits or system-on-chip devices, thereby maintaining end-to-end latency below 250 milliseconds. An integrated call-audio recorder captures bidirectional media streams for secure archiving without interrupting service. The platform exposes a network interface that passes both signalling and media traffic, enabling seamless deployment inside call-centre or enterprise environments and compatibility with softswitch architectures conforming to class-4 Computational Interpretation of Communication using Artificial Intelligence standards. The same functional stack is deliverable as a computer-implemented method and as a non-transitory machine-readable medium storing the instructions executed by the processing resources.

An artificial intelligence-based business management system for real-time decision optimization, consisting of: a data acquisition unit configured to ingest structured, semi-structured and unstructured data streams from enterprise resource planning (ERP) systems, customer relationship management (CRM) platforms, Internet of Things (IoT) devices, external market feeds and financial transaction systems, encrypting, timestamping and verifying the data prior to further processing; a graph processing unit that is communicatively connected to the said acquisition layer, wherein the unit is configured to encode heterogeneous data into dynamic graph structures comprising nodes representing business entities and edges representing transaction or relationship dependencies, wherein the unit is further configured to perform deduplication, metadata tagging and real-time data synchronization; a decision optimization unit operationally linked to the graph processing unit, wherein the decision optimization unit includes modules for reinforcement learning, modules for Bayesian optimization and multi-objective solvers configured to simulate multiple alternative decision paths and select an optimal path based on performance indicators such as cost efficiency, resource utilization, customer satisfaction and risk minimization; a real-time inference control unit with specialized hardware cores, including at least one graphics processing unit (GPU), a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC), wherein the accelerator performs inference tasks of the decision optimization unit with a latency in the millisecond range; a diagnostic processing unit configured to generate causal diagrams, feature mapping maps, and interpretable result summaries according to the optimization outputs; and a control interface unit configured to transmit optimized decisions to process controls within the enterprise, robot actuators, planning systems or interactive dashboards, with the interface supporting bidirectional communication for higher-level interventions, error feedback and triggers for re-optimization.

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

The invention relates to the technical field of electronic design automation, and provides an intelligent three-dimensional design optimization system for an ink-jet circuit board. The system comprises a field programmable gate array core control module, a microcontroller co-processing module, a multi-channel stepping motor driving module, a multi-mode communication interface module, a sensor feedback and state monitoring module and a three-dimensional layout optimization structure. High-precision real-time control and management are realized through heterogeneous cooperation of the programmable gate array core control module and the microcontroller cooperative processing module; in cooperation with multi-channel stepping motor driving, multi-mode communication and sensor feedback, a three-dimensional layout optimization structure is used for carrying out system space optimization on components, signals and a power supply, and heat dissipation, electromagnetic compatibility and signal integrity are remarkably improved. According to the system, the control precision and the real-time monitoring and remote management efficiency are effectively improved, the response speed, the operation stability and the maintainability of the system are enhanced, and high integration level and high reliability are achieved.

The invention provides a multichannel platinum thermal resistor program control simulation card and method, the multichannel platinum thermal resistor program control simulation card comprises a resistor gating array, a relay driving array, a microcontroller module, a communication interface module and a power supply module, and the method comprises the following steps: inputting a temperature value in an upper computer; the upper computer carries out temperature-resistance value conversion; the upper computer sets resistance precision; the upper computer packages the resistance value data into a data packet according to a communication protocol, and the data packet is sent to a microcontroller of the lower computer after CRC verification; the microcontroller receives the data packet, analyzes the data packet according to a communication protocol after performing CRC (Cyclic Redundancy Check), and obtains resistance value data; the microcontroller performs'resistance value-I / O state 'conversion; the microcontroller sets an I / O state. The method has the beneficial effects that the integration and automation levels of test equipment are remarkably improved, and the test failure risk caused by the problems of instrument consistency and the like is reduced.

The invention relates to the technical field of electric connector weak light assembly vibration compensation alignment methods, particularly discloses an electric connector weak light assembly vibration compensation alignment method, and aims to solve the problems of low electric connector assembly positioning precision and high pseudo soldering rate caused by vibration in a weak light environment. The method comprises the following steps: monitoring the thermal radiation change of a vibration source in real time through an infrared thermal imaging sensor, and pre-judging a vibration acceleration vector in combination with a lightweight long-short-term memory neural network; synchronously triggering dual polarization angle imaging to respectively capture a housing reference mark and an enhanced terminal metal feature; the vibration data and the polarization image flow are fused in the field programmable gate array, a self-adaptive optical flow algorithm is adopted to resolve the displacement compensation amount, and a piezoelectric ceramic actuator is driven to carry out submicron order reverse displacement compensation; when the compensation amount exceeds a threshold value, a low-delay correction instruction is sent to the robot through an Ethernet control automation technology bus, and the steady-state error is ensured to be smaller than 0.3 micrometer by combining a strain gauge fine tuning feedback loop. According to the technical scheme, the assembling precision, efficiency and production line adaptability are remarkably improved.

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.

A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

A system for integrated data provenance and reconciliation across heterogeneous financial systems, the system includes: a data ingestion module implemented as a hardware interface and configured with high-throughput adapters for structured and unstructured data ingestion from multiple heterogeneous financial subsystems, including bank ledgers, securities trading platforms, risk management databases, and regulatory reporting systems; a schema harmonization processing unit consisting of a dedicated FPGA (Field Programmable Gate Array) structure configured to perform real-time schema alignment, metadata normalization, and semantic mapping across different data models; a lineage tracking processor array implemented on application-specific integrated circuits (ASICs) and configured to encode dataflow transitions into a graph-encoded structure in which each node represents a transformation and each edge represents a dependency; a reconciliation computation cluster unit embodied as a set of graphics processing units (GPUs) configured to execute parallelized reconciliation techniques, anomaly detection routines, and balance verification processes between transformed financial records and reference records; a cryptographic verification unit comprising secure key storage hardware, quantum-resistant encryption modules, and tamper-resistant enclaves configured to generate, anchor, and verify cryptographic signatures for provenance and reconciliation events; a secure storage subsystem configured in a WORM (write-once, read-many) configuration with hardware-based integrity locks for storing immutable provenance and reconciliation logs; a controller with a dedicated visualization processor configured to generate interactive dashboards and drill-down analyses of lineage charts and voting results; and a modular chassis structure consisting of a high-speed backplane interconnect, secure power distribution modules, and tamper-evident enclosures, enabling the system to achieve real-time scalability, hardware-level security, and auditability of financial data flows across heterogeneous infrastructures.

Aspects of the present disclosure include methods for identifying measurement uncertainty associated with light detected from a sample. Methods according to certain embodiments include introducing a sample into a flow cytometer, flowing the introduced sample in a flow stream, irradiating the sample in the flow stream with a light source, detecting light from particles in the sample flowing in the flow stream and, identifying measurement uncertainty associated with the detected light. In some embodiments, measurement uncertainty is identified corresponding to individual particles in the sample. In certain embodiments, measurement uncertainty is identified for individual parameters of detected light for particles in the sample. Methods according to some embodiments further comprise generating a quality score for each particle based on the measurement uncertainty for each particle. Systems, integrated circuit devices (e.g., a field programmable gate array) and non-transitory computer readable storage mediums for practicing the subject methods are also provided.

The invention belongs to the technical field of magnetic field detection, and discloses a cross-shaped variable baseline magnetic flux gate array and method for measuring a three-order magnetic gradient tensor. The cross-shaped variable baseline magnetic flux gate array comprises a cross-shaped array rack, each supporting arm is provided with a sliding groove with the length of 1, and a sensor is installed on each sliding groove in a clamped mode. A sensor is mounted at the central point of the cross array rack; the baseline distances d between the adjacent sensors are equal, and the sensors slide in the corresponding sliding grooves. According to the adjusting method, the baseline distance is adjusted through the sliding groove. According to the rotation correction method, the surrounding sensors are corrected through the middle sensor, the measurement precision is improved, the zero-order magnetic gradient tensor and the first-order magnetic gradient tensor at the position of each sensor and the second-order magnetic gradient tensor and the third-order magnetic gradient tensor at the position of the center sensor can be measured at the same time, rich target magnetic field information is obtained, and the measurement accuracy is improved. The engineering practical value is realized.