991 results about "Gate array" patented technology

Aspects of the present disclosure include methods for spectrally resolving light from fluorophores in a sample. Methods according to certain embodiments include detecting light with a light detection system from a sample having a plurality of fluorophores having overlapping fluorescence spectra and spectrally resolving light from each fluorophore in the sample with a generalized least squares algorithm. In some embodiments, methods include estimating the abundance of one or more of the fluorophores in the sample, such as on a particle. In certain instances, methods include identifying the particle in the sample based on the abundance of each fluorophore and sorting the particle. Methods according to some embodiments includes spectrally resolving the light from each fluorophore by calculating a spectral unmixing matrix for the fluorescence spectra of each fluorophore. Systems and integrated circuit devices (e.g., a field programmable gate array) for practicing the subject methods are also provided.

The invention relates to the field of intelligent operation and maintenance of a high-speed railway overhead line system, provides a machine learning-based optimization method and system for dropper arrangement of the high-speed railway overhead line system, and aims to solve the problems of insufficient pantograph-catenary coupling stability and relatively low abrasion uniformity of the overhead line system. The method comprises the steps that contact force space distribution characteristics of a pantograph and a contact net are collected, and contact force balance constraint conditions are generated; constructing a line parameter compensation mechanism by combining the track ultrahigh value, the vertical curve curvature and the elevation data of the suspension point acquired by the laser scanner, and outputting a compensation three-dimensional coordinate of the suspension point of the overhead line system; a programmable gate array is adopted to implement parallel acceleration on neural network weight calculation and space coordinate transformation, contact force constraint and compensation coordinates are iteratively processed, and dropper arrangement parameters are generated; based on the segmented tension value and the node offset compensation value, driving equipment to finish accurate adjustment and positioning installation of the dropper. According to the technical scheme provided by the invention, the pantograph-catenary coupling stability and the wear uniformity of the catenary are improved.

The invention discloses an intelligent optimization driving electromagnetic information metasurface multi-dimensional dynamic regulation and control system, solves the problem that the function solidification of an existing metasurface is difficult to dynamically adjust, and belongs to the crossing field of electromagnetic metamaterials and intelligent control technologies. The method comprises the steps that a sensor network collects environment multi-dimensional information of a programmable metasurface unit in real time; the controller processes the environment multi-dimensional information to obtain a multi-dimensional sensing result; the multi-dimensional interaction layer inputs design parameters, the intelligent decision-making layer combines the design parameters and a multi-dimensional perception result to construct a target joint optimization model, reverse design is carried out on the super-surface array coding sequence, and a display array coding pattern and a three-dimensional radiation pattern / two-dimensional radiation pattern are obtained according to the designed super-surface array coding sequence; displaying on the multi-dimensional interaction layer; and the controller performs real-time electromagnetic response reconstruction and 1-bit or 2-bit phase modulation on the programmable metasurface unit through the field programmable gate array according to the designed metasurface array coding sequence.

The invention relates to a software and hardware SOC (System On Chip) verification system and method based on EDA (Electronic Design Automation) and an FPGA (Field Programmable Gate Array), and belongs to the field of SOC chip verification. The software part comprises an SOC UVM TESTBENCH SOC verification platform, a disk network disk and a T CP protocol client side; and the hardware part mainly comprises a TCP (Transmission Control Protocol) SERVER protocol server side and a SOCTOP (System On Chip Over Programmable). The method is characterized in that advantages of EDA verification and FPGA prototype verification are combined, cross-platform accelerated verification of the SOC chip is realized, the verification period of the chip is shortened, and the verification quality of the chip is improved.

The invention discloses an automatic machine learning collaborative optimization method based on hardware perception. The method is used for design of an integrated learning field programmable gate array accelerator in edge artificial intelligence. The method aims at solving the balance challenge between algorithm performance and hardware resource consumption. The method comprises the following steps: defining a joint optimization space containing algorithm hyper-parameters and FPGA hardware configuration parameters; a collaborative optimization objective function is established, the function is determined by algorithm performance indexes and predicted FPGA hardware resource occupancy, and resource prediction quantifies hardware influence according to algorithm hyper-parameters; and searching according to the objective function in the joint optimization space by utilizing an AutoML optimization algorithm so as to identify the optimal configuration of the balance performance and resources. According to the method, the problems of low resource efficiency and high development cost caused by separate optimization of an algorithm and hardware in the prior art are effectively solved, balanced design is realized, automation is enhanced, and complexity is reduced.

The embodiment of the invention provides a broadband signal dynamic generation method and system based on multiple clock sources, and the method comprises the steps: monitoring a target frequency in real time through a field programmable gate array, and automatically switching to a corresponding target clock source based on a frequency band to which the target frequency belongs; correcting the phase difference corresponding to the new and old target clock sources through a phase compensation register when the target clock sources are switched, and loading a compensation value to a phase offset register of a direct digital frequency synthesis chip; a fundamental waveform of a broadband signal is generated based on a direct digital frequency synthesis chip, multiple harmonic components are superposed through a fractional accumulation method, and each harmonic amplitude is independently controlled through a look-up table method; an output signal of the power amplifier is collected through the analog-to-digital converter, error information of the actually measured waveform and the theoretical waveform is extracted, the phase offset register and the harmonic amplitude look-up table coefficient are dynamically corrected, and a target broadband signal is output. Unification of broadband coverage, high resolution and quick response is realized.

A system, method and apparatus for executing a bioinformatics analysis on genetic sequence data is provided. Particularly, a genomics analysis platform for executing a sequence analysis pipeline is provided. The genomics analysis platform includes one or more of a first integrated circuit, where each first integrated circuit forms a central processing unit (CPU) that is responsive to one or more software algorithms that are configured to instruct the CPU to perform a first set of genomic processing steps of the sequence analysis pipeline. Additionally, a second integrated circuit is also provided, where each second integrated circuit forming a field programmable gate array (FPGA), the FPGA being configured by firmware to arrange a set of hardwired digital logic circuits that are interconnected by a plurality of physical interconnects to perform a second set of genomic processing steps of the sequence analysis pipeline, the set of hardwired digital logic circuits of each FPGA being arranged as a set of processing engines to perform the second set of genomic processing steps. A shared memory is also provided.

The invention provides a chip aging test system and method based on a field programmable gate array, and the system is characterized in that a drive control panel comprises a processor module, a communication interface module, and an external connector module; the external connector module comprises a first connector and a second connector; the processor module is used for receiving a test instruction sent by the upper computer through the communication interface module, generating a test signal and a control signal, and receiving a test result acquisition instruction sent by the upper computer after the communication interface module sends response information to the upper computer; the first end of the processor module is also used for sending the interrupt information to an upper computer through the communication interface module and displaying the interrupt information; and the third end of the processor module is connected with the second connector and is used for outputting the control signal to the test board. Test signals are output to multiple groups of tested chips of the test board in parallel through the first connector, the second connector controls the test sequence of the to-be-tested chips on the test board, and hundreds of chips are driven by a single drive board and used for aging test.

The invention discloses a wind-feeling-free radiation type five-constant air conditioner multi-target self-adaptive optimization method and system, and belongs to the technical field of digital monitoring. A personnel density heat and humidity load model and a building heat and humidity response RC network model are established, long and short term memory neural network training is combined, and a humidity load increment rate and a temperature rising rate prediction value are output; a non-dominated sorting genetic algorithm is utilized to dynamically adjust temperature and humidity control weights, an optimal parameter combination is generated, and LSTM parameters are optimized through incremental learning; edge computing nodes are deployed, and LSTM reasoning and NSGA-II non-dominated sorting operation is accelerated by means of a tensor reasoning engine and a field-programmable gate array; a double-time scale strategy is adopted, a quick response layer directly outputs a control quantity during load fluctuation, a deep optimization layer is started to synchronously optimize energy efficiency and comfort after stabilization, energy efficiency is saved, real-time response in a personnel sudden increase scene is realized, algorithm time is compressed to match personnel sudden increase time scale, and energy efficiency and comfort are synchronously improved.

The invention relates to the technical field of fuel cell monitoring and health management, and discloses an intelligent cooperative high-power proton exchange membrane fuel cell life prediction and fault diagnosis method and system, and the method comprises the following steps: S1, collecting multi-dimensional data of a stack key region in real time through a distributed sensing array; s2, removing noise and abnormal values of the collected data, and carrying out feature extraction; s3, constructing a dual-model collaborative prediction framework; s4, inputting the real-time features into the double models; s5, generating a maintenance strategy and early warning; according to the invention, special hardware accelerators such as a graphic processing unit or a field-programmable gate array are integrated on the edge computing module, so that the processing speed and efficiency of high-frequency and multi-source sensor data at a local end are remarkably improved; a distributed computing framework is adopted in a cloud analysis module to process mass feature data transmitted by an edge end, so that the capability and scale of the system for performing deep analysis on the health state of the fuel cell, accurately predicting the remaining service life and quickly tracing the fault are enhanced.

The invention discloses a data acquisition system and method in a CT (Computed Tomography) system, the system comprises a control end and an acquisition end, a first FPGA (Field Programmable Gate Array) module and a second FPGA module are respectively arranged in the control end and the acquisition end, a forward error correction coding module and a data transmitting module are arranged in the first field programmable gate array FPGA module, and a forward error correction decoding module and a data receiving module are arranged in the second field programmable gate array FPGA module; wherein when the control end sends control command data to the acquisition end, the forward error correction encoding module encodes the control command data and then sends the control command data to the forward error correction decoding module through the data sending module, so that the second forward error correction module recovers the encoded control command data; and the data receiving module receives the recovered data. A data forward error correction technology is added to serial communication, so that a receiver does not receive wrong data, and the defects of related technologies are overcome.

An optical transceiver includes an electro-optic front end; a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) connected to the electro-optic front end; and one or more Field Programmable Gate Arrays (FPGAs) connected to the DAC and the ADC, wherein the one or more FPGAs are connected to one or more of a local memory and a remote storage for loading FPGA bit files, and wherein the one or more FPGAs are loaded with a forward error correction (FEC) encoding app and a FEC decoding app. The FEC encoding app and the FEC decoding app can be selected based on any of an optical application and a standard compliance requirement.

The invention provides an accelerator determination method based on a field-programmable gate array, an image processing method, equipment and a storage medium, which can be applied to the technical field of image compression. The accelerator determination method based on the field programmable gate array comprises the steps that a fusion factor list is determined according to the number of fusion units corresponding to a network model, the fusion factor list comprises a plurality of fusion factors, and the fusion factors represent the number of the fusion units needed for fusing the fusion units in the network model into a fusion structure; under the storage constraint and bandwidth constraint of the field programmable gate array, determining a target fusion factor from the plurality of fusion factors according to the image data block parameters and the fusion network parameter sets respectively corresponding to the plurality of fusion factors; and according to the target fusion factor and the fusion network parameter set corresponding to the target fusion factor, performing parameter mapping on the field programmable gate array to obtain an accelerator for realizing image compression.

The invention discloses a dual-path time delay difference PUF circuit, which comprises two time delay modules, two arbiters, a first exclusive-OR gate, n-1 time delay arbitration modules and an exclusive-OR gate array, each time delay module comprises n switch unit arrays, each switch unit array comprises m switch units, n is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Each time delay arbitration module comprises two arbiters and an exclusive-OR gate, the exclusive-OR gate array comprises n-1 exclusive-OR gates, each time delay module is divided into n switch unit arrays, and the two time delay modules are divided into n switch unit array combinations, inserting a time delay arbitration module between every two adjacent switch unit array combinations to extract an intermediate response, then performing XOR processing on the intermediate response through an XOR logic gate array to obtain a response, and then performing XOR processing on the response and responses output by two arbiters again through a first XOR gate to obtain a final response; the method has the advantages of high machine learning attack resistance and low hardware overhead.

A multi-channel analog-digital converter (ADC) subsystem for test device such as a spectrum analyzer may include multiple multi-channel ADCs to receive down-converted signals and convert the received signals to digital output signals, a field programmable gate array (FPGA) to select one or more ADCs based on a frequency, a bandwidth, and / or a signal type of each received signal and a characteristic of each ADC, and an ADC sample clock to provide a clock signal to the selected ADCs. Characteristics of the ADCs may include a resolution, a signal-to-noise-and-distortion ratio (SINAD), an effective number of bits (ENOB), a signal-to-noise ratio (SNR), a total harmonic distortion (THD), a total harmonic distortion plus noise (THD+N), and / or a spurious free dynamic range (SFDR).

A hardware apparatus for isolated virtual environments includes graphics processing unit comprising a first dedicated memory and a first plurality of processing cores, a central processing unit comprising a second dedicated memory and a second plurality of processing cores, a field programmable gate array comprising a third dedicated memory, a control and data bus assembly connecting the field programmable gate array, the central processing unit, and the graphics processing unit, and a hypervisor located on a non-volatile memory of the hardware apparatus, the hypervisor configured to create one or more virtual machines by isolating the graphics processing unit, the central processing unit and the field programmable gate array.

The invention discloses a system-on-chip, a system-on-chip configuration method and electronic equipment. The system on chip comprises a multi-core RISC-V processor and a field programmable gate array (FPGA), the FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after the initial configuration is completed by power-on starting; the multi-core RISC-V processor is configured to start a bootloader according to the initial configuration completion signal, and the bootloader is configured to start the bootloader according to the initial configuration completion signal; under the condition that an FPGA reconfiguration event occurs, a reconfiguration request signal is sent to the FPGA; the FPGA is further configured to set a storage position to obtain new configuration data, and after reconfiguration is completed, a reconfiguration completion signal is sent to the multi-core RISC-V processor; the multi-core RISC-V processor is further configured to execute system interface reinitialization and / or configuration parameter updating according to the reconfiguration completion signal. According to the scheme of the invention, a bidirectional configuration mechanism between the FPGA and the RISC-V is realized based on the standardized interaction signal, and the dynamic configuration / upgrading requirements of system functions are fully met.

The invention relates to the technical field of communication, and discloses a dual-mode communication unit relaying and signal amplifying device, which comprises a signal receiving module comprising an HRF wireless receiving channel and an HPLC power line coupling channel which are independently configured, the working frequency band of the HRF wireless receiving channel is 470-510MHz, the receiving sensitivity is not lower than-120dBm, and the working frequency band of the HPLC power line coupling channel is 470-510MHz; the HPLC coupling channel supports a frequency band of 0.7-12 MHz and has an impedance matching range of 20-200 omega, the two channels alternately scan input signals in a time division multiplexing mode, and the signal processing module is integrated with a digital signal processor and field programmable gate array cooperative processing architecture and is internally provided with a signal type identification circuit. According to the device for relaying and amplifying the signals of the dual-mode communication unit, the HRF signals and the HPLC signals are automatically distinguished through fast Fourier transform spectrum analysis, an HRF wireless receiving channel and an HPLC power line coupling channel are integrated, a repeater is installed in an area where HRF signal transmission is not good, the repeater can process the HRF signals and the HPLC signals at the same time, and the signal transmission efficiency is improved. And real-time receiving and efficient transmission of dual-mode signals are realized.

The invention discloses a hardware acceleration system and method based on a multi-core architecture and related equipment, and relates to the technical field of computers, the hardware acceleration system based on the multi-core architecture comprises a CPU and a field programmable gate array based on the multi-core architecture, the field programmable gate array based on the multi-core architecture comprises a plurality of multi-scalar calculation acceleration cores; the CPU splits a multi-scalar multiplication task into a plurality of multi-scalar multiplication subtasks, and sends the plurality of multi-scalar multiplication subtasks to the field programmable gate array based on the multi-core architecture; the field programmable gate array based on the multi-core architecture receives the plurality of multi-scalar multiplication subtasks, and respectively processes the corresponding split multi-scalar multiplication subtasks based on the plurality of multi-scalar calculation acceleration cores; according to the invention, the hardware resource utilization rate of the field programmable gate array is improved.

A non-transitory computer readable medium is provided comprising instructions that when executed on a processor load a software program into a software debugger for execution on an emulated processor representing a processor portion of a system on chip (SoC), load a hardware design into a hardware simulator representing a programmable gate array portion of the SoC, coordinate execution of software debugger and hardware simulator to simulate operation of the SoC, communicate data between the software debugger and the hardware simulator, and display computed results and current values.

The invention provides a bottom dead center position self-adjustment control method and system for servo stamping equipment, and the method employs a double-speed cooperation architecture of a field programmable gate array (FPGA) and a micro control unit (MCU): the FPGA carries out the high-frequency collection and preprocessing of position, direction, current, temperature, vibration and acceleration signals in a bottom dead center core region, and transmits the signals to the MCU at a low time delay; the MCU executes bottom dead center reference calibration and transmission chain back clearance recognition, constructs a comprehensive error in combination with Kalman filtering state estimation, solves the compensation amount in a rolling mode based on model predictive control (MPC), and writes the compensation amount into a servo driver fine adjustment motion curve through a bus in cooperation with dynamic dead zone control, so that the position of a bottom dead center is stably converged for a long time, and the stamping precision and consistency are improved.

An integrated circuit (IC) layer stack is disclosed that integrates bypass chiplets in the IC layer stack without requiring fabrication of through-silicon vias (TSV) in a digital device for signals and power to a memory stack located above the digital device. Not requiring adding TSVs to an existing design high-performance digital device significantly reduces and / or eliminates digital device modification costs and time to manufacture new products consisting of three-dimensional stacked memory and digital device organizations. The bypass chiplets may be passive with just through conductors in silicon, or active with logic circuits therein. Flexibility of placement of the bypass chiplets in the IC layer stack in combination with an active interposer provides for many possible configurations of IC layer stacks. The digital device may be a microcontroller, a microprocessor, a PLA, an ASIC, a DSP, a GPU, a FPGA, neural processing unit, tensor processing unit, or any combination thereof.

The invention discloses an encrypted file processing method for heterogeneous computing, a program product and a heterogeneous computing system, and belongs to the technical field of computers. The heterogeneous computing encrypted file processing method comprises the steps of caching to-be-processed data to a memory cache region in a transparent file system under the condition that write operation is received; when it is detected that an operating system triggers a write-back process, calling a field programmable gate array to perform encryption operation on the to-be-processed data in the memory cache region; and writing the encrypted data to be processed into disk storage equipment. According to the encrypted file processing method for heterogeneous computing, efficient write-back operation on the encrypted file is achieved, the problems that resources are occupied inefficiently, system performance is poor, data processing efficiency is low and the like due to frequent hardware interaction during heterogeneous computing encryption operation are solved, and the response speed and the overall performance of the system are improved.

An OpenCL-defined scalable runtime-flexible programmable accelerator architecture for accelerating convolutional neural network (CNN) inference in cloud / edge computing is provided, referred to herein as Systolic-CNN. Existing OpenCL-defined programmable accelerators (e.g., field-programmable gate array (FPGA)-based accelerators) for CNN inference are insufficient due to limited flexibility for supporting multiple CNN models at runtime and poor scalability resulting in underutilized accelerator resources and limited computational parallelism. Systolic-CNN adopts a highly pipelined and paralleled one-dimensional (1-D) systolic array architecture, which efficiently explores both spatial and temporal parallelism for accelerating CNN inference on programmable accelerators (e.g., FPGAs). Systolic-CNN is highly scalable and parameterized, and can be easily adapted by users to efficiently utilize the coarse-grained computation resources for a given programmable accelerator. In addition, Systolic-CNN is runtime-flexible and can be time-shared to accelerate a variety of CNN models at runtime without the need to recompile the programmable accelerator kernel hardware or reprogram the programmable accelerator.

Extensometer (10) for measuring strain / stress on a test specimen (200) in a material testing device (190), comprising: - an imaging device (16) for producing an image of a test sample (200) which is subjected to a stress-inducing load; - a calculating device (30, 22, 24) for receiving the image of a test sample (200), for determining the movement of targets (202) on a test sample (200) and for determining the strain / stress from the determined movement of the targets (202); and - an output device (400) for outputting the specified strain / stress in real time, characterized by that the imaging device (16) and the calculating device (22, 24) are located on a single printed circuit board (15), wherein the computing device (30, 22, 24) comprises a field-programmable gate array (22) and a microprocessor (24), and wherein the entire data path from image data input to output takes place in hardware, and that the extensometer (10) has an input for receiving a trigger or synchronization signal to initiate operation or time stamping and, upon receipt of the signal, to generate a time-stamped image of the test sample (200), and that the output device (400) is designed to output the specified strain / stress along with the image with the timestamp.

A receiver includes an antenna block configured to transduce impinging electromagnetic signals into electrical signals; a signal conditioning block configured to condition electrical signals received from the antenna block; and a down-converter block configured to down-convert conditioned electrical signals received from the signal conditioning block. The down-converter block comprises a plurality of signal channels. The receiver further includes a plurality of analog-to-digital converters (ADCs) respectively connected to the signal channels of the down-converter block; and a field-programmable gate array (FPGA). The FPGA is configured to program the down-converter block by selecting a set of mixer frequencies and a set of bandwidths designed to remove interference signals in each signal channel. The selections are calculated to mitigate reductions in dynamic range in the ADCs due to interference. The FPGA is further configured to process digital signals received from the ADCs after the down-converter block has removed the interference signals.

A field-programmable-gate-array (FPGA) IC chip includes multiple first non-volatile memory cells in the FPGA IC chip, wherein the first non-volatile memory cells are configured to save multiple resulting values for a look-up table (LUT) of a programmable logic block of the FPGA IC chip, wherein the programmable logic block is configured to select, in accordance with its inputs, one from the resulting values into its output; and multiple second non-volatile memory cells in the FPGA IC chip, wherein the second non-volatile memory cells are configured to save multiple programming codes configured to control a switch of the FPGA IC chip.

The invention discloses a miniature multi-ion sensing system based on a non-gate array and a preparation method thereof, and belongs to the technical field of electrochemical sensing, and the miniature multi-ion sensing system comprises a multi-ion sensing unit and a molybdenum disulfide non-gate array; the multi-ion sensitive unit comprises a metal electrode array, an ion sensitive film array and a liquid storage tank, multiple ions are detected through the ion sensitive film array at the same time and converted into electric signals, and the electric signals are transmitted to the molybdenum disulfide non-gate array through the metal electrode array; the molybdenum disulfide NOT gate array comprises a plurality of molybdenum disulfide NOT gates, and each molybdenum disulfide NOT gate comprises a metal electrode layer, a molybdenum disulfide layer, a NOT gate input end and a NOT gate output end, so that two field effect transistors are formed, received electric signals are amplified, the Nernst limit is broken through a NOT gate structure, and tiny changes of ion concentration are accurately detected. The sensitivity is higher; molybdenum disulfide is used as a channel material of the NOT gate, so that the size and power consumption of the NOT gate are effectively reduced, the integration level of the system is improved, and the service life of the system is prolonged.

A chip package includes a ball-grid-array (BGA) substrate; a first metal bump at a bottom of the ball-grid-array (BGA) substrate, wherein the first metal bump comprises tin; a field programmable chip package over and coupling to the ball-grid-array (BGA) substrate, wherein the field programmable chip package comprises a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip therein and a second metal bump at a bottom of the field programmable chip package and bonded to a top of the ball-grid-array (BGA) substrate; and a memory chip package under and coupling to the ball-grid-array (BGA) substrate, wherein the memory chip package comprises a first non-volatile memory (NVM) integrated-circuit (IC) chip therein and a third metal bump at a top of the memory chip package and bonded to the bottom of the ball-grid-array (BGA) substrate.

There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y≤1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0≤x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).