432 results about "Gate array" patented technology

The invention discloses a system-on-chip, a system-on-chip configuration method and electronic equipment. The system on chip comprises a multi-core RISC-V processor and a field programmable gate array (FPGA), the FPGA is configured to send an initial configuration completion signal to the multi-core RISC-V processor after the initial configuration is completed by power-on starting; the multi-core RISC-V processor is configured to start a bootloader according to the initial configuration completion signal, and the bootloader is configured to start the bootloader according to the initial configuration completion signal; under the condition that an FPGA reconfiguration event occurs, a reconfiguration request signal is sent to the FPGA; the FPGA is further configured to set a storage position to obtain new configuration data, and after reconfiguration is completed, a reconfiguration completion signal is sent to the multi-core RISC-V processor; the multi-core RISC-V processor is further configured to execute system interface reinitialization and / or configuration parameter updating according to the reconfiguration completion signal. According to the scheme of the invention, a bidirectional configuration mechanism between the FPGA and the RISC-V is realized based on the standardized interaction signal, and the dynamic configuration / upgrading requirements of system functions are fully met.

The invention provides a bottom dead center position self-adjustment control method and system for servo stamping equipment, and the method employs a double-speed cooperation architecture of a field programmable gate array (FPGA) and a micro control unit (MCU): the FPGA carries out the high-frequency collection and preprocessing of position, direction, current, temperature, vibration and acceleration signals in a bottom dead center core region, and transmits the signals to the MCU at a low time delay; the MCU executes bottom dead center reference calibration and transmission chain back clearance recognition, constructs a comprehensive error in combination with Kalman filtering state estimation, solves the compensation amount in a rolling mode based on model predictive control (MPC), and writes the compensation amount into a servo driver fine adjustment motion curve through a bus in cooperation with dynamic dead zone control, so that the position of a bottom dead center is stably converged for a long time, and the stamping precision and consistency are improved.

A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

The invention discloses a domestic heterogeneous chip dynamic power consumption cooperative scheduling method oriented to a vehicle-mounted environment, and aims to solve the problem of system energy efficiency optimization caused by strict limitation of power supply and heat dissipation resources, dynamic mixing of calculation tasks and unique power consumption characteristics of domestic chips in the vehicle-mounted environment. The method is based on a vehicle-mounted heterogeneous computing platform comprising a domestic central processing unit, a field programmable gate array and a memory, and is realized through a closed-loop scheduling process executed by the central processing unit. According to the method, global, dynamic and collaborative power consumption management of domestic heterogeneous chip resources is realized, and the overall energy efficiency and the operation reliability of the system are remarkably improved on the premise of ensuring the real-time performance and the performance of a vehicle-mounted task.

A telecommunications switch-type platform positioned between a private-branch exchange and a data network dynamically hosts artificial-intelligence agents that interpret, transcribe, translate and transliterate live call traffic while the session is in progress. Machine-readable instructions stored in local memory instantiate, migrate and terminate the agents on demand across dedicated processing resources such as field-programmable gate arrays, application-specific integrated circuits or system-on-chip devices, thereby maintaining end-to-end latency below 250 milliseconds. An integrated call-audio recorder captures bidirectional media streams for secure archiving without interrupting service. The platform exposes a network interface that passes both signalling and media traffic, enabling seamless deployment inside call-centre or enterprise environments and compatibility with softswitch architectures conforming to class-4 Computational Interpretation of Communication using Artificial Intelligence standards. The same functional stack is deliverable as a computer-implemented method and as a non-transitory machine-readable medium storing the instructions executed by the processing resources.

An artificial intelligence-based business management system for real-time decision optimization, consisting of: a data acquisition unit configured to ingest structured, semi-structured and unstructured data streams from enterprise resource planning (ERP) systems, customer relationship management (CRM) platforms, Internet of Things (IoT) devices, external market feeds and financial transaction systems, encrypting, timestamping and verifying the data prior to further processing; a graph processing unit that is communicatively connected to the said acquisition layer, wherein the unit is configured to encode heterogeneous data into dynamic graph structures comprising nodes representing business entities and edges representing transaction or relationship dependencies, wherein the unit is further configured to perform deduplication, metadata tagging and real-time data synchronization; a decision optimization unit operationally linked to the graph processing unit, wherein the decision optimization unit includes modules for reinforcement learning, modules for Bayesian optimization and multi-objective solvers configured to simulate multiple alternative decision paths and select an optimal path based on performance indicators such as cost efficiency, resource utilization, customer satisfaction and risk minimization; a real-time inference control unit with specialized hardware cores, including at least one graphics processing unit (GPU), a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC), wherein the accelerator performs inference tasks of the decision optimization unit with a latency in the millisecond range; a diagnostic processing unit configured to generate causal diagrams, feature mapping maps, and interpretable result summaries according to the optimization outputs; and a control interface unit configured to transmit optimized decisions to process controls within the enterprise, robot actuators, planning systems or interactive dashboards, with the interface supporting bidirectional communication for higher-level interventions, error feedback and triggers for re-optimization.

The utility model discloses a dynamic signal acquisition circuit based on an FPGA kernel, and belongs to the technical field of signal acquisition. Comprising a field programmable gate array (FPGA) which is connected with a first synchronous dynamic random access memory (SDRAM), an ARM processor and a plurality of analog-to-digital converters (ADC). The input end of the analog-to-digital converter ADC is connected with the output end of the signal conditioning board; the input end of the signal conditioning board is connected with the dynamic acceleration sensor, the strain sensor and the displacement sensor and receives signals output by the sensors; the ARM processor is connected with a nonvolatile storage device FLASH and a second synchronous dynamic random access memory SDRAM; and the field programmable gate array FPGA is used for filtering and converting the acquired data and transmitting the data to the ARM processor. According to the utility model, synchronous acquisition, synchronous processing, synchronous analysis and synchronous transmission can be realized; the signal conditioning circuit adopts a modular design and can be compatible with sensors of various dynamic signals.

The invention relates to the technical field of electric connector weak light assembly vibration compensation alignment methods, particularly discloses an electric connector weak light assembly vibration compensation alignment method, and aims to solve the problems of low electric connector assembly positioning precision and high pseudo soldering rate caused by vibration in a weak light environment. The method comprises the following steps: monitoring the thermal radiation change of a vibration source in real time through an infrared thermal imaging sensor, and pre-judging a vibration acceleration vector in combination with a lightweight long-short-term memory neural network; synchronously triggering dual polarization angle imaging to respectively capture a housing reference mark and an enhanced terminal metal feature; the vibration data and the polarization image flow are fused in the field programmable gate array, a self-adaptive optical flow algorithm is adopted to resolve the displacement compensation amount, and a piezoelectric ceramic actuator is driven to carry out submicron order reverse displacement compensation; when the compensation amount exceeds a threshold value, a low-delay correction instruction is sent to the robot through an Ethernet control automation technology bus, and the steady-state error is ensured to be smaller than 0.3 micrometer by combining a strain gauge fine tuning feedback loop. According to the technical scheme, the assembling precision, efficiency and production line adaptability are remarkably improved.

Aspects of embodiments of the present disclosure relate to a field programmable gate array (FPGA) configured to implement an exponential function data path including: an input scaling stage including constant shifters and integer adders to scale a mantissa portion of an input floating-point value by approximately log2 e to compute a scaled mantissa value, where e is Euler's number; and an exponential stage including barrel shifters and an exponential lookup table to: extract an integer portion and a fractional portion from the scaled mantissa value based on the exponent portion of the input floating-point value; apply a bias shift to the integer portion to compute a result exponent portion of a result floating-point value; lookup a result mantissa portion of the result floating-point value in the exponential lookup table based on the fractional portion; and combine the result exponent portion and the result mantissa portion to generate the result floating-point value.

Aspects of the present disclosure include methods for identifying measurement uncertainty associated with light detected from a sample. Methods according to certain embodiments include introducing a sample into a flow cytometer, flowing the introduced sample in a flow stream, irradiating the sample in the flow stream with a light source, detecting light from particles in the sample flowing in the flow stream and, identifying measurement uncertainty associated with the detected light. In some embodiments, measurement uncertainty is identified corresponding to individual particles in the sample. In certain embodiments, measurement uncertainty is identified for individual parameters of detected light for particles in the sample. Methods according to some embodiments further comprise generating a quality score for each particle based on the measurement uncertainty for each particle. Systems, integrated circuit devices (e.g., a field programmable gate array) and non-transitory computer readable storage mediums for practicing the subject methods are also provided.

Embodiments herein relate to testing chiplets during the manufacturing process. In one aspect, an on-chiplet interface is provided which allows testing of inter-chiplet communications of a chiplet on a package substrate without requiring the use of another chiplet. The interface communicates with an external Field-Programmable Gate Array (FPGA) on the package substrate at a reduced frequency compared to a frequency of the inter-chiplet communications. The FPGA can in turn communicate with a workstation to receive instructions and provide test results. The FPGA sends test pattern signals to, and evaluates corresponding responses from, circuitry of the chiplet which implements an inter-chiplet communication standard such as the Universal Chiplet Interconnect Express (UCIe) standard. In another aspect, the physical layer (PHY) circuits of two chiplet are tested with respective FPGAs.

The invention provides a quantum circuit system based on an AES cryptosystem and an encryption method. The quantum circuit system based on the AES cryptosystem comprises a byte replacement module which adopts a pre-optimized S-box query circuit to realize non-linear byte replacement; the row shift module completes in-row byte cyclic shift through quantum bit exchange operation; the column confusion module realizes a matrix multiplication circuit based on finite field operation, and a quantum circuit of the column confusion module is generated by a depth-first matrix decomposition algorithm; and the round key adding module realizes XOR operation of a round key and a state by using a CNOT gate array, and a key required by the round key adding module is dynamically generated through a key expansion circuit. And a compact Z-shaped architecture is adopted to optimize time sequence scheduling and resource allocation of each module. On the premise of keeping the quantum bit resource usage amount equivalent to that of an original Z-shaped architecture, the quantum circuit depth is remarkably reduced, and higher fidelity and shorter execution time can be realized on NISQ equipment.

Embodiments herein are directed to systems and methods for enhancing the security of multi-tenant FPGA operations. A multi-tenant field-programmable gate array (FPGA) system may include a first fabric partition and a second fabric partition. A periphery of the second fabric partition may be programmed with barrier logic to isolate the second fabric partition from the first fabric partition.

The invention relates to a metal resonator gyroscope temperature drift online compensation system and method based on parameter real-time identification. The system comprises a metal resonator gyroscope, a field programmable gate array (FPGA), a temperature sensor, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a microcontroller ARM and a memory. The metal resonant gyroscope is used for sensing the external angular velocity; the field programmable gate array FPGA is used for generating an excitation signal and detecting a vibration signal; the temperature sensor is used for detecting the working temperature of the gyroscope in real time; the ADC is used for synchronously converting the collected gyroscope vibration signal, temperature signal and excitation signal; the digital-to-analog converter DAC is used for converting an excitation signal generated by the field programmable gate array FPGA and outputting the excitation signal to the metal resonant gyroscope; the microcontroller ARM is responsible for operating a parameter identification algorithm and compensation calculation; the memory is used for storing initial model parameters, algorithm programs and real-time data. According to the invention, high-precision compensation in a full-temperature zone can be realized, and the zero-bias stability, the scale factor linearity and the environmental adaptability of the gyroscope can be obviously improved.

The invention discloses a seamless range switching system and a seamless range switching method for instrument current measurement. The seamless range switching system comprises a digital-to-analog converter, an error amplifier, a first driving circuit, a first current measurement circuit, a clamping circuit, a second driving circuit, a second current measurement circuit, two analog-to-digital converters and a field programmable gate array. The first current measuring circuit converts 10 [mu] A to 30 mA low current into a first voltage signal to form a negative feedback closed loop. When the first voltage signal reaches a Zener breakdown threshold value, the clamping circuit outputs a trigger signal to start the second driving circuit, so that the two driving circuits jointly provide a total current of 30mA to 500mA for the load; the two analog-to-digital converters perform synchronous sampling, and the field programmable gate array selects digital signal output which is in a linear measurement range and has an error not exceeding + / -0.05% of a full scale. No mechanical switch exists in the switching process, the current is uninterrupted, and wide-range high-precision continuous measurement is achieved.

Systems and methods for a new field programmable gate array (FPGA) architecture that is optimized for machine learning (ML) applications are provided. Such ML applications can specifically include, for example, artificial neural networks and deep neural networks. Various embodiments enable the design of faster and more power efficient hardware accelerators for machine learning algorithms, compared to existing FPGAs in the market. This is made possible by hard systolic matrix multiplier blocks, hard activation blocks and soft ML-centric configurable logic blocks. The matrix multiplier blocks are connected to field programmable interconnect resources to enable creation of larger matrix multipliers. The hard matrix multipliers and the hard activation blocks have programmable interconnects between them and neighboring memory or compute blocks on the device.

The invention provides an error frame injection device, method and system, and the device comprises a control register module, an error frame memory module and a medium access control module which are respectively constructed in a field programmable gate array. The control register module is used for receiving an Ethernet data frame and an error frame injection strategy, generating an Ethernet error frame, and generating an injection control signal of the Ethernet error frame according to an error injection frequency if an injection trigger condition is monitored to be established; the error frame memory module is used for receiving and storing Ethernet error frames; and the medium access control module is used for responding to the injection control signal, reading the Ethernet error frame from the error frame memory module, and injecting the Ethernet error frame into the equipment to be tested for testing. By integrating the control register module, the error frame memory module and the medium access control module in the field programmable gate array, Ethernet error frame injection is realized, and an efficient, comprehensive and economical test means is provided for high-speed Ethernet equipment.

The application discloses a kind of delay pulse generation device, method and electronic equipment based on FPGA chip, field programmable gate array FPGA chip has M delay units, the device includes: clock generation module, for generating reference clock, output clock and delay clock;Pulse generation module, for generating first output pulse according to reference clock;Delay adjustment module, for first output pulse is delayed adjustment according to delay clock, obtains second output pulse, wherein, delay adjustment module includes N delay units, N is less than or equal to M positive integer;And serial conversion module, for second output pulse is converted into parallel according to reference clock and output clock, and output delay pulse sequence.The device is based on FPGA chip internal logic to realize sub-nanosecond delay adjustment, generates sub-nanosecond delay pulse sequence, and the requirement level of peripheral circuit is low, with the advantages of low cost, simple structure, easy to realize.

The utility model discloses a high-definition multi-path image processing structure, which comprises a shell, at least one network interface arranged on the shell, a processor arranged in the shell, a video decoder arranged in the shell and connected with the network interface and the processor, and a processor arranged in the shell and connected with the network interface and the processor. And the video receiver is arranged in the shell and is connected with the video decoder and the processor. Therefore, the system chip (system-on-chip, SoC) and the field programmable gate array (field programmable gate array, FPGA) are separately arranged, so that the required FPGA and SoC can be flexibly selected for development, the cost can be effectively reduced, the processing efficiency can be improved, the overall speed can be improved, the system load of a personal computer (PC) is reduced, and the development cost of the system chip (system-on-chip, SoC) and the development cost of the system chip (system-on-chip, SoC) can be reduced. Therefore, the structure of the utility model can carry out multi-path high-quality image processing.

The application discloses a weak PUF circuit with rich excitation response based on MOS tube leakage current, comprising a first decoder, a second decoder, a third decoder, a fourth decoder, a first PUF array, a second PUF array, two transmission gate arrays and one shared header, each PUF array comprises two column units, q is an integer greater than 1, each column unit comprises two NMOS units, p is an integer greater than 1, each NMOS unit comprises an NMOS tube, under the decoding action of the first decoder, the third decoder and the second decoder, the fourth decoder on the excitation signal, a certain NMOS unit in a certain column unit in the first PUF array can be compared with any NMOS unit in any column unit in the second PUF array to generate a final output response, and the advantage is that the PUF entropy source utilization rate is improved by 2 times while the hardware overhead is kept small, and the number of CRPs is significantly improved. q p p+q ​​​

The invention relates to a tone mapping method and device, electronic equipment and a storage medium. According to the method, a first logical operation unit, a second logical operation unit, a third logical operation unit and a lookup table of a field programmable logic gate array are matched with one another. Specifically, by inputting the Y channel median value into the lookup table, the Y channel value adjustment coefficient can be directly obtained, and exponential operation between the Y channel median value and the Y channel value adjustment coefficient does not need to be carried out. By inputting the ratio of the Y channel value of each pixel stretched to the full domain to the median value of the Y channel of each pixel stretched to the full domain into the lookup table, the compression value of the Y channel can be directly obtained, and exponential operation of the ratio and the compression value of the Y channel is not needed, so that the data processing efficiency is improved, and the operation resources are saved.

The application discloses a free space optical communication real-time regulation system based on light top technology, and belongs to the field of space optical communication. An AMCC transmitting module superimposes an AMCC signal on a service signal to form a mixed optical signal by controlling the bias voltage of a VOA; the mixed optical signal is transmitted to a free space channel through a space optical lens group; a beam splitter divides the received optical signal into communication side information and control side information; on the control side, the optical signal is received by an APD and converted into an electrical signal, which is sent into an AMCC receiving module after being sampled by an ADC, and the regulation information is fed back to a coherent receiver after being processed; the coherent receiver receives the regulation information to regulate the board card state in real time; the application is based on AMCC technology, utilizes the parallel processing capacity of a field programmable gate array (FPGA), and realizes efficient regulation of free space optical communication.

A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.

An example system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, and a producer port linked with a consumer port through direct memory access (DMA). Data received by the PCIe interface is assigned to the producer port. The device includes dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz.

The invention relates to a composite sensor reading system and method, and the system comprises a composite sensor which is used for detecting environment data of a target environment; the field programmable gate array is connected with the composite sensor and is used for sending a single-bit serial instruction to the composite sensor based on a data reading instruction and receiving, identifying and storing environmental data detected by the composite sensor; the digital signal processor is connected with the field programmable gate array and used for sending a data reading instruction to the field programmable gate array and reading the environment data in the field programmable gate array, and the problem that an existing sensor reading method generally aims at a single sensor and lacks a method for reading a composite sensor can be solved.

A state estimation method for mobile robot navigation is provided which includes: step S1, initializing the processing module, and then controlling the field-programmable gate array to obtain measurement values of a moment k collected by the inertial measurement unit and the localization apparatus in a constant sampling period; step S2, controlling the application-specific integrated circuit to send the measurement values to the processing module; step S3, controlling the processing module to, based on the measurement values, sequentially perform vector padding, additional inertial vector acquisition, normalization processing, alignment error computation, filter measurement value computation, bias estimation value computation, velocity estimation value computation, pose estimation value computation and orthogonalization processing to obtain state estimation values of the moment k; step S4, controlling the processing module to send the state estimation values to the human-machine interface for visual display.

Low size, weight, power and cost (SWaP-C), flexible programmability and rapid run-time reconfigurability are desired features for the design of adaptive, underwater wireless communication modems for micro autonomous underwater vehicle (μAUV) swarms. Disclosed herein are first-generation and second-generation software and hardware design of a new class of low SWaP-C underwater modems that can accommodate wide-band acoustic front-ends and achieve s-level reconfigurability during run-time. By dynamically mapping certain signal processing operations of the acoustic communication stack to the Field Programmable Gate Array (FPGA) and others to the embedded processing system of the modem's System-on-Chip, data rates of up to 2000 bps can be achieved in ranges up to 50 m with the implementation of custom programmable logic.

The application belongs to the technical field of wind turbine simulation, and provides a wind turbine full-closed loop simulator and method based on a field programmable gate array, which comprises a field programmable gate array chip, an ARM chip and a digital-analog interface connected with the field programmable gate array chip; the application adopts the field programmable gate array chip, and realizes transient real-time simulation of the electromagnetic system of the wind turbine by means of the powerful parallel computing capability of the field programmable gate array chip; compared with the prior art, the application can quickly verify the effect of the control strategy by using the built-in controller, and can access the actual wind turbine controller through the digital-analog interface to perform hardware-in-the-loop simulation and test the control effect; meanwhile, the ARM chip is used as a real-time operation carrier of the wind turbine controller algorithm, and the field programmable gate array chip and the ARM chip interact with real-time data through a digital-analog channel to realize a wind turbine closed loop real-time simulation platform.

This invention discloses a contactless chip testing system. The platform includes a PC, a data parsing / forwarding module, a source signal excitation module, a gating array, and a chip slot under test. The platform allows for simultaneous multi-selection via a PC's visual interface, enabling automated integrated testing of resistance, capacitance, package integrity, voltage, and overall power consumption between any chip pins. Compared to traditional mechanical probe-based contact testing systems, this invention is more compact. Furthermore, it employs an automatically gating physical path switching method, resulting in a higher switching rate and more efficient package testing.

Provided in the present disclosure are an information transmission method, an apparatus, a device, a storage medium and a computer program product. The method comprises: a first network element receives first information, wherein the first information represents a resource descriptor related to a field programmable gate array (FPGA) hardware resource required by an application to be deployed, and the first information is used for generating configuration information of a target FPGA device deploying said application.