Design method of hardware accelerator based on LSTM recursive neural network algorithm on FPGA platform

Abstract

The invention discloses a method for accelerating an LSTM neural network algorithm on an FPGA platform. The FPGA is a field-programmable gate array platform and comprises a general processor, a field-programmable gate array body and a storage module. The method comprises the following steps that an LSTM neural network is constructed by using a Tensorflow pair, and parameters of the neural networkare trained; the parameters of the LSTM network are compressed by adopting a compression means, and the problem that storage resources of the FPGA are insufficient is solved; according to the prediction process of the compressed LSTM network, a calculation part suitable for running on the field-programmable gate array platform is determined; according to the determined calculation part, a softwareand hardware collaborative calculation mode is determined; according to the calculation logic resource and bandwidth condition of the FPGA, the number and type of IP core firmware are determined, andacceleration is carried out on the field-programmable gate array platform by utilizing a hardware operation unit. A hardware processing unit for acceleration of the LSTM neural network can be quicklydesigned according to hardware resources, and the processing unit has the advantages of being high in performance and low in power consumption compared with the general processor.

Description

technical field [0001] The invention relates to the field of computer hardware acceleration, in particular to a design method of an FPGA-based LSTM recursive neural network hardware accelerator. Background technique [0002] LSTM (Long Short-Term Memory) neural network is a kind of recurrent neural network (RNN), which is widely used in sequence processing applications. It solves the traditional problem by replacing the neurons in the ordinary RNN network with LSTM components. The long-term dependence problem in RNN network training. Since the LSTM component representing a neuron contains four gates, each gate must be connected to the input node, and the value received by each gate must also undergo a series of operations to obtain the output value of the LSTM component, so when the neural network When the number of LSTM components contained in the hidden layer in , the amount of computational tasks inside the neural network and the power consumption will be very large. Th...

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However, the high energy consumption of GPU has

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