A system includes one or more processors; one or more trace debug circuits configured to monitor one or more of instruction, data, and watchpoint buses of the one or more processors, and record information determined from said monitoring; and a sequence processing unit configured to provide a control signal to a trace debug circuit of the one or more trace debug circuits, wherein in response to the control signal, the trace debug circuit controls one or more of said monitoring and recording, and a system on a chip comprises the one or more processors, the one or more trace debug circuits, and the sequence processing unit.