11results about "Operational speed enhancement" patented technology

Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and / or performance issues relating to GPU processing / caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

Data processing methods and apparatus are disclosed. A processor-implemented data processing method includes receiving a request for executing a neural network model on an accelerator, generating a plurality of candidate kernels for each of a plurality of layers included in the model, and assigning a single candidate kernel to the accelerator, the single candidate kernel being selected from the plurality of candidate kernels generated for a layer to be run on the accelerator based on corresponding kernel information and state information of the accelerator.

Apparatus, method, and medium are provided. The apparatus includes a decoder circuit that generates a control signal in response to a vector extraction and merge instruction that specifies control parameters, a first vector register, a second vector register, and a destination vector register. The apparatus includes a processing circuit that executes processing of a plurality of beats in response to the control signal, and each beat includes processing corresponding to at least a part of the first vector register and the destination vector register. The processing for the K 番目 beats includes extracting bits specified by the control parameters from the K 番目 portion of the first vector register, concatenating the bits with further bits, and storing the result in the K 番目 portion of the destination register. The further bits are, for the first portion, extracted from the first portion of the second vector register, and otherwise, from the (K - 1) 番目 portion of the first vector register.

Circuitry for performing multiply / accumulate operations evaluates the type of each value in a pair of input values. Signed values are separated into a sign and a magnitude. One or more pairs of parameters are input to a multiplier such that the parameters have fewer bits than the magnitude of the signed or unsigned values. This can include separating the input values into multiple parameters, and inputting multiple pairs of parameters for a single pair of input values to the multiplier.

A high-performance disk device is provided. A plurality of control chips included in the disk device each include a cache control circuit and an arbitration circuit, and control one of a plurality of actuator systems. A first control chip is connected to a buffer memory via the cache control circuit included in the first control chip, and is connected to a second control chip. The second control chip is connected to the first control chip and a third control chip. An arbitration circuit included in the second control chip performs arbitration between data transfer between the third control chip and the first control chip and data transfer between an actuator system controlled by the second control chip among the plurality of actuator systems and the first control chip.

The present disclosure provides a data processing method and device, electronic equipment, storage medium and program product, relating to the technical field of large model, the method comprises: dividing an input matrix into a plurality of sub-matrices, determining the number and position index of each sub-matrix based on a grouping interleaving method; performing corresponding sub-matrix operation based on at least one computing thread block in a thread block network, and transmitting the operation result of the corresponding sub-matrix based on at least one communication thread block corresponding to the at least one computing thread block; storing the operation result of each sub-matrix in the cache based on the number sequence corresponding to each sub-matrix, determining the output matrix based on the number and position index corresponding to each sub-matrix and the operation result of the sub-matrix stored in the cache in sequence; in this way, the communication thread block is arranged between the computing thread blocks, so that the computing thread blocks can perform sub-matrix operation synchronously in the process of communication, improving the utilization rate of graphics processor resources.

Disclosed are an accelerator, a method of operating an accelerator, and an electronic device including the accelerator. The method of operating the accelerator configured to perform a target operation: packs input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation, and stores the packed input data in the memory; and performs the target operation between a portion of the input data stored in the same word in the memory and a weight of the filter.

An acceleration system includes a plurality of modules. Each of the plurality of modules includes at least one central processing unit, at least one graphics processing unit, at least one field programmable gate array, or at least one application specific integrated circuit. At least one of the plurality of modules includes at least one other of the plurality of modules such that the acceleration system is structured in a nested hierarchy.