Detecting memory-hazard conflicts during vector processing

Abstract

A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors when memory operations are performed in parallel using at least a portion of the vectors, and tracking positions in at least one of the vectors of any detected conflict between the memory addresses. Next, the processor executes the instructions for detecting the conflict between the memory addresses and tracking the positions.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 11 / 803,576, filed on May 14, 2007, entitled “Memory-Hazard Detection and Avoidance Instructions for Vector Processing,” (Attorney Docket No. APL-P4982US1) which is herein incorporated by reference. This application hereby claims priority under 35 U.S.C. § 120 to the above-listed parent patent application.[0002]This application is also related to co-pending U.S. patent application Ser. No. ______, filed on Jul. 11, 2008, entitled “Generating Stop Indicators During Vector Processing,” (Attorney Docket No. APL-P5452US2) and to co-pending U.S. patent application Ser. No. ______ filed on Jul. 11, 2008, entitled “Generating Predicate Values During Vector Processing,” (Attorney Docket No. APL-P5452US3) each of which are herein incorporated by reference.BACKGROUND[0003]1. Field of the Invention[0004]The present invention relates to techniques for improving c...

AI Technical Summary

Benefits of technology

[0012]One embodiment of the present invention provides a method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor. During operation, the processor receives instructions for detecting conflict between memory addresses in vectors ...

Problems solved by technology

Among these impediments, one of the more difficult problems to address is memory hazards, such as address hazards, in which different memory references refer to the same address.

The potential for memory hazards often restricts exploitation of many features available in modern high-performance processors.

For example, memory hazards may block instruction-level parallelism (ILP) by preventing load instructions from being hoisted above store instructions.

Furthermore, memory hazards may block data-level parallelism (DLP) by preventing compilers from vectorizing loops, or may block thread-level parallelism by preventing threads from being spawned.

However, these compilers operate without the benefit of runtime information and, therefore, cannot always predetermine if moving a load ahead of a store will be safe.

This uncertainty forces these compilers to be conservative in hoisting loads which greatly sacrifices performance.

This also greatly limits performance in superscalar in-order computers, such as those that implement very-long-instruction-word (VLIW) architectures.

In the case of DLP, existing autovectorizing compilers cannot freely vectorize code for exactly the same memory-hazard-related reasons that scalar and superscalar processors cannot freely reorder loads and stores.

In particular, aggregating a set of temporally sequential operations (such as loop iterations) into a spatially parallel vector creates essentially the same problem as reordering the loads and stores.

In either case, the sequential semantics of the program are potentially violated.

However, in the case of vector processors the ramifications are more than a mere incremental performance loss.

Consequently, vector processors are rarely built and those with short-vector facilities, such as Single-Instruction-Multiple-Data (SIMD) processors, are often underutilized.

The underlying problem for these processors is that existing compilers are severely limited in their ability to automatically vectorize code due to their inability to statically disambiguate memory references.

Similarly, in the case of thread-level parallelism existing multithreading compilers are often prevented from spawning multiple parallel threads due to the potential for memory hazards.

This limitation may not be a large problem for existing multi-core and multithreaded processors because they currently operate using coarse-grain threads and depend upon explicit parallelization by human programmers.

Unfortunately, it is difficult to scale these manual parallelization techniques.

Moreover, conflict between the memory addresses in the vectors may be associated with at least one memory hazard.

Moreover, detecting the conflict may involve identifying one or more memory hazards that lead to different results when the memory addresses are accessed in parallel than when the memory addresses are accessed in program order.

Note that a given stop indicator may indicate a critical memory hazard that leads to different results when the memory addresses in the vectors are accessed in parallel during the memory operations than when the memory addresses are accessed sequentially.

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