13 results about "Superscalar" patented technology

This invention discloses a fault handling method based on a dual-core lockstep processor. The dual-core lockstep processor includes a master processor and a slave processor. The dual-core lockstep processor receives data from the last four stages of the processor's pipeline via a fault detection module, outputting a fault flag signal and a fault program pointer. A front-end fault handling module receives the fault flag signal and the fault program pointer, performing a pipeline-level rollback. A back-end fault handling module controls the handshake and selection signals of the last four stages of the pipeline and executes a virtual write-back fault-tolerance mechanism, managing the operating status of the last four stages of the pipeline and the instruction fetch stage pipeline. This prevents data conflicts during superscalar processor fault handling, thereby achieving full coverage of fault handling while maintaining low time and area overhead, and simultaneously achieving high performance and high reliability. This invention can be widely applied in the field of dual-core lockstep processors.

The application belongs to the technical field of processors, and provides a verification method and system of a RISC-V out-of-order superscalar processor, a test program is generated based on a random instruction generator of a RISC-V instruction set, and the test program is run in parallel by an out-of-order superscalar processor and an instruction set simulator; in the running process of the out-of-order superscalar processor, retired instruction information is sequentially extracted from a reorder buffer thereof, and corresponding instruction execution results are read from a physical register file according to the information of the retired instruction, a check information queue table item of sequential execution is generated, and is stored into a check information queue; through a preset interface, the instruction set simulator is controlled to run in single step, and sequential submission results corresponding to the check information queue table item are extracted and stored into a submission result queue; the table items in the check information queue and the submission result queue are compared one by one, if the comparison is consistent, the verification is continued, and if the comparison is inconsistent, an error instruction is located. The efficiency of verification is improved.

The invention provides an operation result cache management method and a superscalar processor, and the method comprises the steps: in a transmission period of a first instruction, creating a target cache entry in a data undetermined state in a result cache module, and forwarding a target physical register index of the target cache entry to a transmission queue; the target cache entry and a target physical register used for storing a target operation result have a binding relationship, and the target operation result is obtained after the first instruction is executed; after the transmitting queue receives the target physical register index, screening out a second instruction depending on the target operation result, waking up the second instruction and marking the second instruction as a ready state; after the first instruction is executed, the target operation result is written into a target cache entry, and the target cache entry is marked as a valid state; and after the target cache entry is marked as a valid state, transmitting a second instruction in a ready state. According to the invention, delay bubbles on a dependency chain are eliminated.

The invention provides a high-order matrix multiplication calculation system and method based on an FPGA platform, and belongs to the technical field of computers.The system comprises a superscalar pipeline multiplication calculation module used for obtaining row data and column data of matrixes which are input in a serial mode and stored through a BRAM, the matrixes comprise the first matrix and the second matrix, and the first matrix and the second matrix are used for obtaining the row data and the column data of the matrixes; one BRAM stores a row of data in the first matrix; the superscale streamline multiplication calculation module is also used for carrying out multiplication calculation on each element in rows and columns of the matrix through a multiplier in a superscale serial streamline mode, and outputting each multiplication calculation result in parallel; and the superscale assembly line accumulation calculation module is used for performing assembly line processing on the superscale multiplication calculation result after receiving the superscale multiplication calculation result, performing accumulation calculation, and outputting a matrix multiplication result in parallel. According to the high-order matrix multiplication calculation system and method based on the FPGA platform, a matrix multiplication calculation structure capable of reducing the hardware resource consumption and guaranteeing the calculation speed can be provided.

The invention provides an automatic circuit design method of a TAGE branch predictor, which comprises the following steps: constructing a superscalar front-end simulator comprising a branch prediction unit, an instruction cache, an instruction queue and a prediction information cache, and simulating processor front-end behaviors through parameterized configuration; a time sequence and combinatorial logic decoupling normal form is introduced into the branch prediction unit, the branch prediction unit is decomposed into a time sequence component and a combinatorial logic component, the time sequence component comprises a global historical register, a folding historical register and a multi-stage prediction table, and the combinatorial logic component comprises a metadata generation unit, a direction prediction unit, a table item updating unit and a historical maintenance unit; obtaining input and output data of the branch prediction unit in the execution process; and based on the input and output data, generating a hardware description language code of the combinatorial logic component by using an automatic circuit design algorithm so as to realize automatic circuit design of the TAGE branch predictor. Therefore, the design efficiency and the performance of automatically designing the branch prediction component can be improved.

The present disclosure relates to a vector processor implemented on programmable hardware (e.g., a field programmable gate array (FPGA) device). The vector processor includes a plurality of vector processor channels, wherein each vector processor channel includes a vector register file having a plurality of register file libraries and a plurality of execution units. Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with Time Single Instruction Multiple Data (SIMD).

According to the automatic superscale processor design method based on the learning data dependency relationship, the superscale processor supporting instruction-level parallelism is automatically designed by learning data dependency between instructions, and the defect that dynamic dependency cannot be processed in the prior art is overcome. According to the technical scheme, dependency prediction is achieved based on a hardware-friendly machine learning model, and the most reusable state is selected from a high-dimensional processor state space through a state selector and stored in a small buffer area; and the state speculator is used for generating a hardware predictor by utilizing the selected state high-precision prediction dependence data and integrating the hardware predictor into the superscalar processor. The predictor is obtained by training a machine learning model S-BSD and comprises a state selector and a state speculator. According to the scheme, low-delay and high-precision prediction is achieved under the condition that hardware resources are limited, and parallel execution of multiple instructions is supported.

The application belongs to the technical field of integrated circuit design, and particularly relates to an extended instruction interface based on a superscalar RISC-V processor pipeline. The extended instruction interface can be connected with the superscalar RISC-V processor pipeline, and normal processing and execution of an extended instruction in a RISC-V instruction set in the processor can be completed. The application comprises original pipeline modification logic and an extensible instruction management module of an open-source adamantium processor. The pipeline modification logic completes processing logic of the extensible instruction in the pipeline, including: extensible instruction decoding logic, extensible instruction emission logic, extensible instruction write-back and retirement logic. The extensible instruction management module is responsible for behavior management of the extensible instruction between the main processor and the coprocessor, including: an instruction state management module, an instruction information management module and an instruction completion management module. Through information interaction between the extensible instruction management module and the main pipeline, the running of a program containing the extended instruction in the processor can be realized.

The application provides a method for instruction fusion using a superscalar processor and related equipment. A decoding unit obtains first instruction control signals of multiple instructions to be executed, and sends the first instruction control signals to a fusion decoding unit. The fusion decoding unit determines, for any one of at least one instruction pair, that a first instruction in the any one instruction pair is an I-type instruction, a second instruction in the any one instruction pair is an I-type instruction or an R-type instruction, and judges whether there is an instruction pair matching the any one instruction pair in a plurality of preset instruction pairs. If there is, instruction fusion is performed under the condition that a source operand of the first instruction is equal to a destination operand of the first instruction and the destination operand of the first instruction is equal to at least one source operand of the second instruction, to obtain a fusion instruction. A fusion instruction execution unit executes the fusion instruction according to an operation logic of the fusion instruction.

Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.

Techniques are disclosed relating to scheduling instructions for floating-point execution units with different capabilities. In some embodiments, a first pipeline is configured to execute a first type of floating-point operation on operands having up to a first precision and a second pipeline is configured to execute the first type of floating-point operation on operands having up to a second, greater precision. In some embodiments, round circuitry is configured to round results from an output precision of the second pipeline to an output precision of the first pipeline. Scheduling circuitry may select operations for issuance for a given cycle from multiple ready threads. This may include to prioritize a determined highest-precision operation of the first type from ready operations and assign the determined operation to a lowest-precision pipeline, of the multiple pipelines, that is configured to perform the first type of operation according to the operand precision of the determined operation.

This invention discloses a fine-grained, lock-step-tolerant, superscalar out-of-order processor design method and system. The method includes: reading the current instruction address and performing branch prediction to obtain the fetch address of the next instruction; decoding the instruction fetch to extract the opcode, source operand register number, and destination operand register number; renaming the instruction decoding result; processing the renamed instruction decoding result through a reservation station module; performing arithmetic and logical operations on the arbitrated instruction decoding result; comparing and checking the results of executed instructions and writing them into the system; reordering and buffering the written results of executed instructions before committing them to construct the superscalar out-of-order processor. This invention improves the fault detection and recovery capabilities of superscalar out-of-order processors. As a fine-grained, lock-step-tolerant, superscalar out-of-order processor design method and system, this invention can be applied to the field of fault-tolerant processor design technology.

This invention belongs to the field of integrated circuit design technology, specifically a coprocessor memory access interface based on the superscalar RISC-V processor pipeline. This invention includes modified logic for the original load-memory unit pipeline of the open-source XuanTie processor and a coprocessor memory access state machine. The modified pipeline logic handles the processing of coprocessor memory access instructions within the pipeline, including load and store pipeline borrowing logic and address conflict resolution logic. The state machine manages the instruction issuance and response behavior of coprocessor memory access instructions between the coprocessor and the main processor's load-memory pipeline, including a load state machine and a store state machine. By borrowing the main processor's load-memory pipeline through the coprocessor memory access interface, the coprocessor achieves normal memory access behavior within the system. The coprocessor connected to the main processor performs memory access operations on the L1 Cache in the system through this memory access interface, completing access to the shared data area for use by other computational operations.