24 results about "Register renaming" patented technology

Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be mapped to a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be mapped to a physical register of the first set of physical registers.

The invention provides a method for quickly releasing physical resources, a processor core and a processor, the method is applied to the processor core, and the processor core adopts an instruction pipeline mode to process an instruction; the method comprises the steps that under the condition that a register renaming unit completes register renaming operation on a first instruction, a submitting unit judges whether the first instruction is abnormal or not; and under the condition that the first instruction is determined not to be abnormal, the submitting unit releases a reordering buffer resource occupied by the first instruction, and the submitting unit sends a resource release message to the register renaming unit, the resource release message is used for notifying the register renaming unit to release the physical register resource occupied by the first instruction. According to the method, the physical resources occupied by the instruction can be more quickly released in the process that the processor core processes the instruction according to the instruction pipeline, so that the utilization rate of the physical resources and the performance of the processor can be improved.

Apparatuses, methods, and systems for register renaming are disclosed. The offset fetcher is configured to obtain a first offset and a second offset in accordance with a first register usage and a second register usage, respectively, based on thread identifiers identifying at least one of the first thread and the second thread, respectively. The first thread and the second thread execute on a processing element (PE). The address pointer generator is configured to generate at least one of the first register address and the second register address based on at least one of the first offset and the second offset, respectively. The first register address and the second register address correspond to a first operand and a second operand stored in the register file, respectively. The first thread and the second thread respectively include a first decode instruction and a second decode instruction that respectively operate on the first operand and the second operand.

A technique for register renaming is disclosed. A conflict detector circuit is configured to detect a register conflict between a first decoded instruction and a second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. A mapping circuit is configured to change the first architectural register to a second architectural register and to map the second architectural register to a second physical register different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

This invention discloses a method and apparatus for implementing an integer register file in a multi-instruction set processor. The method includes: dividing a 64-bit wide integer register file into two 32-bit bodies; adding an extension field to the integer register renaming mapping table to indicate whether the higher 32 bits of data originate from an extension of the lower 32 bits of data and how the extension is performed; identifying the access granularity of the integer register type operands during instruction decoding; reading or updating the extension field of the register renaming mapping table during the register renaming stage based on the operand type, access granularity, and the current architecture type of the multi-instruction set processor; and controlling read and write access to the integer register file during the instruction execution stage based on the access granularity and the value of the extension field. This invention aims to avoid unnecessary read and write operations on the higher 32 bits of the integer register file when accessing integer registers with 32-bit granularity, thereby reducing the power consumption of integer register file access and simplifying hardware control.

Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be mapped to a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be mapped to a physical register of the first set of physical registers.

The application provides a method for asynchronously recording a reorder processor register renaming checkpoint and rollback, belonging to the technical field of register storage, and comprising the following steps: S1, a scalar instruction processing step, which maps logical registers to physical registers through a scalar register renaming module for all instructions, and records the historical mapping relationship of a scalar target register; S2, a vector instruction processing step, which maps logical registers to physical registers through a vector register renaming module after the dispatch of the scalar instruction, supports flexible configuration such as a vector length, and the rollback processes of the two renaming modules are parallel, and if the rollback time of the vector renaming module is relatively long, the scalar renaming module can directly start working without synchronizing the state of the vector renaming module, and the correctness and efficiency of processing are ensured by the back pressure mechanism of the vector renaming module.

The invention provides a register mapping processing method and device, a processor and computer equipment. The method comprises the steps that bit width comparison is conducted on a first architecture register and a second architecture register and a physical register; and under the condition that the sum of the bit width of the first architecture register and the bit width of the second architecture register is not greater than the bit width of the physical register, mapping the first architecture register to a first bit field of the physical register, and mapping the second architecture register to a second bit field of the physical register. According to the method, the space utilization rate of the physical register can be improved, the probability of register renaming blockage caused by insufficiency of the physical register is reduced, and then the performance of the processor is improved.

An instruction execution method, an instruction execution device, an electronic device and a non-transitory computer-readable storage medium. The instruction execution method comprises: reading an instruction, wherein the instruction comprises at least one source operand; decoding the instruction to determine an operand bit width corresponding to the instruction; determining a physical register port bit width corresponding to the instruction; based on the operand bit width and the physical register port bit width, performing a register renaming operation to determine a register mapping table, wherein in the register mapping table, a logical register corresponding to each source operand of the instruction is associated with a plurality of physical registers in a physical register file corresponding to the instruction; and based on the register mapping table, executing the instruction to obtain an instruction execution result.

The invention discloses a processor chip defense method for ghost attack based on control flow misprediction, and belongs to the field of computer system structure security. The method comprises the following steps of: performing key security control in a register renaming stage, an instruction transmitting stage and an execution finishing stage of a processor: firstly, dynamically allocating an NSESL level for each instruction, and judging whether to label a target register according to the NSESL level; secondly, in an instruction transmitting stage, whether the transmission instruction is allowed to be transmitted is judged based on the NSESL and the label state; finally, after the branch instruction is analyzed, the NSESL of the instruction in the reservation station is decreased progressively, and label clearing operation is executed. The method is suitable for a processor architecture supporting out-of-order execution and branch prediction, and on the premise that the performance is not obviously influenced, speculation execution security threats caused by ghost attacks based on control flow misprediction are effectively resisted.

The invention discloses a register renaming device and method, a processor and computer equipment, and belongs to the technical field of computers. The device comprises a determining unit and a mapping unit. The determining unit is used for determining the first physical register in the candidate physical registers meeting the idle condition under the condition that the current instruction indicates that the first logic register is to be written with data; the mapping unit is used for updating the second physical register originally mapped by the first logic register into the first physical register; wherein the second physical register is released when the non-transmitted dependent instruction does not exist, and the time when the non-transmitted dependent instruction does not exist in the second physical register is earlier than the submission time of the current instruction. Based on the device, the method, the processor and the computer equipment, the second physical register can be released in advance, the utilization rate of the physical register is improved, and then the processing performance of the processor is improved. The register renaming device is suitable for an artificial intelligence processor.

The present disclosure provides an instruction execution method and device, electronic equipment and storage medium, and relates to the technical field of computer processors. The method comprises: after the register renaming pipeline stage, identifying the instruction type of the to-be-executed instruction; and performing instruction operation on the to-be-executed instruction based on the instruction type. Thus, compared with the current technology in which all types of instructions need to be sent to the dispatch queue to implement subsequent instruction operation, the present scheme can improve the instruction execution efficiency, reduce resource consumption, and enhance the flexibility and adaptability of the processor by setting different instruction types corresponding to different instruction operations.

The application provides a scalar processor, a high-performance processor and an electronic device, the scalar processor comprising: a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit; wherein the synchronization unit is configured to synchronize the scalar processor and a vector processor. The scalar processor provided by the application synchronizes the scalar processor and the vector processor through the synchronization unit, thereby efficiently executing instructions.

The invention provides a physical register distribution method and device. The method comprises the steps that an instruction distribution unit determines the required number of physical registers according to a microinstruction; when the number of the tokens of the idle complete physical registers is larger than or equal to the required number, the corresponding tokens are reduced, and an instruction renaming unit is triggered to distribute the physical registers; when the number of the tokens is smaller than the required number, physical register distribution is not carried out; the instruction renaming unit sequentially selects complete or single physical registers meeting the required data size when the physical registers are distributed, and distributes the complete or single physical registers to the corresponding microinstructions; wherein a single physical register is preferentially selected; when a single physical register is selected, a corresponding number of tokens of idle complete physical registers are returned to the beat instruction distribution unit; renaming the register, and updating the mapping relation of the register; the number of complete or single physical registers can be dynamically adjusted through a dynamic adjustment mechanism.

A technique for register renaming is disclosed. An offset retriever is configured to obtain a first offset and a second offset according to a first register usage and a second register usage, respectively, based on a thread identifier that identifies at least one of a first thread or a second thread, respectively. The first and second threads execute on a processing element (PE). An address pointer is configured to generate at least one of a first register address or a second register address based on at least one of the first offset or the second offset, respectively. The first and second register addresses correspond to first and second operands, respectively, stored in the register file. The first and second threads include first and second decoded instructions, respectively, that operate on the first and second operands, respectively.

Techniques are disclosed relating to physical register sharing. In some embodiments, a processor includes, in a register file, physical registers of a largest architected register size for a given operand type defined in an instruction set architecture (ISA). A register rename circuit of the processor is configured to assign a first physical register to an architected register of the largest architected register size. The register rename circuit is also configured to assign a first portion of a second physical register to a second ISA-defined architected register of a smaller size than the largest architected register size and a second portion of the second physical register to a third ISA-defined architected register of the smaller size. In the second assignment, the second and third architected registers of the smaller size are separate and distinct registers in the ISA.

Register renaming for a deterministically updated register is disclosed. A processor circuit is configured to operate according to an instruction set architecture that defines a plurality of architectural registers. A register file circuit includes a plurality of physical registers having a first subset dedicated for use in renaming a particular architectural register. A first counter value increments in response to execution of an instruction that updates the particular architectural register. A second counter value increments in response to retirement of a previously executed instruction that updated the particular architectural register. The counter values identify respective physical registers. A mapper circuit is configured to determine, in response to an indication that an instruction that updates the particular architectural register, if a physical register is available based on the count values. The physical register to be mapped to the architectural register is selected based on the count value of the first counter.

A register mapping circuit is provided for restoring the register mapping state associated with a flushed instruction by traversing ROB entries from a snapshot of another register mapping state. The register mapping circuit includes ROB control circuitry, a snapshot circuitry, and a register rename recovery circuitry (RRRC). The ROB control circuitry assigns ROB entries to instructions entering the processor pipeline, including target ROB entries assigned to a target instruction and other ROB entries assigned to other instructions. The snapshot circuitry captures a snapshot of the logical register-to-physical register mapping state in a rename mapping table associated with a subset of instructions that can be flushed. If the target instruction is flushed, the RRRC restores the rename mapping table register mapping state corresponding to the target instruction based on a snapshot in the ROB entries assigned to another instruction, and traverses the register mapping updates in the intermediate ROB entries.

Apparatuses, methods, and systems for register renaming are disclosed. A conflict detector circuit is configured to detect a register conflict between the first decoded instruction and the second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. The mapping circuit is configured to change the first architectural register to a second architectural register and map the second architectural register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

An apparatus comprises at least one register rename table structure comprising rename entries for indicating register mappings between architectural registers and corresponding physical registers, and register rename circuitry to update the register mappings indicated by the rename entries. Rename entries corresponding to at least one set of architectural registers support a cleared-register encoding. In response to an operation specifying a source architectural register for which a corresponding rename entry is set to the cleared-register encoding, the register rename circuitry controls the processing circuitry to process that operation with a source operand corresponding to the source architectural register being treated as having a predetermined value. In response to detection of a register clearing event indicating that at least one set of architectural registers is to be treated as having been cleared to the predetermined value, the register rename circuitry sets rename entries corresponding to the at least one set of architectural registers to the cleared-register encoding.

The invention provides a method and a device for recovering a register mapping table, a processor and computer equipment, the method is applied to the processor, and a mapping table backup storage space is arranged in the processor. The mapping table backup storage space comprises a first backup storage space used for backing up a first type of register mapping table and a second backup storage space used for backing up a second type of register mapping table. Determining the type of a register mapping table to be backed up; and under the condition that the register mapping table to be backed up only comprises the first type of register mapping table and the first backup storage space is not enough to store the register mapping table to be backed up, backing up the register mapping table to be backed up to the second backup storage space. The method can improve the register mapping table recovery efficiency of the processor.

Embodiments of the present application disclose a register renaming method and device for RISC-V matrix instructions. Embodiments of the present application obtain a busy table of a physical register, the busy table including a direction bit and a slice vector bit of the physical register; the direction bit representing a current slice operation direction of the physical register, and the slice vector bit representing a ready state of the plurality of slices of the physical register; in response to a source logical register of a matrix instruction being a two-dimensional register, a first physical register corresponding to the source logical register is determined; the direction bit and the slice vector bit of the first physical register are obtained in the busy table; in response to a slice operation direction of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, the slice vector bit of the first physical register is distributed to a launch queue. Through the above method, the launch delay and the execution period of the matrix instruction can be reduced, and the instruction per cycle (IPC) performance is improved.

The application belongs to the technical field of processors, and particularly relates to a register renaming method and system of a vector processor and a storage medium. The instruction fetching unit of the register renaming system of the vector processor is used for fetching instructions from a memory and sending the instructions to a decoding unit; the decoding unit is used for decoding the received instructions; the renaming unit is used for renaming the destination registers corresponding to the decoded scalar instructions and vector instructions into physical registers; the reordering buffer unit is used for storing the vector instructions, the scalar instructions and the renaming information of the scalar instructions; and the vector history stack unit is used for recording the renaming information of the vector instructions in microinstruction granularity. Compared with the prior art, the application can simultaneously rename the vector instructions and the scalar instructions, effectively reduces blocking, optimizes transmission bandwidth, and further improves the performance of the processor.

The invention relates to the technical field of computer system architecture, and discloses a processor clustering system and a shunting method based on instruction relevance, and the system comprises an instruction fetching unit which is connected with an instruction cache to obtain an instruction; the decoding unit is connected with the instruction fetching unit to analyze the instruction; the reordering buffer is connected with the decoding unit to record the order of the instructions and reorder the submitted instructions; the renaming unit is connected with the reordering buffer to execute register renaming and dependency management and output recognition results of the key instruction and the non-key instruction; the first assembly line is connected with the renaming unit to execute the key instruction; the second pipeline is connected with the renaming unit to execute the non-key instruction; and a bypass network bidirectionally connecting the first pipeline and the second pipeline so as to transfer the cross-cluster dependent data. According to the invention, the problems of area and power consumption caused by a complex bypass network in a symmetric structure are avoided, the problem of resource waste caused by idle function units in an asymmetric structure is solved, and the configuration and utilization efficiency of hardware resources are balanced.