42 results about "Register renaming" patented technology

The invention is suitable for the technical field of processors, and particularly relates to a vector configuration instruction implementation method and system and a storage medium. The implementation system comprises an instruction fetching unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit and a vector execution unit. The vector configuration instruction execution unit is used for obtaining the number of the idle register, renaming the received vector configuration instruction according to the number of the idle register to obtain a renamed vector configuration instruction and renaming information, and executing the renamed vector configuration instruction to obtain the renamed vector configuration instruction. And generating vector configuration information according to the execution result and sending the vector configuration information to a vector execution unit. Compared with the prior art, the vector configuration instruction is realized by introducing a register renaming technology, and simple and quick recovery can be carried out when speculative execution errors occur while the speculative execution capability is reserved, so that the design complexity can be reduced and the execution efficiency of the instruction can be improved while the performance is considered.

The invention provides a scalar processor, a high-performance processor and electronic equipment, and the scalar processor comprises an instruction fetching unit, a register renaming unit, an operation reservation stack unit, a storage reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit and a register file unit, a special vector register file unit; wherein the synchronization unit is used for synchronizing the scalar processor and the vector processor. According to the scalar processor provided by the invention, the synchronization of the scalar processor and the vector processor is realized through the synchronization unit, so that an instruction is efficiently executed.

The invention discloses a register renaming device, a processor and a method for maintaining a register mapping table, and belongs to the technical field of computers. The register renaming device comprises a mapping table caching module, a control module, a recovery module and a reordering caching ROB module, and the recovery module is configured to rename a renamed register when a speculative path of a branch instruction is wrong and a copy distributed for the branch instruction is covered. And if the number of the program instructions between the program instruction pointed by the retirement pointer of the ROB module and the branch instruction in the ROB module is greater than the number of the program instructions on the speculative path, restoring the modification of the first register mapping table based on the branch instruction according to the copy and the ROB module. According to the register renaming device provided by the invention, unexpected modifications in the first register mapping table can be recovered by combining the copies and the ROB module under the condition that the number of the copies is smaller than the number of the branch instructions, the recovery efficiency is high, and the resource overhead is low.

The invention provides a register renaming method, which comprises the following steps of: analyzing a current instruction to obtain a bit width and a serial number of a logic register; determining a target idle physical register table from the plurality of idle physical register tables according to the bit width of the logic register, and selecting a target physical register from the target idle physical register table; based on the serial number of the target physical register and the serial number of the logical register, establishing a mapping relation between the target physical register and the logical register, and storing the mapping relation between the target physical register and the logical register and the use bit of the target physical register in a renaming mapping table; and updating all idle physical register tables according to the mapping relationship between the target physical register and the logic register and the use bit of the target physical register. The invention further provides electronic equipment, a readable medium and a program product.

Methods, systems, and apparatus for reducing power to physical registers using a freelist that is used for register renaming. One of the methods includes maintaining, in a processor, a freelist that tracks the availability of physical registers of a physical register file, wherein the freelist is partitioned into a plurality of regions, each region corresponding to a subset of the physical register file. If a region of the freelist represents an inactive region of the physical register file, power is reduced to one or more physical registers is in the physical register file corresponding to the inactive region of the freelist.

Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be mapped to a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be mapped to a physical register of the first set of physical registers.

The invention provides a method for quickly releasing physical resources, a processor core and a processor, the method is applied to the processor core, and the processor core adopts an instruction pipeline mode to process an instruction; the method comprises the steps that under the condition that a register renaming unit completes register renaming operation on a first instruction, a submitting unit judges whether the first instruction is abnormal or not; and under the condition that the first instruction is determined not to be abnormal, the submitting unit releases a reordering buffer resource occupied by the first instruction, and the submitting unit sends a resource release message to the register renaming unit, the resource release message is used for notifying the register renaming unit to release the physical register resource occupied by the first instruction. According to the method, the physical resources occupied by the instruction can be more quickly released in the process that the processor core processes the instruction according to the instruction pipeline, so that the utilization rate of the physical resources and the performance of the processor can be improved.

A method, system, and apparatus are provided for reducing power to physical registers using a freelist used for register renaming. One method comprises the step of maintaining a freelist in a processor that tracks the availability of physical registers in a physical register file, wherein the freelist is partitioned into multiple regions, each region corresponding to a subset of the physical register file. If a region of the freelist represents an inactive region of the physical register file, power is reduced for one or more physical registers in the physical register file corresponding to the inactive region of the freelist.

Methods, systems, and apparatus for maintaining a hybrid freelist for register renaming. One of the methods includes maintaining a hybrid freelist representing physical registers that are available for register renaming, wherein the hybrid freelist comprises a plurality of entries having an order, each entry comprising a pair of bits for each physical register of a plurality of physical registers, wherein the pair of bits for each entry comprises a valid bit and a commit bit representing a valid state and a commit state respectively for a physical register. A head pointer and a tail pointer of the freelist are used to perform in-order allocation of free physical register names from the plurality of entries of the freelist.

Methods, systems, and apparatus for maintaining a hybrid freelist for register renaming are disclosed. One of the methods comprises the step of maintaining a hybrid freelist representing physical registers available for register renaming, wherein the hybrid freelist comprises a plurality of ordered entries, each entry comprising a bit pair for each physical register among the plurality of physical registers, and the bit pair for each entry comprises an effective bit and a commit bit representing the effective state and the commit state for the physical register, respectively. The head pointer and tail pointer of the freelist are used to perform sequential assignment of free-state physical register names from the plurality of entries of the freelist.

Apparatuses, methods, and systems for register renaming are disclosed. The offset fetcher is configured to obtain a first offset and a second offset in accordance with a first register usage and a second register usage, respectively, based on thread identifiers identifying at least one of the first thread and the second thread, respectively. The first thread and the second thread execute on a processing element (PE). The address pointer generator is configured to generate at least one of the first register address and the second register address based on at least one of the first offset and the second offset, respectively. The first register address and the second register address correspond to a first operand and a second operand stored in the register file, respectively. The first thread and the second thread respectively include a first decode instruction and a second decode instruction that respectively operate on the first operand and the second operand.

A technique for register renaming is disclosed. A conflict detector circuit is configured to detect a register conflict between a first decoded instruction and a second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. A mapping circuit is configured to change the first architectural register to a second architectural register and to map the second architectural register to a second physical register different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

The invention is suitable for the technical field of processors, and particularly relates to a register renaming method and system of a vector processor and a storage medium. An instruction fetching unit of the register renaming system of the vector processor is used for storing an instruction from a memory and sending the instruction to a decoding unit; the decoding unit is used for decoding the received instruction; the renaming unit is used for renaming destination registers corresponding to the decoded scalar instruction and vector instruction as physical registers; the reordering buffer unit is used for storing a vector instruction, a scalar instruction and renaming information of the scalar instruction; the vector history heap unit is used for recording renaming information of vector instructions with micro instruction granularity. Compared with the prior art, the method has the advantages that the vector instruction and the scalar instruction can be renamed at the same time, blocking is effectively reduced, the transmitting bandwidth is optimized, and then the performance of a processor is improved.

This invention discloses a method and apparatus for implementing an integer register file in a multi-instruction set processor. The method includes: dividing a 64-bit wide integer register file into two 32-bit bodies; adding an extension field to the integer register renaming mapping table to indicate whether the higher 32 bits of data originate from an extension of the lower 32 bits of data and how the extension is performed; identifying the access granularity of the integer register type operands during instruction decoding; reading or updating the extension field of the register renaming mapping table during the register renaming stage based on the operand type, access granularity, and the current architecture type of the multi-instruction set processor; and controlling read and write access to the integer register file during the instruction execution stage based on the access granularity and the value of the extension field. This invention aims to avoid unnecessary read and write operations on the higher 32 bits of the integer register file when accessing integer registers with 32-bit granularity, thereby reducing the power consumption of integer register file access and simplifying hardware control.

Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be mapped to a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be mapped to a physical register of the first set of physical registers.

The application provides a method for asynchronously recording a reorder processor register renaming checkpoint and rollback, belonging to the technical field of register storage, and comprising the following steps: S1, a scalar instruction processing step, which maps logical registers to physical registers through a scalar register renaming module for all instructions, and records the historical mapping relationship of a scalar target register; S2, a vector instruction processing step, which maps logical registers to physical registers through a vector register renaming module after the dispatch of the scalar instruction, supports flexible configuration such as a vector length, and the rollback processes of the two renaming modules are parallel, and if the rollback time of the vector renaming module is relatively long, the scalar renaming module can directly start working without synchronizing the state of the vector renaming module, and the correctness and efficiency of processing are ensured by the back pressure mechanism of the vector renaming module.

At least one embodiment of the invention provides an instruction processing method, a processor, an electronic device and a storage medium. The instruction processing method comprises the steps that a target record item is selected in an instruction submission queue, and a field of a target logic register number of the target record item and a field of a physical register number to be released are empty; respectively writing an object logic register number and an object physical register number mapped with the object logic register number through register renaming in a field of a target logic register number of the target record item and a field of a physical register number to be released; and submitting a target instruction corresponding to the target record item. According to the instruction processing method, simple and effective release of the physical register can be realized in a convenient vehicle building mode.

The invention provides a register mapping processing method and device, a processor and computer equipment. The method comprises the steps that bit width comparison is conducted on a first architecture register and a second architecture register and a physical register; and under the condition that the sum of the bit width of the first architecture register and the bit width of the second architecture register is not greater than the bit width of the physical register, mapping the first architecture register to a first bit field of the physical register, and mapping the second architecture register to a second bit field of the physical register. According to the method, the space utilization rate of the physical register can be improved, the probability of register renaming blockage caused by insufficiency of the physical register is reduced, and then the performance of the processor is improved.

The embodiment of the invention provides a register renaming method and a processor. The method comprises the steps of obtaining a to-be-processed target instruction; if the target instruction is a first instruction for writing a flag bit, distributing a corresponding first target physical register for a first target logic register of the first instruction according to a renaming mechanism; renaming a flag bit physical register corresponding to a first flag bit of the first instruction as the first target physical register; and according to the first destination physical register, updating table entries corresponding to the first destination logical register and the first flag bit in a renaming table. According to the embodiment of the invention, the design complexity of the flag bit related instruction in the micro-architecture is reduced, and the execution efficiency of the processor on the flag bit related instruction is improved.

The present invention provides a vector instruction processing method, apparatus, electronic device and storage medium, relating to the technical field of data processing. The method includes: allocating an empty entry for a vector instruction in an instruction ordering queue, splitting the vector instruction into vector instruction internal operations corresponding to each data element in the vector instruction, performing register renaming on each vector instruction internal operation, allocating an empty entry for each vector instruction internal operation in the vector instruction ordering queue respectively, executing the vector instruction internal operations out of order, and after writing each vector instruction internal operation back to the entry corresponding to each vector instruction internal operation in the vector instruction ordering queue, writing the vector instruction back to the entry corresponding to the vector instruction in the instruction ordering queue. The present invention provides a vector instruction processing method, apparatus, electronic device and storage medium, which can more reasonably utilize the computing resources of a processor, thereby reducing the computing resources of the processor required for vector instruction processing.

An instruction execution method, an instruction execution device, an electronic device and a non-transitory computer-readable storage medium. The instruction execution method comprises: reading an instruction, wherein the instruction comprises at least one source operand; decoding the instruction to determine an operand bit width corresponding to the instruction; determining a physical register port bit width corresponding to the instruction; based on the operand bit width and the physical register port bit width, performing a register renaming operation to determine a register mapping table, wherein in the register mapping table, a logical register corresponding to each source operand of the instruction is associated with a plurality of physical registers in a physical register file corresponding to the instruction; and based on the register mapping table, executing the instruction to obtain an instruction execution result.

The invention discloses a processor chip defense method for ghost attack based on control flow misprediction, and belongs to the field of computer system structure security. The method comprises the following steps of: performing key security control in a register renaming stage, an instruction transmitting stage and an execution finishing stage of a processor: firstly, dynamically allocating an NSESL level for each instruction, and judging whether to label a target register according to the NSESL level; secondly, in an instruction transmitting stage, whether the transmission instruction is allowed to be transmitted is judged based on the NSESL and the label state; finally, after the branch instruction is analyzed, the NSESL of the instruction in the reservation station is decreased progressively, and label clearing operation is executed. The method is suitable for a processor architecture supporting out-of-order execution and branch prediction, and on the premise that the performance is not obviously influenced, speculation execution security threats caused by ghost attacks based on control flow misprediction are effectively resisted.

Techniques for register renaming caching are described. In an embodiment, an apparatus includes a register renaming cache, front-end circuitry, lookup circuitry, and execution circuitry. The register renaming cache is to store register renaming information associated with an instruction trace. The register renaming information is to be learned from a first execution of the instruction trace and is to be used to perform register renaming in connection with a second execution of the instruction trace. The front-end circuitry is to provide, based on the instruction trace, operations for execution. The lookup circuitry to look in the register renaming cache for entries corresponding to the operations. The execution circuitry is to execute the instruction trace.

The invention discloses a register renaming device and method, a processor and computer equipment, and belongs to the technical field of computers. The device comprises a determining unit and a mapping unit. The determining unit is used for determining the first physical register in the candidate physical registers meeting the idle condition under the condition that the current instruction indicates that the first logic register is to be written with data; the mapping unit is used for updating the second physical register originally mapped by the first logic register into the first physical register; wherein the second physical register is released when the non-transmitted dependent instruction does not exist, and the time when the non-transmitted dependent instruction does not exist in the second physical register is earlier than the submission time of the current instruction. Based on the device, the method, the processor and the computer equipment, the second physical register can be released in advance, the utilization rate of the physical register is improved, and then the processing performance of the processor is improved. The register renaming device is suitable for an artificial intelligence processor.

The present disclosure provides an instruction execution method and device, electronic equipment and storage medium, and relates to the technical field of computer processors. The method comprises: after the register renaming pipeline stage, identifying the instruction type of the to-be-executed instruction; and performing instruction operation on the to-be-executed instruction based on the instruction type. Thus, compared with the current technology in which all types of instructions need to be sent to the dispatch queue to implement subsequent instruction operation, the present scheme can improve the instruction execution efficiency, reduce resource consumption, and enhance the flexibility and adaptability of the processor by setting different instruction types corresponding to different instruction operations.

The application provides a scalar processor, a high-performance processor and an electronic device, the scalar processor comprising: a fetch unit, a register renaming unit, an operation reservation stack unit, a memory reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit and a special vector register file unit; wherein the synchronization unit is configured to synchronize the scalar processor and a vector processor. The scalar processor provided by the application synchronizes the scalar processor and the vector processor through the synchronization unit, thereby efficiently executing instructions.

Techniques for register renaming caches are described. In an embodiment, an apparatus includes a register rename cache, a front-end circuit, a lookup circuit, and an execution circuit. The register renaming cache is to store register renaming information associated with the instruction trace. Register renaming information is learned from a first execution of the instruction trace and used to perform register renaming in conjunction with a second execution of the instruction trace. The front-end circuitry is to provide operations for execution based on the instruction trace. The lookup circuit is used for lookup of an entry corresponding to the operation in the register renaming cache. The execution circuitry is to execute the instruction trace.

The invention provides a physical register distribution method and device. The method comprises the steps that an instruction distribution unit determines the required number of physical registers according to a microinstruction; when the number of the tokens of the idle complete physical registers is larger than or equal to the required number, the corresponding tokens are reduced, and an instruction renaming unit is triggered to distribute the physical registers; when the number of the tokens is smaller than the required number, physical register distribution is not carried out; the instruction renaming unit sequentially selects complete or single physical registers meeting the required data size when the physical registers are distributed, and distributes the complete or single physical registers to the corresponding microinstructions; wherein a single physical register is preferentially selected; when a single physical register is selected, a corresponding number of tokens of idle complete physical registers are returned to the beat instruction distribution unit; renaming the register, and updating the mapping relation of the register; the number of complete or single physical registers can be dynamically adjusted through a dynamic adjustment mechanism.

The invention provides an instruction execution method and device, electronic equipment and a storage medium, and relates to the technical field of computer processors, the method comprises the following steps: after a register renaming pipeline stage, identifying an instruction type of a to-be-executed instruction; and performing instruction operation on the to-be-executed instruction based on the instruction type. Therefore, compared with the prior art that all types of instructions need to be sent to the dispatch queue to realize subsequent instruction operation, the scheme has the advantages that different instruction types are set to correspond to different instruction operations, so that the instruction execution efficiency can be improved, the resource consumption can be reduced, and meanwhile, the flexibility and adaptability of the processor can be enhanced.

The application belongs to the technical field of processors, and particularly relates to a vector configuration instruction implementation method, system and storage medium. The implementation system comprises a fetch unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit and a vector execution unit; the vector configuration instruction execution unit is used for obtaining an idle register number, renaming a received vector configuration instruction according to the idle register number, obtaining a renamed vector configuration instruction and renaming information, executing the renamed vector configuration instruction, and generating vector configuration information according to an execution result and sending the vector configuration information to the vector execution unit. Compared with the prior art, the application introduces a register renaming technology to implement a vector configuration instruction, retains the ability of speculative execution, and can simply and quickly recover when the speculative execution is wrong, so that the design complexity can be reduced while the performance is considered, and the execution efficiency of the instruction is improved.