11 results about "Register renaming" patented technology

Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be mapped to a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be mapped to a physical register of the first set of physical registers.

The invention provides a method for quickly releasing physical resources, a processor core and a processor, the method is applied to the processor core, and the processor core adopts an instruction pipeline mode to process an instruction; the method comprises the steps that under the condition that a register renaming unit completes register renaming operation on a first instruction, a submitting unit judges whether the first instruction is abnormal or not; and under the condition that the first instruction is determined not to be abnormal, the submitting unit releases a reordering buffer resource occupied by the first instruction, and the submitting unit sends a resource release message to the register renaming unit, the resource release message is used for notifying the register renaming unit to release the physical register resource occupied by the first instruction. According to the method, the physical resources occupied by the instruction can be more quickly released in the process that the processor core processes the instruction according to the instruction pipeline, so that the utilization rate of the physical resources and the performance of the processor can be improved.

Apparatuses, methods, and systems for register renaming are disclosed. The offset fetcher is configured to obtain a first offset and a second offset in accordance with a first register usage and a second register usage, respectively, based on thread identifiers identifying at least one of the first thread and the second thread, respectively. The first thread and the second thread execute on a processing element (PE). The address pointer generator is configured to generate at least one of the first register address and the second register address based on at least one of the first offset and the second offset, respectively. The first register address and the second register address correspond to a first operand and a second operand stored in the register file, respectively. The first thread and the second thread respectively include a first decode instruction and a second decode instruction that respectively operate on the first operand and the second operand.

A technique for register renaming is disclosed. A conflict detector circuit is configured to detect a register conflict between a first decoded instruction and a second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. A mapping circuit is configured to change the first architectural register to a second architectural register and to map the second architectural register to a second physical register different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

This invention discloses a method and apparatus for implementing an integer register file in a multi-instruction set processor. The method includes: dividing a 64-bit wide integer register file into two 32-bit bodies; adding an extension field to the integer register renaming mapping table to indicate whether the higher 32 bits of data originate from an extension of the lower 32 bits of data and how the extension is performed; identifying the access granularity of the integer register type operands during instruction decoding; reading or updating the extension field of the register renaming mapping table during the register renaming stage based on the operand type, access granularity, and the current architecture type of the multi-instruction set processor; and controlling read and write access to the integer register file during the instruction execution stage based on the access granularity and the value of the extension field. This invention aims to avoid unnecessary read and write operations on the higher 32 bits of the integer register file when accessing integer registers with 32-bit granularity, thereby reducing the power consumption of integer register file access and simplifying hardware control.

The application provides a method for asynchronously recording a reorder processor register renaming checkpoint and rollback, belonging to the technical field of register storage, and comprising the following steps: S1, a scalar instruction processing step, which maps logical registers to physical registers through a scalar register renaming module for all instructions, and records the historical mapping relationship of a scalar target register; S2, a vector instruction processing step, which maps logical registers to physical registers through a vector register renaming module after the dispatch of the scalar instruction, supports flexible configuration such as a vector length, and the rollback processes of the two renaming modules are parallel, and if the rollback time of the vector renaming module is relatively long, the scalar renaming module can directly start working without synchronizing the state of the vector renaming module, and the correctness and efficiency of processing are ensured by the back pressure mechanism of the vector renaming module.

An instruction execution method, an instruction execution device, an electronic device and a non-transitory computer-readable storage medium. The instruction execution method comprises: reading an instruction, wherein the instruction comprises at least one source operand; decoding the instruction to determine an operand bit width corresponding to the instruction; determining a physical register port bit width corresponding to the instruction; based on the operand bit width and the physical register port bit width, performing a register renaming operation to determine a register mapping table, wherein in the register mapping table, a logical register corresponding to each source operand of the instruction is associated with a plurality of physical registers in a physical register file corresponding to the instruction; and based on the register mapping table, executing the instruction to obtain an instruction execution result.

A technique for register renaming is disclosed. An offset retriever is configured to obtain a first offset and a second offset according to a first register usage and a second register usage, respectively, based on a thread identifier that identifies at least one of a first thread or a second thread, respectively. The first and second threads execute on a processing element (PE). An address pointer is configured to generate at least one of a first register address or a second register address based on at least one of the first offset or the second offset, respectively. The first and second register addresses correspond to first and second operands, respectively, stored in the register file. The first and second threads include first and second decoded instructions, respectively, that operate on the first and second operands, respectively.

A register mapping circuit is provided for restoring the register mapping state associated with a flushed instruction by traversing ROB entries from a snapshot of another register mapping state. The register mapping circuit includes ROB control circuitry, a snapshot circuitry, and a register rename recovery circuitry (RRRC). The ROB control circuitry assigns ROB entries to instructions entering the processor pipeline, including target ROB entries assigned to a target instruction and other ROB entries assigned to other instructions. The snapshot circuitry captures a snapshot of the logical register-to-physical register mapping state in a rename mapping table associated with a subset of instructions that can be flushed. If the target instruction is flushed, the RRRC restores the rename mapping table register mapping state corresponding to the target instruction based on a snapshot in the ROB entries assigned to another instruction, and traverses the register mapping updates in the intermediate ROB entries.

Apparatuses, methods, and systems for register renaming are disclosed. A conflict detector circuit is configured to detect a register conflict between the first decoded instruction and the second decoded instruction. The register conflict is associated with a first architectural register and a first physical register corresponding to the first architectural register. The mapping circuit is configured to change the first architectural register to a second architectural register and map the second architectural register to a second physical register that is available and different from the first physical register. The first decoded instruction and the second decoded instruction are decoded from a single thread in a processing element (PE).

Embodiments of the present application disclose a register renaming method and device for RISC-V matrix instructions. Embodiments of the present application obtain a busy table of a physical register, the busy table including a direction bit and a slice vector bit of the physical register; the direction bit representing a current slice operation direction of the physical register, and the slice vector bit representing a ready state of the plurality of slices of the physical register; in response to a source logical register of a matrix instruction being a two-dimensional register, a first physical register corresponding to the source logical register is determined; the direction bit and the slice vector bit of the first physical register are obtained in the busy table; in response to a slice operation direction of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, the slice vector bit of the first physical register is distributed to a launch queue. Through the above method, the launch delay and the execution period of the matrix instruction can be reduced, and the instruction per cycle (IPC) performance is improved.