2 results about "Register renaming" patented technology

The application provides a method for asynchronously recording a reorder processor register renaming checkpoint and rollback, belonging to the technical field of register storage, and comprising the following steps: S1, a scalar instruction processing step, which maps logical registers to physical registers through a scalar register renaming module for all instructions, and records the historical mapping relationship of a scalar target register; S2, a vector instruction processing step, which maps logical registers to physical registers through a vector register renaming module after the dispatch of the scalar instruction, supports flexible configuration such as a vector length, and the rollback processes of the two renaming modules are parallel, and if the rollback time of the vector renaming module is relatively long, the scalar renaming module can directly start working without synchronizing the state of the vector renaming module, and the correctness and efficiency of processing are ensured by the back pressure mechanism of the vector renaming module.

Embodiments of the present application disclose a register renaming method and device for RISC-V matrix instructions. Embodiments of the present application obtain a busy table of a physical register, the busy table including a direction bit and a slice vector bit of the physical register; the direction bit representing a current slice operation direction of the physical register, and the slice vector bit representing a ready state of the plurality of slices of the physical register; in response to a source logical register of a matrix instruction being a two-dimensional register, a first physical register corresponding to the source logical register is determined; the direction bit and the slice vector bit of the first physical register are obtained in the busy table; in response to a slice operation direction of the matrix instruction on the first physical register being the same as the direction bit of the first physical register, the slice vector bit of the first physical register is distributed to a launch queue. Through the above method, the launch delay and the execution period of the matrix instruction can be reduced, and the instruction per cycle (IPC) performance is improved.