35 results about "Rename" patented technology

The invention relates to a distributed file system recycle bin performance optimization method, which comprises the following steps: in the execution process of an unlink interface of a Linux file system, sequentially completing recycle bin function starting judgment, file deletability verification and recycle bin storage suitability judgment, and obtaining metadata of a target deleted file parent directory from a server; when a file system is created, a global unified root recycle bin directory is synchronously generated, and when a file is deleted, a corresponding recycle bin subdirectory is created in a target MDS based on a parent directory inode number; an atomic operation is executed through a Linux standard rename interface, the file is moved to a corresponding recycle bin subdirectory, and the operation is limited to the interior of a single MDS; when the file is recovered, extracting an inode number of a parent directory, and iteratively querying metadata to restore an original complete path; and during batch recovery, if the original catalogue does not exist or needs to be recovered to a new catalogue, directly and integrally moving the catalogue corresponding to the recycle bin, otherwise, executing recovery operation one by one. The file deletion and recovery performance is remarkably improved, the resource overhead is reduced, and the data consistency is guaranteed.

The invention provides an immediate operand instruction fusion method, an immediate operand instruction fusion device, electronic equipment and a computer program product. In a renaming stage, aiming at a RAW instruction having data read-after-write RAW correlation with a first loading immediate operand instruction, according to a source logic register number index register mapping table of the RAW instruction, the first loading immediate operand instruction is subjected to data read-after-write RAW correlation; obtaining a first status bit and a first table item of a source operand of the RAW instruction; and obtaining a fusion instruction by combining the RAW instruction with a first immediate value of a first loading immediate number instruction stored in the first table item under the condition that the table item storage content corresponding to the source logic register number is determined to be the immediate value according to the first status bit. Therefore, the immediate operand is directly fused to the RAW instruction in the renaming stage by utilizing the extended register mapping table, so that the dependence of instruction fusion on the adjacent program sequence is broken, a consumer instruction can obtain the operand without waiting for the execution of the immediate operand loading instruction, and the instruction execution delay is remarkably reduced.

The application discloses a security reinforcement method and device based on a programming language library, and aims to solve the technical problem that site administrators currently usually manually reinforce the security of sites, and the sites are prone to missing replacement and missing modification. The method comprises the following steps: obtaining a programming language script matched with a regular expression from a target folder storing a script file according to the regular expression; renaming a script name corresponding to the programming language script according to a preset script dictionary, so as to obtain a specified script name after renaming; determining a hyper text markup language document referencing the programming language script, and modifying the name of the programming language script referenced in the hyper text markup language document according to the specified script name.

1. The name of the present design product: the operation area of the graphical user interface for file renaming of electronic device. 2. The use of the present design product: an electronic device. 3. The design points of the present design product: the partial graphical user interface in the electronic device. 4. The picture or photo that best shows the design points: design 1 front view. 5. Design 1 is designated as the basic design. 6. The use of the graphical user interface: the graphical user interface is used for file renaming. The partial graphical user interface that is claimed is used for file renaming. 7. The human-computer interaction mode of the graphical user interface: the user can perform batch renaming of files by touching or clicking the smartly recommended renaming instruction in the design 1 front view. The user can modify the file name in the file name edit box in the design 2 front view to achieve file renaming. The user can undo the renaming of a certain file by touching or clicking the undo button in the design 3 front view. In response to the user touching or clicking the file name edit box of a certain file in the design 4 front view, the graphical user interface changes from the design 4 front view to the design 4 changed state view to retract the instruction input box of smart renaming. In response to the user touching or clicking the smartly recommended renaming instruction in the design 5 front view, the graphical user interface changes from the design 5 front view to the design 5 changed state view to display the batch renaming result of the files. The user can perform batch renaming of files by touching or clicking the smartly recommended renaming instruction in the design 6 front view. The user can modify the file name in the file name edit box in the design 7 front view to achieve file renaming. The user can undo the renaming of a certain file by touching or clicking the undo button in the design 8 front view. In response to the user touching or clicking the file name edit box of a certain file in the design 9 front view, the graphical user interface changes from the design 9 front view to the design 9 changed state view to retract the instruction input box of smart renaming. In response to the user touching or clicking the smartly recommended renaming instruction in the design 10 front view, the graphical user interface changes from the design 10 front view to the design 10 changed state view to display the batch renaming result of the files. 8. Other circumstances that need to be explained: the part of the graphical user interface shown by the dashed line in each view of designs 1 to 10 does not constitute the part claimed in the present design.

The present application relates to the technical field of computer software development and version control, and particularly relates to a software technical debt identification and quantification method and system based on version control logs. The method obtains version control logs containing commit records, commit parent node relationships, branch reference records, merge commit records, merge conflict records, code difference records, file renaming records and version tag records, constructs a merge propagation graph anchored by version tags and a code entity identity chain; generates a merge influence unit for a merge commit node within a version tag interval, identifies source branch introduction segments, conflict resolution segments, target branch coverage segments and pre-tag re-introduction segments on the same code entity identity chain; when the above segments are connected in the order of merge propagation edges and commit topologies, a version propagation closed loop technical debt event is generated and a technical debt quantification record is formed.

This application provides a data processing method, apparatus, device, and medium. The method includes: if a linking error is detected due to an identifier conflict in the source program during the linking process, then obtaining a first identifier mapping table between the conflicting identifiers in the source program and the corresponding source program; determining a first file to which the conflicting identifier belongs in the first identifier mapping table; renaming the conflicting identifiers in the first file to obtain a second file; replacing the first file in the source program with the second file to obtain an updated source program; obtaining a second identifier mapping table corresponding to the updated source program; comparing and analyzing the first identifier mapping table and the second identifier mapping table to generate an evaluation report for the second file. Implementing this application embodiment can improve the processing efficiency of conflicting identifiers while ensuring that the stability and performance of the program are not affected.

The invention discloses a design draft transcoding method and device, a medium, electronic equipment and a program product, and relates to the technical field of computers, and the method comprises the steps: obtaining an initial code of a to-be-transcoded design draft in response to a received transcoding request for the to-be-transcoded design draft; the initial code is optimized through a first agent, an optimized code is obtained, the optimized code is obtained by executing optimization operation on the initial code through the first agent in combination with a cue word rule, and the optimization operation comprises at least one of component reconstruction, component abstract rendering, style abstraction, component renaming and attribute definition. According to the method, optimization processing such as component reconstruction, component abstract rendering, style abstraction, component renaming and attribute definition is performed on the initial code by utilizing the first agent, so that the code acquisition quality can be improved to a great extent.

The invention relates to a code error feedback method combining static analysis and dynamic analysis, and mainly solves the problems of insufficient error feedback and low efficiency in an Online Judge system: reconstructing codes of correct and error versions, including alignment and renaming of variables, and rearranging statements on the premise of not influencing semantics; static and dynamic multi-level alignment is carried out, in the static alignment, an editing script with the minimum cost is calculated through a heuristic editing distance algorithm, an alignment block and a difference list are obtained, in the dynamic alignment, compiling execution is carried out on source codes of two versions, test cases which do not pass operation are dynamically printed through gdb, and execution track information of the test cases is dynamically printed through gdb; error positioning is achieved, data flow backtracking analysis and scoring are carried out on error positions, and error feedback is generated. The method has the characteristics of high execution efficiency, high accuracy and easier understanding of generated feedback, automatic feedback of error codes can be realized, and the learning efficiency of students in programming tasks is improved.

One or more techniques and / or computing devices are provided for managing an arbitrary set of storage items using a granset. For example, a storage controller may host a plurality of storage items and / or logical unit numbers (LUNs). A subset of the storage items are grouped into a consistency group. A granset is created for tracking, managing, and / or providing access to the storage items within the consistency group. For example, the granset comprises application programming interfaces (APIs) and / or properties used to provide certain levels of access to the storage items (e.g., read access, write access, no access), redirect operations to access either data of an active file system or to a snapshot, fence certain operations (e.g., rename and delete operations), and / or other properties that apply to each storage item within the consistency group. Thus, the granset provides a persistent on-disk layout used to manage an arbitrary set of storage items.

Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be mapped to a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be mapped to a physical register of the first set of physical registers.

The invention discloses a decoupling method and device, a program product, a server and a storage medium, and relates to the field of servers. Aiming at the problem that firmware versions of the BMC and the BIOS must be always kept synchronous due to tight coupling between the BMC and the BIOS, a decoupling method is provided, and accurate matching of fields is carried out by introducing semantic hash values instead of field names. Wherein the semantic hash value can better represent the essential meaning of the field compared with the field name, so that the surface name is not required to be completely consistent. Therefore, the field matching is carried out by replacing the field name with the semantic hash value, so that the compatibility can be improved, and the automatic renaming of the field name can be realized. On the basis of the method, the coupling between the BIOS and the BMC can be reduced, so that the BMC and the BIOS version can be independently upgraded without synchronous maintenance, and the operation and maintenance cost is remarkably reduced.

This invention belongs to the field of computer technology, specifically relating to a method, apparatus, device, and storage medium for determining conflicting symbols between dynamic libraries. From pre-stored dynamic library files of a target application, target external symbols that are repeatedly defined in multiple dynamic libraries are selected. The target dynamic library files containing the target external symbols are disassembled to obtain the corresponding assembly code for each target dynamic library. By determining whether the assembly code corresponding to the target external symbols in each target dynamic library is completely identical, conflicting target external symbols between the target dynamic libraries can be identified. Therefore, developers can rename only the conflicting target external symbols between target dynamic libraries, saving application development time and resources and improving work efficiency.

Apparatus and methods for dependency tracking, chaining, and / or fusing for vector instructions. A system, processor, or integrated circuit includes a renamer to generate a valid bit mask for each micro-operation decoded from a first vector instruction, where the valid bit mask indicates what portion of a mask register to write and generate a dependency bit mask for each micro-operation decoded from a second vector instruction, where the dependency bit mask is based on a relationship between the first vector instruction and the second vector instruction, and an issue queue configured to issue for execution each micro-operation from the second vector instruction when an associated dependency bit mask is cleared based on execution of appropriate micro-operations from the first vector instruction.

The application discloses a dependency version uniform replacement and security control method and system for Java, and belongs to the technical field of software development. The method comprises the following steps: acquiring a project version number of a current Java project, and calculating a corresponding target major version number; parsing a build description file of the project, and extracting all dependency items defined in the build description file; acquiring a corresponding dependency version mapping strategy and a global disabled dependency list based on the target major version number; matching the extracted dependency items with the global disabled dependency list, and if there is a matching item, terminating the subsequent process and reporting an error; if there is no disabled dependency, replacing all dependency declarations identified as snapshot versions in the build description file with formal version numbers specified in the mapping strategy according to the dependency version mapping strategy; executing a compilation command of the project, and after the compilation is successful, renaming a generated binary product file according to a preset naming rule. The application realizes the determinacy, safety and standardization of production construction.

Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be mapped to a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be mapped to a physical register of the first set of physical registers.

The application provides a method for asynchronously recording a reorder processor register renaming checkpoint and rollback, belonging to the technical field of register storage, and comprising the following steps: S1, a scalar instruction processing step, which maps logical registers to physical registers through a scalar register renaming module for all instructions, and records the historical mapping relationship of a scalar target register; S2, a vector instruction processing step, which maps logical registers to physical registers through a vector register renaming module after the dispatch of the scalar instruction, supports flexible configuration such as a vector length, and the rollback processes of the two renaming modules are parallel, and if the rollback time of the vector renaming module is relatively long, the scalar renaming module can directly start working without synchronizing the state of the vector renaming module, and the correctness and efficiency of processing are ensured by the back pressure mechanism of the vector renaming module.

The invention provides an executable program packaging method and device, a storage medium and electronic equipment. A target program code is packaged in an executable program starter; a target dynamic link library is packaged in the executable program starter, and the target dynamic link library is a dynamic link library on which the to-be-packaged executable program depends; a target program modifier is packaged in the executable program starter, and the target program modifier is an executable program modifier corresponding to the executable program to be packaged; and renaming the executable program starter as a name corresponding to the executable program to be packaged. The executable program starter adopts static compiling, does not need to configure a running environment, is supported to be used in any unix system, and does not need a linux release version program. The method can be used in light-weight file systems such as build-root or busybox of embedded light-weight equipment, and is wide in applicability and convenient to use.

The application provides a binary security patch detection method and system, electronic equipment and storage medium, and relates to the technical field of network security.The application can effectively reduce the differential noise introduced by variable renaming, compiler optimization and other factors by processing the pseudo code of the binary program through the iterative variable mapping and differential alignment algorithm, generate the high-quality pseudo code differential text after alignment, and provide clear and accurate input basis for subsequent security analysis;Further, through the large language model agent analysis mechanism, the program semantic information across functions and processes can be intelligently identified and utilized, the security impact of the patch is deeply reasoned, and finally the accurate detection and judgment of the binary security patch are realized.The application provides a security patch detection scheme which does not depend on the source code, can effectively process the binary program difference noise, and can comprehensively utilize the context information for accurate judgment.

Parallel traversal of slice reorder buffers (SROBs) is disclosed herein for performing flush recovery. In an exemplary embodiment, a register mapping circuit provides a rename mapping table (RMT) comprising RMT entries representing logical register number (LRN) to physical register number (PRN) mappings. The register mapping circuit also provides an SROB comprising a plurality of SROB slices, each SROB slice corresponding to a respective LRN. Each SROB slice tracks non-committed instructions that write to the LRN corresponding to that SROB slice and maintains the instructions in program order with respect to each other. Upon detecting a non-committed instruction that writes to an LRN, the register mapping circuit allocates an SROB slice entry in the SROB slice corresponding to the LRN. Upon occurrence of a pipeline flush from a target instruction, the register mapping circuit restores RMT entries of the RMT to their previous mapping state based on parallel traversal of the SROB slices of the SROB.

A code obfuscation tool has been created to safely rename strings within metadata sections of an executable file or binary to obscure program functionality and structure that may be revealed by class metadata in the binary. The code obfuscation tool parses metadata sections of the binary that have references to metadata that can be potentially renamed safely and locates the corresponding strings. The code obfuscation tool identifies from predetermined metadata sections metadata that is unsafe to rename. The code obfuscation tool evaluates each string that is a candidate for renaming against heuristics-based renaming rules and the determined unsafe strings to identify strings that are safe to rename. The code obfuscation tool generates a new name for each string determined as safe to rename based on renaming constraints. The code obfuscation tool creates a mapping structure that tracks renaming of strings and uses the mapping structure for consistent renaming of string.

The invention provides a code review method and device based on a program dependency graph, computing equipment and a computer readable storage medium, the method adopts a deep semantic difference analysis method based on the program dependency graph, and non-functional changes such as code formats, annotations and variable renaming are effectively ignored; secondly, functional equivalent reconstruction operations such as an extraction method can be accurately identified by utilizing the structural characteristics of the program dependency graph; and thirdly, through a bidirectional traversal algorithm, automatically tracking and aggregating cross-file and cross-module data and control dependence, aggregating fragmented association modifications into logic cohesion'function change blocks', and presenting core changes and influences brought by the changes in a one-stop manner through a visual difference comparison report, so as to obtain a function change block. Therefore, the efficiency, the accuracy and the safety of code review are fundamentally improved.

A system may access names of the named objects stored in memory and context information within the application including object attributes of the named objects and an object hierarchy specifying hierarchical relationships among the named objects. The system may generate a generative artificial intelligence model input including at least a portion of the context information and request generation of one or more suggested names based on the at least the portion of the context information included in the generative artificial intelligence model input. The system may present the one or more suggested names for the named object. The system may receive a selection of a suggested name to yield a selected suggested name corresponding to the named object. The system may rename the named object in the memory with the selected suggested name.

A system may access names of the named objects stored in memory and context information within the application including object attributes of the named objects and an object hierarchy specifying hierarchical relationships among the named objects. The system may generate a generative artificial intelligence model input including at least a portion of the context information and request generation of one or more suggested names based on the at least the portion of the context information included in the generative artificial intelligence model input. The system may present the one or more suggested names for the named object. The system may receive a selection of a suggested name to yield a selected suggested name corresponding to the named object. The system may rename the named object in the memory with the selected suggested name.

This application provides a user code version management system, method, and electronic device. Based on the traditional JupyterHub and Linux file system, the system adds a code storage database independent of the Linux file system. In response to user-inputted save operations, a local temporary storage unit within this code storage database retrieves the user-inputted Jupyter project file from the Linux file system and submits it to the local storage unit. The local storage unit then renames the Jupyter project file according to a naming rule pre-set based on the user's username and stores it in both local and remote storage units. Thus, even if the physical machine hosting the Linux file system fails or malfunctions, the user-inputted software code still exists in both the local and remote storage units, effectively preventing code loss.

Embodiments of the present application provide an instruction processing method and device, electronic equipment and readable storage medium, relating to the technical field of computer. In the method, n instructions are selected from an instruction stream as to-be-decoded instructions of a current round, and the to-be-decoded instructions are decoded by using n decoding units to obtain a microinstruction sequence; n is an integer not less than 2. According to the input width of a renaming unit, the microinstructions in a preset cache and the microinstructions in the microinstruction sequence are delivered to the renaming unit; the preset cache is used to store the microinstructions not delivered in the last round. The microinstructions not delivered in the microinstruction sequence are written into the preset cache. n instructions are reselected from the instruction stream as to-be-decoded instructions of a next round, and the step of decoding the to-be-decoded instructions by using the n decoding units is continued to be executed until a stop condition is reached, so that the decoding throughput and decoding efficiency can be improved.

Techniques are disclosed relating to physical register sharing. In some embodiments, a processor includes, in a register file, physical registers of a largest architected register size for a given operand type defined in an instruction set architecture (ISA). A register rename circuit of the processor is configured to assign a first physical register to an architected register of the largest architected register size. The register rename circuit is also configured to assign a first portion of a second physical register to a second ISA-defined architected register of a smaller size than the largest architected register size and a second portion of the second physical register to a third ISA-defined architected register of the smaller size. In the second assignment, the second and third architected registers of the smaller size are separate and distinct registers in the ISA.

This invention relates to a performance optimization method for a distributed file system recycle bin. During the execution of the Linux file system unlink interface, the method sequentially performs recycle bin functionality activation checks, file deletability verification, and recycle bin storage compatibility checks, obtaining metadata of the parent directory of the target deleted file from the server. A globally unified root recycle bin directory is generated synchronously during file system creation. When a file is deleted, a corresponding recycle bin subdirectory is created in the target MDS based on the parent directory's inode number. An atomic operation is performed using the Linux standard rename interface to move the file to the corresponding recycle bin subdirectory; this operation is limited to a single MDS. When restoring a file, the parent directory's inode number is extracted, and the original complete path is reconstructed by iteratively querying the metadata. During batch restoration, if the original directory does not exist or needs to be restored to a new directory, the entire recycle bin directory is moved; otherwise, restoration is performed file-by-file. This significantly improves file deletion and restoration performance, reduces resource overhead, and ensures data consistency.

Register renaming for a deterministically updated register is disclosed. A processor circuit is configured to operate according to an instruction set architecture that defines a plurality of architectural registers. A register file circuit includes a plurality of physical registers having a first subset dedicated for use in renaming a particular architectural register. A first counter value increments in response to execution of an instruction that updates the particular architectural register. A second counter value increments in response to retirement of a previously executed instruction that updated the particular architectural register. The counter values identify respective physical registers. A mapper circuit is configured to determine, in response to an indication that an instruction that updates the particular architectural register, if a physical register is available based on the count values. The physical register to be mapped to the architectural register is selected based on the count value of the first counter.

The invention provides an instruction compression method and device, a processor core and computer equipment, and relates to the technical field of data compression. The instruction compression method comprises the steps of obtaining a plurality of micro-operations corresponding to at least one instruction in a current period; according to the execution unit type corresponding to each of the plurality of microoperations and a plurality of preset compression types, determining a plurality of compression modes for the plurality of microoperations; according to the compression lengths of the various compression modes, selecting a target compression mode from the various compression modes; and compressing the plurality of microoperations into the reordering buffer area by adopting a target compression mode. According to the method, multiple compression modes with the high coverage rate are determined based on execution unit types corresponding to the microoperations and multiple preset compression types, then an optimal target compression mode is determined from the multiple compression modes based on the compression length, and the multiple microoperations are compressed into a reordering buffer area in the target compression mode. In this way, more microoperations can be accommodated for the same reordering buffer area resources, the effective capacity of the reordering buffer area is improved, and then the renaming speed is increased.

This invention provides a structured text code generation method for PLC honeypots, relating to the field of computer technology. The method includes: constructing a set of protected variables; performing equivalent structural transformations on control blocks and expressions; re-segmenting the code after data flow analysis; and performing statement rearrangement, value modification, and temporary variable renaming on linear statement segments based on data dependency analysis, achieving diverse code perturbations while maintaining semantic consistency. The transformation space is further expanded through loop safety checks and large language model-assisted refinement. Finally, declaration information is supplemented and the output variant L5X file is backfilled. This invention, through semantic awareness and large language model assistance, improves the semantic consistency, formal diversity, and usability of generated code variants.