313 results about "Register file" patented technology

The invention discloses a low-power-consumption single-emission out-of-order execution RISC-V processor, which comprises seven stages of pipeline architecture, namely an instruction fetch unit, an instruction buffer unit, a decoding unit, an emission unit for single instruction emission, a physical register file, an execution unit for parallel out-of-order calculation and a retirement unit in sequence, and the instruction fetch unit is used as the front end of the RISC-V processor; a five-level pipeline architecture formed by the decoding unit, the transmitting unit, the physical register file, the execution unit and the retirement unit is used as the rear end of the RISC-V processor; through the technical scheme, the invention provides a micro-architecture which is more balanced in performance and power consumption, so that the applicability of a processor core in a scene with high computing requirements and sensitive power consumption is improved.

The invention discloses an information processing method and device, electronic equipment and a storage medium, and is applied to the field of information processing. The information processing method comprises the steps that a first utilization rate is determined in combination with a data flow between a memory and a shared memory when a processor executes a general matrix multiplication operator, and the first utilization rate is used for indicating performance evaluation of the general matrix multiplication operator at a processor level; determining a second utilization rate in combination with a data stream between a shared memory and a register file in a single computing unit when the processor executes the general matrix multiplication operator, the second utilization rate being used for indicating performance evaluation of the general matrix multiplication operator at the computing unit level; and based on the smaller one of the first utilization rate and the second utilization rate, determining the theoretical performance of the processor when executing the universal matrix multiplication operator. At present, only chip-level performance evaluation is considered in performance evaluation of a GEMM operator, and double-level-dimension theoretical performance evaluation is provided, so that the evaluation result is more accurate.

Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.

Provided are an apparatus and method for accelerating computation, and a chip. The apparatus for accelerating computation comprises: an instruction decoding module, a bit width selection module, a small bit width processing module, and a large bit width processing module. The instruction decoding module is configured to decode an inputted instruction, determine the bit width of the instruction on the basis of a decoding result, generate a control signal comprising bit width information of the instruction, and send the control signal to the bit width selection module. The bit width selection module is configured to forward the control signal to the small bit width processing module when the bit width of the instruction is a small bit width, and forward the control signal to the large bit width processing module when the bit width of the instruction is a large bit width. The small bit width processing module is configured to process the instruction by using a register file having a small bit width and a corresponding arithmetic logic unit. The large bit width processing module is configured to process the instruction by using a register file having a large bit width and a corresponding arithmetic logic unit.

The invention provides a DCU-based high-performance sparse stiffness matrix vector multiplication method, which comprises the following steps of: according to a sparse stiffness matrix, dividing a non-zero element into a plurality of calculation unit blocks by rows, pre-loading non-zero element data to an L1 shared memory or a register file through an on-chip shared memory controller of the DCU, a high-bandwidth crossbar switch of the DCU is used for realizing data copying and transmission; starting multi-row fusion execution for a short row of which the row non-zero element is lower than a DCU single-instruction multi-data width threshold value; constructing a wavefront scheduler based on a DCU asynchronous computing engine: binding an independent instruction cache region for each wavefront, and loading a multiply-add operation instruction set in advance through a prefetch instruction queue; a calculation unit state register is established, and when a wavefront scheduler ready signal is triggered, a scalar unit of the DCU is activated to execute calculation; and realizing cross-thread block reduction by adopting a DCU atomic operation accelerator. According to the method, the calculation throughput and the memory bandwidth utilization rate of large-scale structural mechanics stiffness matrix vector multiplication are effectively improved.

The invention provides a processor based on an RISC-V architecture and a data processing system and method. The processor comprises an instruction obtaining unit, an instruction decoding unit, a register file, a distribution unit, an execution unit, an expansion processing unit and a data access interface. Decoding the program instruction to obtain an instruction type and an application field type; identifying an application field type, distributing the program instruction to an execution unit and an expansion processing unit according to a preset distribution rule under the condition that the application field type accords with a preset field type, and identifying an instruction type under the condition that the application field type does not accord with the preset field type; when the instruction type of the program instruction is an RISC-V instruction set instruction, the RISC-V instruction set instruction is distributed to the execution unit, and when the instruction type of the program instruction is an extension instruction, the extension instruction is distributed to the extension processing unit; the instruction can be quickly processed for different application fields, and the instruction processing efficiency is improved.

The embodiment of the invention provides a matrix multiplication and accumulation operation unit and method, a hardware accelerator and electronic equipment, and the matrix multiplication and accumulation operation unit comprises a data loading storage engine, a tensor register file and a matrix multiplication engine. The data loading and storage engine is used for loading data of a plurality of matrixes to be subjected to matrix multiplication and accumulation calculation; the tensor register file is used for storing data of a plurality of matrixes acquired from the data loading storage engine; the tensor register file comprises at least three tensor register groups, each tensor register group comprises a plurality of tensor registers, and different tensor register groups are used for storing data of different matrixes in the plurality of matrixes; and the matrix multiplication engine is used for carrying out matrix multiplication accumulation calculation based on the data of the plurality of matrixes stored in the tensor register file. According to the embodiment of the invention, more efficient MMA calculation is realized under the conditions of low cost, low power consumption and less occupied space.

The invention discloses a sparse matrix processing method and device in an image recognition process, equipment and a medium, and relates to the field of computer image processing, and the method comprises the steps: inputting a feature image into a convolutional neural network; if the convolution kernel meets a preset sparse matrix condition, performing structured sparseness on the convolution kernel to obtain a sparse matrix, compressing the sparse matrix by using an improved compression sparse row format to obtain a compression matrix, and constructing an index matrix of the compression matrix; storing the feature image, the compression matrix, the index matrix and the preset bias matrix in a global memory, activating a target thread bundle in the computing core, and distributing the target thread bundle to a target data processing channel; loading the compression matrix and the index matrix to a shared memory corresponding to the target data processing channel by using the target thread bundle, and loading the feature image and a preset bias matrix to a register file; and executing the operation instruction to read the current matrix operation data from the shared memory and the register file to the matrix calculation unit to complete the matrix multiplication and addition operation.

An apparatus and method for efficiently processing vector memory accesses on an integrated circuit. In various implementations, a computing system includes a processing circuit with multiple compute circuits for executing wavefronts of a parallel data application. Each compute circuit includes a local memory subsystem for accessing data not found in vector register files of the compute circuit. The local memory subsystem includes a first execution pipeline and a second execution pipeline. The second execution pipeline processes vector stack access instructions that access temporary data such as stack data of a function call used by each wavefront that is generated based on the function call. The first execution pipeline processes other types of vector memory access instructions and includes multiple complex pipeline stages not found in the second execution pipeline. Thus, the second execution pipeline has a latency less than the latency of the first execution pipeline.

Provided in the embodiments of the present disclosure are a matrix multiply accumulation (MMA) operation unit and operation method, and a hardware accelerator and an electronic device. The MMA operation unit comprises a data load / store engine, a tensor register file and a matrix multiplication engine, wherein the data load / store engine is used for loading data of a plurality of matrixes to be subjected to MMA computation; the tensor register file is used for storing the data of the plurality of matrixes that is acquired from the data load / store engine; the tensor register file comprises at least three tensor register groups, each tensor register group comprising a plurality of tensor registers, and different tensor register groups being used for storing data of different matrixes among the plurality of matrixes; and the matrix multiplication engine is used for performing MMA computation on the basis of the data of the plurality of matrixes that is stored in the tensor register file. By means of the embodiments of the present disclosure, more efficient MMA computation is realized with low cost, low power consumption and a smaller footprint.

Systems and methods related to vector mask buffers in a vector instruction execution pipeline are disclosed herein. The vector instruction execution pipeline may include several lanes. Each lane may include a vector register file, a vector mask buffer, and a functional processing unit. The vector register file may store operand data and the vector mask buffer may store a vector mask associated with the operand data. In a lane, the operand data may be read from the register file into a functional processing unit, and the vector mask may be read from the vector mask buffer to the functional processing unit. The functional processing unit may process the operand data based on the vector mask. The lane-specific vector mask buffers improve the efficiency of the vector instruction execution pipeline by storing the vector masks proximate to where the vector masks will be used.

The invention discloses a matrix multiplication optimization method and system based on an RISC-V architecture, belongs to the technical field of machine learning, and aims to solve the technical problem of how to effectively improve the performance of sparse matrix multiplication. Comprising the following steps: constructing a sparse matrix adaptive to a machine learning model; the sparse matrix is converted into a structured sparse matrix, non-zero elements in the structured sparse matrix are stored in a vector register file, and column indexes corresponding to the non-zero elements are stored in a scalar register file; determining expansion factors of the internal circulation and the external circulation, and adjusting the expansion factors of the internal circulation; executing instructions in different loop iterations in a staggered manner in a staggered manner; designing and realizing a user-defined vector index multiply-add instruction; a custom vector index multiply-add instruction is executed.

The present disclosure relates to a vector processor implemented on programmable hardware (e.g., a field programmable gate array (FPGA) device). The vector processor includes a plurality of vector processor lanes, where each vector processor lane includes a vector register file with a plurality of register file banks and a plurality of execution units. Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with a temporal single-instruction multiple data (SIMD).

The invention relates to a method for calculating matrix multiplication, an artificial intelligence chip, a calculation device, a medium and a program product. The method comprises the following steps of: accumulating a calculation result of a current cycle calculation and a calculation result of a previous cycle calculation of matrix multiplication executed in a thread bundle group granularity by utilizing a buffer which is configured in a calculation core and is used for accumulation operation; determining whether the last cycle calculation of the matrix multiplication performed at the thread bundle group granularity is completed; and in response to determining that the last cycle computation of the matrix multiplication performed at the thread bundle group granularity is completed, writing the computation results accumulated via the buffer to the register file. According to the invention, the write bandwidth of the register and the occupation of the register space can be obviously reduced.

The invention provides a high-efficiency matrix engine (RVME) architecture based on RISC-V matrix extension and a calculation method, and the architecture comprises an instruction buffering and decoding module, a matrix loading / storage module, a matrix register file, a parallel outer product array and an element-by-element operation module; the matrix register file comprises a Tile register and an Acculator register; the storage modules are respectively used for storing an input matrix and an accumulation result and supporting efficient data access and parallel computing; the matrix loading / storage module significantly improves the data loading efficiency through cache line alignment and matrix transposition optimization; the instruction buffering and decoding module cooperates with a main processor through a reordering buffer area and an instruction buffer area to ensure efficient scheduling and execution of instructions. The parallel outer product array is adopted to replace a traditional systolic array, the idle period in the calculation process is eliminated through multicast data flow scheduling and a ping-pong buffer read-write mechanism, and matrix multiplication and addition operation with high calculation utilization rate and low delay is achieved.

Storing floating-point values according to an extended QFloat floating-point (xqFP) format in processor devices is disclosed herein. In some aspects, a processor device comprises a register file comprising a plurality of registers, and comprises a floating-point unit (FPU) circuit that is configured to store a first floating-point value in a register of the plurality of registers. The first floating-point value is formatted according to the xqFP format that comprises an exponent field and a significand field. The significand field is formatted as a signed one's complement value, and comprises a sign bit, an explicit most-significant-bit (MSB), a fractional field, and a deferred increment bit that represents a value of one-half (½) unit of least precision (ULP).

The invention discloses an in-memory computing accelerator, system and method based on a self-adaptive utilization rate. The in-memory computing accelerator based on the self-adaptive utilization rate comprises an in-memory computing processor, a global buffer area, a vector processor, a control module and a configuration register file, the control module and the configuration register file are respectively connected with the in-memory computing processor, the global buffer area and the vector processor, the in-memory computing processor is connected with the global buffer area, and the global buffer area is connected with the vector processor; the in-memory computing processor comprises a plurality of in-memory computing cores, and the plurality of in-memory computing cores form a dynamic parallel structure. According to the method and the device, at least one neural network reasoning calculation process can be executed on the input data aiming at the input data of a certain neural network, and relatively high space utilization rate and time utilization rate can be obtained when facing calculation requirements of different operators, so that efficient acceleration of a diversified neural network model is realized.

A computer system, a processor, and a method for processing information are disclosed, comprising at least one computer processor; a main register file associated with the at least one processor, the main register file having multiple entries for storing data, one or more write ports for writing data to the main register file entries, and one or more read ports for reading data from the main register file entries; one or more execution units, including a complex mathematical execution unit; and at least one accumulator register file having multiple entries for storing data. The results of the complex mathematical execution unit are written to the accumulator register file according to one aspect, preferably multiple times to the same accumulator register file entry, and the data from the accumulator register file are written to the main register file.

A memory device includes a plurality of memory banks, and a processing-in-memory (PIM) block accessible to the plurality of memory banks, wherein the PIM block comprises a control circuit configured to receive a plurality of operation instructions from a host and, in response to a predicated instruction indicating a predication operation among the plurality of operation instructions, instruct an arithmetic logic unit (ALU) to perform the predication operation, a predicate register file (PRF) configured to store therein a predicate value determined by the predication operation, and the ALU configured to perform an operation according to a command signal translated by the control circuit based on the predicate value from an operation instruction that depends on the predicate value among the plurality of operation instructions.

The invention relates to the technical field of computer data storage and distributed systems, in particular to a distributed read-write method for large model training, which comprises the following steps of: constructing a hierarchical structure of local cache, distributed shared cache and persistent storage, and maintaining a global cache table copy at each client to register file blocks and cache positions. And during writing, firstly writing in a local cache and copying to other client nodes, and submitting persistent storage after registration is completed. During reading, the file blocks are obtained from the local cache and the distributed shared cache in sequence, if the file blocks are not hit, the file blocks are obtained from the persistent storage, meanwhile, the effective file blocks are written back to the local, and table items are supplemented. Unified visibility is achieved through position mapping and version constraint, nearby reading and fault recovery are achieved, back-end pressure and access delay are reduced, and the method is suitable for large-scale training and batch processing scenes.

The invention provides a database concurrency control and memory access optimization method which can be applied to the technical field of computer system software performance optimization. According to the method, multi-level instruction-level reconstruction is carried out on an execution path of a database kernel through the characteristics of an underlying hardware instruction set of a collaborative application processor platform, and the method comprises the following collaborative implementation optimization dimensions: based on a register file and a cache hierarchical structure of the processor platform, an access mode of a database core data structure is optimized; the number of memory access instructions is reduced; the data locality is improved; on the basis of atomic instruction set extension of a processor platform, instruction-level reconstruction is carried out on key primitives in a database multi-thread synchronization mechanism so as to reduce the overhead and contention of synchronization operation; on the basis of single-instruction multi-data-stream extension of a processor platform and a vector atomic operation instruction of the single-instruction multi-data-stream extension, parallel acceleration is carried out on batch life cycle management operation of objects in a database.

A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on the hash instruction, the hash circuit receives a current state of the hash message from the register file and buffers the current state within the state register. The state update circuit executes a state update function on the content of the state register, where executing the state update function includes executing a plurality of iterative processing rounds on the content of the state register, and returning a result of each of the plurality of iterative processing rounds to the state register. The execution unit stores the content of the state register to the register file as an updated state of the message after completion of an iterative processing round of all of the plurality of iterative processing rounds.

Systems and methods related to vector mask buffers in a vector instruction execution pipeline are disclosed herein. The vector instruction execution pipeline may include several lanes. Each lane may include a vector register file, a vector mask buffer, and a functional processing unit. The vector register file may store operand data and the vector mask buffer may store a vector mask associated with the operand data. In a lane, the operand data may be read from the register file into a functional processing unit, and the vector mask may be read from the vector mask buffer to the functional processing unit. The functional processing unit may process the operand data based on the vector mask. The lane-specific vector mask buffers improve the efficiency of the vector instruction execution pipeline by storing the vector masks proximate to where the vector masks will be used.

The invention provides a scalar processor, a high-performance processor and electronic equipment, and the scalar processor comprises an instruction fetching unit, a register renaming unit, an operation reservation stack unit, a storage reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit and a register file unit, a special vector register file unit; wherein the synchronization unit is used for synchronizing the scalar processor and the vector processor. According to the scalar processor provided by the invention, the synchronization of the scalar processor and the vector processor is realized through the synchronization unit, so that an instruction is efficiently executed.

The invention provides a cross-domain large file transmission method based on a distributed soft bus, and belongs to the technical field of communication transmission. The method comprises the following steps: finishing networking of different local area networks; on a first local area network side, a large file to be transmitted is fragmented according to a preset fixed size, so that a plurality of file fragments are generated; registering file fragment information on the soft bus, wherein the file fragment information comprises the serial number, the size and the check code of the file fragment; according to file fragment information registered by the soft bus, dynamically sending file fragments through a soft bus transmission process; on a second local area network side, receiving the file fragments which arrive successively through a soft bus transmission process; the serial number and the check code of the file fragment are checked through the soft bus; and after all the file fragments are received, carrying out file recombination according to the file fragment information, and recovering the original large file. According to the invention, the efficiency, stability and safety of cross-domain transmission can be improved.

A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

The invention provides a completeness K-SAT solver based on an incremental updating technology, and the solver comprises an incremental updater, and the incremental updater comprises an assignment mask unit which is used for adjusting the current assignment of a target character based on the current working mode of the assignment mask unit, and obtaining the adjusted assignment information; the register file is used for storing historical assignment information of characters contained in each clause in the Boolean formula; one end of the updating logic unit is connected with the assignment mask unit, the other end of the updating logic unit is connected with the register file, and the updating logic unit is used for determining character assignment information based on the historical assignment information and the adjusted assignment information; and the assignment mask unit is also used for outputting the character assignment information, so that the solver carries out complete K-SAT solving based on the character assignment information. According to the method, efficient storage and management of historical assignment information are realized on the hardware level, and hardware resource consumption and solution delay caused by frequent storage and backtracking in completeness analysis are effectively reduced.

The invention discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises a control unit which is used for receiving and decoding a machine instruction, managing the execution processes of internal and external circulation and microinstruction circulation, and generating a control signal of each stage of a microinstruction assembly line; the microinstruction buffer area is used for storing a microinstruction sequence pre-generated by the neural network compiler; the register file is used for storing source operands and results of ALU operation; each entry of the register file is composed of a valid bit, a tag bit and a data bit; the ALU computing core adopts an SIMD (Single Instruction Multiple Data) architecture and comprises a plurality of paths of parallel arithmetic logic function units; the Load / Store unit is used for processing data exchange between a register file and a local buffer area; and the data selection interface is used for selecting a data source or a target buffer area according to the storage tag field of the microinstruction. According to the method, the high efficiency and the flexibility of the ALU in the neural network hardware accelerator can be effectively considered.

A memory device includes a first scalar register file storing a first input fragment, a second scalar register file storing a second input fragment, an arithmetic logic unit (ALU), and a control circuit. The control circuit is configured to perform, using the ALU, a first operation between the first input fragment and a first weight fragment based on a first operation command received from a host, and to perform, using the ALU, a second operation between the second input fragment and a second weight fragment based on a second operation command received from the host.

A processor includes a plurality of register sets of a register file, and a plurality sets of functional units which are coupled by sets of dedicated read and write buses to allow parallel execution of instruction. The register sets and functional units are organized as odd and even sets. Shared buses may also be employed. The processor may also include a time counter and a time-resource matrix and provides a method for statically dispatching instructions.