462results about "Microcontrol arrangements" patented technology

Various embodiments of the present invention provide a mobile computing device that operates multiple, co-existing and independent operating system environments on a common kernel. A booting process for initiating a multiple operating system environment is also provided. Additionally, various embodiments of the present invention include processes for managing a switch between one operating system environment to a second operating system environment.

An object of this invention is to easily identify an image file transferred from an image input apparatus and saved in an image file management apparatus. In an image file management method of saving an image file transferred from an image input apparatus in a folder created in accordance with the photographing date information of the image file, when transferred image files include one kind of photographing date, one kind of folder to save the image files is displayed on a screen as a current folder. When a plurality of kinds of photographing dates are present, a folder of an upper hierarchy which includes a plurality of folders created in correspondence with the plurality of kinds of photographing dates is displayed on the screen as the current folder.

A method and apparatus for configuring a microcontroller. An XML description of the microcontroller's hardware resources may be accessed. A user may select from available hardware resources and pre-defined user modules to select a configuration. Configuration information, which may include register bit patterns and microprocessor instructions, may be automatically generated. Additionally, application programming interface calls and structure, as well as interrupt vector tables may be automatically generated. Embodiments of the present invention provide improved ease of use and the ability to manage greater complexity in the configuration of configurable microcontrollers.

A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical partition. In other words, the resource and partition manager supports virtual interrupts in a logically partitioned computer system that may include share processors with no changes to a logical partition's operating system. A set of virtual interrupt registers is created for each virtual processor in the system. The resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the point of view of the operating system, the interrupt processing when the operating system is running in a logical partition that may contain shared processors and virtual interrupts is no different that the interrupt processing when the operating system is running in computer system that only contains dedicated processor partitions.

A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.

A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor's cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a composite core configuration for the microprocessor. The composite core configuration may reveal the number of enabled cores, identify the enabled cores, reveal a hierarchical coordination system of the multi-core processor, such as a nodal map of the cores for certain inter-core communication processes or restricted activities, identify various domains and domain masters within such a system, and/or identify resources, such as voltage sources, clock sources, and caches, shared by various domains of the microprocessor. The composite core configuration may be used for power state management, reconfiguration, and other purposes.

A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.

In a network-on-chip (NoC) system, multiple data messages may be transferred among modules of the system. Power consumption due to the transfer of the messages may affect a cost and overall performance of the system. A described technique provides a way to reduce a volume of data transferred in the NoC system by exploiting redundancy of data messages. Thus, if a data message to be sent from a source in the NoC includes so-called “zero” bytes that are bytes including only bits set to “0,” such zero bytes may not be transmitted in the NoC. Information on whether each byte of the data message is a zero byte may be recorded in a storage such as a data structure. This information, together with non-zero bytes of the data message, may form a compressed version of the data message. The information may then be used to uncompress the compressed data message at a destination.

The invention provides a device for executing reverse training of an artificial neural network. The device comprises an instruction buffer memory unit, a controller unit, a direct memory accessing unit, an H-tree module, a main operation module and a plurality of auxiliary operation modules. The device can realize reverse training of a multilayer artificial neural network. For each layer, weighted summation is performed on an input gradient vector and an output gradient vector of the layer is calculated. An input gradient vector of a next layer can be obtained through multiplying the output gradient vector by a derivative value of an excited function in forward operation. The gradient of the weight at this layer is obtained through multiplying the input gradient vector by an input neuron in forward operation. Then the weight of this layer can be updated according to the gradient of the weight at this layer.

A method and apparatus for increasing a processing speed using a quantum coprocessor are provided. The method includes receiving a command and data for performing a predetermined task, converting the command and the data into a signal having a format that the quantum coprocessor can receive if the command requests a quantum computation, sending the signal to the quantum coprocessor, receiving a processing result from the quantum coprocessor, and storing the processing result as a result of the command.

A multi-buffering apparatus in a random number generator. A microprocessor includes a random number generator that employs multiple buffers for buffering random data bytes generated by the generator. The apparatus maintains a first selector for selecting one of the buffers as the current buffer for filling with generated bytes. When the current fill buffer becomes full, the apparatus updates the first selector to a different buffer and continues the process until all buffers are full. The apparatus maintains a second selector for selecting one of the buffers as the current buffer for supplying random data bytes to an application. When the current supply buffer becomes empty, the apparatus updates the second selector to a different buffer and continues the process until all buffers are empty. The apparatus can concurrently fill the buffer selected by the fill selector and supply data from the buffer selected by the supply selector.

Disclosed are an ECU update method and apparatus of an AUTOSAR-based system. In the ECU update method, an MCAL driver layer receives ECU update data, and an ECAL driver layer receives the ECU update data from the MCAL driver layer and directly transfers the ECU update data to ECU update software. Therefore, the ECU update method minimizes unnecessary operations in updating an ECU while performing an operation conforming to the AUTOSAR standard, thus quickly updating the ECU.

One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream relating to the digital serial interface. A configuration register is maintained either by one of the plurality of processors or by each of the processors to arbitrate access to the individual time slot registers. Another aspect of the invention allows one or more processors to efficiently access and/or write more bits to a resource such as a time slot register than the width of the processor's respective data bus allows. Extra bits registers are maintained for at least one of the read and write direction data busses. The extra bits correspond to the least significant bits conventionally ignored in changing from a data bus of one width to a data bus of a narrower width. The extra bits in the write direction are accessed, e.g., by a write to a write direction extra bits register addressable through a specific input/output (I/O) location. The extra bits are tacked on to a subsequent write cycle in the digital serial interface, e.g., in the AC '97 link, to write an excess length data word. In the read direction, each read cycle places excess bits in a read direction extra bits register for reading in a subsequent read cycle. Another aspect of the invention provides an automatic status register which provides, e.g., automatic creation of a TAG Phase in time slot 0 of an AC '97 link using, e.g., a write enable signal to various resources in the digital serial interface, e.g., write enable signals to time slot registers.

The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively loads the memory operand into the microprocessor from the memory location, and a second distinct execution unit also receives the first microinstruction and responsively calculates the destination address of the memory location.

A method and device for controlling commands used for a flash memory are provided. The method includes, substantially reducing usage of a central processing unit (CPU) and a bus, when controlling the flash memory, by receiving information on at least one command currently stored in a system memory, receiving a command represented by the received information from the system memory, and generating an interrupt representing that all the commands are received, when receiving of substantially all the commands represented by the received information is completed.

A method of developing an application for deployment on a computing system. The computing system includes a processor and a reconfigurable logic in communication with the processor for configuration thereby. The method includes programming the processor with hardware-neutral instructions in a high-level software programming language. The instructions are representative of an application configured to execute at least partially on the reconfigurable logic. The method further includes instantiating elements from a library of elements compatible with the high-level programming language; and constructing programmatically a generic data graph representative of the application to be mapped at least partially onto the reconfigurable logic. The generic data graph is expressed as streams of records flowing between operators. A computing system is also disclosed. By presenting an instruction level streaming data processing model that expresses an application as operators and data flows, the invention provide several advantages such as design portability.

A VLIW processor includes a plurality of containers holding a plurality of sub-instructions in a VLIW instruction, an exchanging portion exchanging the plurality of sub-instructions held in the plurality of containers and inputting the instructions to the plurality of containers, a plurality of decoders decoding the sub-instructions held in the plurality of containers, and a plurality of processing units executing the sub-instructions decoded by the plurality of decoders. Since the exchanging portion exchanges a plurality of sub-instructions held in the plurality of containers and inputs the instructions to the plurality of containers, a compressed code can be executed in such an execution sequence that is taken prior to compression.

A secure element includes a boot program comprises instructions for the execution a startup step to determine if a non-volatile memory stores an active operating system, and, in the affirmative, to launch execution of the operating system, an authentication step of a updater device, as a function of first authentication data determined by a secure element and second authentication data received from the updater device, and, in response to the authentication step, a storage step of a new operating system received from the update, device in the non-volatile memory and an activation step of the new operating system, when said instructions are executed by a microprocessor.