104results about "Microcontrol arrangements" patented technology

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

A method of utilizing 3-level wHCSs created in the first generation to accommodate 3-level conveyer-integrated workgroups in a production facility to make these workgroups work collaboratively as one Task crew-entity is disclosed. By installing the 3-level 3-link-typed TeamProcessors in a 3-level wHCS with Task feedback-control operation-oriented OSs, Task operation programs and Task-operation and management libraries, a 3-level Task operation workgroup-computing Entity-oriented system, can be established to support the Task crew-entity as a whole and provide fine-grained-proactive closed-loop-problem-solving (PS) operations for external users, collaborators and supervisors in a real-time concurrent and secure manner, abiding by the self-improving solution-domain PS-principle.

The application discloses an online upgrading method of a multi-core microcontroller starting guide program, and the PC pointer is pointed to the RAM before erasing and writing the FLASH, and the B core is put to sleep and waits for the instruction; when the A core has an upgrading request, the B core receives the IPC interrupt request, the PC pointer jumps to the storage area of the interrupt vector table, the corresponding IPC interrupt service function address is searched, the corresponding upgrading service processing is executed, the PC pointer jumps back to the RAM after the execution is completed, the PC pointer is prevented from pointing to the invalid address, and thus the B core is prevented from abnormally stopping and the starting guide program upgrading operation is successfully completed.

A method may include identifying a time window of a procedure. The method may also include obtaining operational information of the time window. The operational information may include a limit of pulse repetition frequency (PRF) acceleration and a plurality of preliminary radio frequency (RF) PRFs. The method may also include determining a plurality of updated RF PRFs by updating the plurality of preliminary RF PRFs. A rate of variation between any two adjacent updated RF PRFs may be less than or equal to the limit of PRF acceleration. The method may also include causing an RF source to generate electromagnetic waves at the plurality of updated RF PRFs in the time window.

The application provides a splitting implementation method of a RISC-V vector cryptography instruction, which splits a message scheduling instruction into a plurality of micro-instructions for execution on a processor with a vector data path bit width of 128 bits according to a preset splitting rule in an instruction decoding stage, the splitting rule comprising: obtaining a message scheduling instruction in a SHA-512 algorithm, the message scheduling instruction being used to expand an input message block into a required message sequence; splitting the message scheduling instruction into a 0th type micro-instruction for processing a transformation path of sig0 and a 1st type micro-instruction for processing a transformation path of sig1 according to a calculation type; and the method does not introduce additional storage data space, and can reduce the area overhead of the processor for implementing the instruction while maintaining the unit data path operation throughput.

The present invention describes how a workgroup expert system can be established to mimic a real world task-expert and possess the equal four expert-Human-Intelligent (expert-HI) Problem-Solving (PS) competencies, including: 1) real-time concurrent workgroup-AI PS-processing, 2) real-time semantic workgroup-AI PS-transactions, 3) real-time task-domain workgroup-AI PS-collaborations and 4) real-time fine-grained adaptive workgroup-AI PS-services, based on multi-node workgroup architectures with derived workgroup-software methods and developed workgroup-system disciplines. Therefore, according to the Turing Test, the workgroup expert-task system should be deemed "Strong-AI-PS competent" for solving any task that is handled by one task expert with the help of functional processors, while all the current nodes-service-infrastructures with four node-AI-PS competencies can only mimic a group of real world functional processors with pre-developed logic-modelled processor-Human-Intelligent (processor-HI) PS-competencies for solving a pre-defined / specific multi-function-modelled task-oriented problem and should be deemed "Weak-AI-PS competent".

The invention discloses a speculative fusion design structure supporting discontinuous microcodes. The speculative fusion design structure is composed of a fusion predictor, a microcode queue, a reservation station and a fusion historical queue. The invention further discloses a speculation fusion optimization method supporting the discontinuous microcodes, which comprises the following steps of: S1, accessing the fusion predictor, acquiring fusion information of the corresponding microcodes, and storing the hit corresponding microcodes and the fusion information carried by the microcodes into a microcode queue; s2, after the microcodes and fusion information carried by the microcodes are stored in a microcode queue, internal correlation check and deadlock check of the microcodes are carried out; and S3, checking the correctness of microcode fusion in a submission stage after microcode fusion. According to the method, effective detection can be carried out during non-continuous microcode fusion, the problem of execution conflicts generated after non-continuous microcode fusion is avoided, the confidence degree of the prediction path is dynamically monitored, and the prefetching range and the prefetching accuracy are both considered.

The invention relates to a method of controlling a device (104) of a vehicle (102) in order to modify a state of the vehicle (102), of the type comprising, for each problem (P) in a domain (D), the domain (D) defining possible actions of the device (104) modifying the state of the vehicle (102) and the problem (P) indicating a starting state of the vehicle (102) and an arrival state of the vehicle (102): - a search, by a planning software (110) installed on an embedded computer system (108) in the vehicle (102), for a solution (S) to the problem (P), the solution (S) listing actions of the domain (D) to go from the starting state to the arrival state; - an evaluation, by a validator software (116) installed on the embedded computer system (108), of the solution (S);and - if the solution (S) is validated by the validator software (116), a transmission of the solution (S) to a control system (106) of the device (104) so ​​that the device successively performs the actions listed in the solution (S). The validator software (116) is first obtained by a translation, by a translator software (114) executed by a computer system (114) external to the vehicle (102), of the domain (D) so that the validator software (116) is dedicated to the domain (D), then installed on the embedded computer system (108). Figure for the abbreviation: Fig. 1;

Systems and methods for cloud-based hybrid service mesh in microservice architecture are disclosed. A method for selecting a microservice in a cloud-based hybrid mesh microservice architecture can include: (1) receiving, at a hybrid service mesh repository in a first microservice instance, a request for a second microservice, wherein the hybrid service mesh repository includes microservice information for a plurality of microservice instances, the microservice information including an identification of each microservice instance, a location of each microservice instance, and a status of each microservice instance; (2) identifying, by the hybrid service mesh repository, a number of microservice instances for the microservice and a location of each microservice instance; (3) selecting, by the hybrid service mesh repository, one of the plurality of microservice instances; and (4) invoking, by the hybrid service mesh repository, the selected microservice instance.

The embodiment of the invention provides a universal verification component, a verification platform and a related method and equipment, and the universal verification component is applied to verification of a to-be-tested design compatible with an instruction set and comprises an instruction verification component and a micro instruction verification component, the instruction verification component is used for receiving an instruction sequence, generating an instruction decoding microinstruction entry sequence based on the instruction sequence, and providing the instruction decoding microinstruction entry sequence for the microinstruction verification component; the instruction sequence is generated based on an instruction set compatible with a to-be-tested design; the microinstruction verification assembly is used for receiving the instruction decoding microinstruction entry sequence and the test case microinstruction entry sequence to form a mixed microinstruction sequence, and generating test excitation based on the mixed microinstruction sequence; the test case microinstruction entry sequence is generated based on the test case; the test case is defined through the verification scene. According to the universal verification assembly provided by the embodiment of the invention, the coverage rate of each instruction in the verification process of the to-be-tested design compatible with the instruction set is improved.

The invention provides a random instruction sequence generation method, a random instruction sequence generator and a random instruction sequence verification system. N instances are created according to microinstruction quantity parameters in a target test case; determining an instruction slot identifier and a target instruction library corresponding to each instance according to the number of instruction slots; determining a matching instruction of the instance according to the target instruction library; performing register allocation according to the matching instruction of each instance, and determining information of each register in the microinstruction corresponding to the instance to obtain a corresponding assembly instruction; and generating an assembly instruction file according to the sorting number corresponding to each instance and all the assembly instructions, wherein the assembly instruction file comprises a random instruction sequence formed by the assembly instructions according to the sorting numbers corresponding to the instances and an instruction slot identifier corresponding to each assembly instruction. A random instruction sequence matched with the processor of the ultra-long instruction word framework can be generated, various test scenes can be simulated and completed, and the method is used for verifying the processor of the ultra-long instruction word framework.

The present disclosure provides methods, microcontrollers, and system-on-a-chip devices for cryptographic operations. A memory address corresponding to encrypted data transmitted via a serial memory interface (SMIF) is determined by a processing device to be within a range of memory addresses corresponding to a computational key stored in a key cache. In response to determining that the memory address is within the range of memory addresses corresponding to the computational key, an exclusive-OR (XOR) operation is performed on the encrypted data and the computational key to generate plaintext corresponding to the encrypted data.

The invention discloses a command transmission method and device, a processor, a system on chip, equipment and a medium, and belongs to the technical field of computers. The method comprises the steps of generating a microcode instruction through a central processing unit according to a task attribute of a processing task; the microcode instruction is composed of an operation code field, a microcode configuration field and an operand; the microcode instruction comprises an immediate microcode or a stream microcode; sending the microcode instruction to a microcode processor in a graphics processor through a central processing unit; the microcode processor is composed of logic units in the graphics processor; and analyzing the microcode instruction through the microcode processor, and distributing the processing task to an execution unit in the graphics processor. The problem that an existing instruction generation method is high in complexity can be solved.

This invention proposes a micro-operation decomposition module, processor, and electronic device. A numbering update unit provides the current micro-operation number to an element quantity counting unit and an execution module. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and decoding information. Performing micro-operations before instruction execution avoids excessive pipeline delays caused by micro-operations, enabling rapid response to instruction changes, accurate completion of micro-operations, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

The embodiment of the invention discloses a processor core, a chip, electronic equipment and an instruction running method, relates to the technical field of semiconductors, and can effectively improve the utilization rate of a physical register in the processor core. The processor core comprises: a renaming component configured to map a logical register in a microinstruction to a physical register and then send the microinstruction to a scheduling component; wherein the computer instruction comprises a first instruction, the microinstructions obtained by decoding the first instruction comprise at least two target microinstructions, and the target microinstructions have a dependency relationship with each other; the target operands of the target microinstructions are mapped to the same physical register; the execution component is configured to execute the microinstructions under the scheduling of the scheduling component and broadcast a first composite identifier in response to the completion of execution of each target microinstruction; and the scheduling component is configured to schedule each to-be-executed target microinstruction according to the first composite identifier. The method is suitable for microinstruction scheduling.

The embodiments of the present disclosure disclose a distributed electromagnetic signal generation method, system, storage medium and program product. The method comprises: generating a continuous signal event description character stream in real time based on an electromagnetic scene simulation description file; analyzing the signal event description character stream in a frame as the minimum unit to generate a corresponding micro-instruction stream; distributing the micro-instruction stream to multiple signal processing nodes for parallel processing, and synchronously generating multiple IQ signal streams by each signal processing node; and modulating and converting the IQ signals in each IQ signal stream to generate corresponding electromagnetic signals. The method can realize efficient parallel, flexible expansion and multi-channel synchronization of the electromagnetic signal generation system through distributed analysis, scheduling and parallel signal generation.

This application provides a microprocessor and a method thereof. In one embodiment, a microprocessor includes: an instruction cache configured to receive instruction fetches including a first byte portion and a second byte portion; a side cache tag array configured to signal further processing of the second byte portion other than the first byte portion based on a hit in the side cache tag array; and a side cache data array configured to store instruction data of the second byte portion.

An electronic device and a method for managing micro-operations are provided. In an embodiment, the method includes determining, by a processing unit, whether a micro-operation corresponding to a translation instruction is stored in a translation buffer and a micro-operation cache when the processing unit executes the translation instruction; outputting, by the processing unit, a specific micro-operation to enter a system management mode when the micro-operation corresponding to the translation instruction is not stored in the translation buffer and the micro-operation cache; translating, by the processing unit, the translation instruction into the micro-operation corresponding to the translation instruction in the management mode; and storing, by the processing unit, the micro-operation corresponding to the translation instruction into the micro-operation cache.

The embodiment of the invention provides a signal storage circuit and a microcontroller system. The signal storage circuit comprises a conversion module, an OR gate, a register and a power-off isolation module, the conversion module receives the first digital control signal transmitted by the digital module, converts the first digital control signal into an analog control signal and outputs the analog control signal; the OR gate receives the analog control signal and a first signal output by the register, and outputs a comparison signal according to the analog control signal and the first signal; in a first mode, a first digital control signal and a second digital control signal are first levels, so that a comparison signal output by an OR gate is the first level, a first signal output by a register is the first level, and a power-off isolation module takes a signal value of a candidate control signal at a first signal rising edge moment as a target control signal; therefore, in a low-power-consumption mode, even if the power supply of the digital module is closed, the candidate control signal generated by the digital module can still be effectively stored and reliably transmitted to the analog module.

Disclosed are a micro-controller chip containing a multi-protocol communication interface peripheral and an operation method thereof. The micro-controller chip comprises a multi-protocol communication interface peripheral, the multi-protocol communication interface peripheral is connected to a system bus, the multi-protocol communication interface peripheral is connected with an I / O port, the multi-protocol communication interface peripheral comprises an exclusively used RISC instruction set micro-kernel, a code memory and a code program stored on the code memory and executable by the RISC instruction set micro-kernel, the code program at least comprises two bit operation instructions of 1 setting and 0 clearing, the instructions are single-cycle instructions, and when the RISC instruction set micro-kernel executes the code program, the I / O port outputs 1 or 0.

The present disclosure discloses an instruction processing device, an instruction processing method and related products, including an integrated circuit device, a board card and a computer readable storage medium. The method can be included in a combined processing device, which can include a computing device, an interface device, a processing device and a storage device. The technical solution of the present disclosure can process based on the type of instructions to be processed, which is more conducive to software personnel to directly intervene in the decoding behavior of instruction disassembly.

An apparatus and method for efficiently processing denormals on a processor. For example, one embodiment of a processor comprises: a decoder to decode instructions of a program code sequence into mircooperations (uops); a control register to store one or more bits related to denormal processing; uop morphing circuitry to generate or select a first type of FP divide or square root uop when the one or more bits indicate no possibility of denormals and to generate or select a second type of FP divide or square root uop when the one or more bits indicate a possibility of denormals; and execution circuitry to execute the first type of FP divide or square root uop to generate a result or to execute the second type of FP divide or square root uop, handling any denormals in hardware, to generate the result.

A quantum-computing control system includes a script processor, an instruction memory, an instruction fetcher, and a waveform player. The instruction memory stores a plurality of local instructions forming a local instruction set. The script processor executes a local script and transmits to the instruction fetcher a sequence of fetch commands that is based on the local script. The instruction fetcher retrieves, based on each fetch command of the sequence of fetch commands, a fetched instruction from the instruction memory. The fetched instruction belongs to the local instruction set. The instruction fetcher also transmits, to the waveform player, the fetched instruction as one of a sequence of fetched instructions. The waveform player executes the sequence of fetched instructions to generate a digital waveform. The control system may be used to implement mid-circuit (i.e., during runtime) non-sequential control flow of a quantum computer or other type of quantum-engineered system.

The invention provides a micro-operation disassembling module, a processor and electronic equipment. A number updating unit provides a current micro-operation number for an element quantity counting unit and an execution module; an element quantity counting unit determines a current microoperation element quantity according to the current microoperation number and reference information corresponding to the target vector instruction; the execution module executes the corresponding micro-operation according to the current micro-operation number, the current micro-operation element quantity and the decoding information. According to the method, the micro-dismounting operation is performed before the instruction is executed, so that the situation that the pipeline delay is excessively increased due to the micro-dismounting operation is avoided, the instruction change is quickly responded, the micro-dismounting operation is accurately completed, the instruction processing efficiency is improved, and the high-performance calculation requirement can be met.

This disclosure provides a memory access instruction processing method, apparatus, device, storage medium, and program product, relating to the field of processor technology. In some embodiments of this disclosure, when a store instruction reaches the first stage of the store instruction pipeline, the physical address of the store instruction is obtained; based on the physical address of the store instruction, a memory access instruction violation check is performed to obtain the target violation fetch instruction; the target violation fetch instruction and all instructions following the target violation fetch instruction are re-executed; this disclosure checks and processes violations of store and fetch instructions to ensure the correctness of memory access instruction execution, improve the execution efficiency of memory access instructions, and enhance the overall performance of the processor.

The invention relates to a high-resolution signal calibration circuit, the circuit generates a first periodic signal and a second periodic signal representing a clock signal according to the clock signal, a phase difference detection unit is used for determining the phase difference between the first periodic signal and the second periodic signal, and when a clock period is not reached, the stage number of a calibration delay chain is adjusted, and the calibration time is adjusted. When the phase relation represents that the phase difference is the clock period, the period delay series corresponding to the clock period can be obtained, the period delay series is the actual delay unit series corresponding to each clock period in the current environment, and an accurate numerical value is obtained; actual delay characteristics of the delay unit can be measured in real time through a calibration mechanism, and picosecond-level time delay control can be realized in combination with a multi-level delay chain structure; and a closed-loop calibration mechanism based on an actual clock period is adopted, so that delay errors caused by process deviation, power supply fluctuation, temperature change and the like can be automatically calibrated, and the accuracy of high-resolution signal delay is improved.

The invention discloses a program control instruction generation method based on large model federation prompt fine tuning, which realizes the collaborative utilization of multi-party data on the premise of protecting the data privacy of each party by constructing a multi-level conditional diffusion model federation learning architecture. The problem of rapid adaptation of new equipment is solved through a heterogeneous document-oriented hierarchical retrieval enhancement generation method, and the problems of information fragmentation and text discontinuity in the traditional RAG technology are solved by constructing an operation process knowledge graph and a multi-granularity semantic representation learning framework and adopting a continuous perception retrieval mechanism. And finally, solving a fundamental contradiction between large model probability generation and test instruction preciseness through a constraint satisfaction deterministic generation mechanism, and converting a probability generation process into a strict logical reasoning process by adopting a beam search algorithm guided by a complete deterministic constraint. By constructing a three-dimensional constraint system of grammar constraint, semantic constraint and security constraint and a multi-stage verification mechanism, each generated instruction is ensured to have uniqueness, correctness and security.