160results about "Microcontrol arrangements" patented technology

The invention discloses a tensor processing architecture based on reconfigurable calculation, a working mode of the tensor processing architecture and an FPGA (Field Programmable Gate Array) development board. The overall architecture comprises a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, an RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module and a result return network. The working modes of the overall architecture are divided into two modes: a CPU control mode and a cluster computing mode, wherein the CPU control mode is used for controlling global computing and output through a CPU during single-chip computing; the cluster calculation mode is used for being connected with an upper computer to cooperate with the upper computer to execute calculation tasks such as matrix calculation; the whole architecture is realized through an FPGA (Field Programmable Gate Array) development board, and the FPGA development board adopts Virtex UltraScale + VU13P as a main logic realization platform. Through the dynamic granularity configuration of the on-chip microcode, multiple operation modes can be realized, and the utilization rate of hardware is improved; and hardware realizes multiple configuration strategies, and the universality is high.

A pipelined decoding microarchitecture design method for RISC-V vector instructions includes the following steps: S1, extracting an instruction packet according to a PC, performing preprocessing, and writing a preprocessing result, each instruction field and preprocessed instruction information into a cache; S2, reading the cache, obtaining pre-decoding result data and recognizing each configuration instruction; S3, transmitting the pre-decoding result data to an instruction buffer, and acquiring field information, a split quantity and predicted vtype information; and splitting each instruction into multiple microoperations, and constructing a queue to store each microoperation; and S4, transmitting first, by means of the queue, each configuration instruction, performing decoding and execution, acquiring vtype information generated after execution, and when the vtype information generated after execution is identical with the predicted vtype information, controlling the number of microoperations input to multiple decoders, and transmitting a decoding result to an instruction slot.

The invention discloses a superconducting quantum measurement and control microcontroller and measurement and control system based on an extended instruction set, and relates to the technical field of quantum computing, and the superconducting quantum measurement and control microcontroller comprises a state machine which is used for controlling system operation and managing the execution sequence and state switching of instructions; the assembly line is of a four-step two-stage assembly line structure, a current instruction is sequentially subjected to instruction fetching, decoding, execution and write-back stages, instruction fetching of a next instruction is started to be executed in the write-back stage, and each instruction is completed in three clock periods; the code word transmitting instruction is used for generating a control pulse signal of the superconducting quantum bit; the time sequence control instruction is matched with the time delay module and is used for controlling a time interval in quantum bit operation; the feedback transmitting instruction is used for adjusting the state of the quantum bit in real time according to the feedback signal and supporting quantum error correction; according to the superconducting quantum measurement and control microcontroller and the measurement and control system, efficient and low-delay quantum bit control and real-time feedback are realized.

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

The utility model provides a power management system and electronic equipment. The power management system comprises a switch, a switch state detection module and a power control module, the switch state detection module is used for outputting a switch-off signal to the control module and the power supply control module when the switch is detected to be switched off, and the switch-off signal is used for indicating the control module to finish data read-write operation; and the power supply control module is used for responding to the off signal and is disconnected after a preset delay duration, so that the first power supply stops supplying power to the control module. According to the invention, the problem of data loss caused by directly cutting off a power supply through a switch can be solved.

This specification describes methods and systems for accessing attribute data in graph neural network (GNN) processing. An example system includes: a plurality of cores, each of the plurality of cores comprises a key-value fetcher and a filter, and is programmable using a software interface to support a plurality of data formats of the GNN attribute data, wherein: the key-value fetcher is programmable using the software interface to perform key-value fetching associated with accessing the GNN attribute data, and the filter of at least one of the plurality of cores is programmable using the software interface to sample node identifiers associated with accessing the GNN attribute data; and a first memory communicatively coupled with the plurality of cores, wherein the first memory is configured to store data shared by the plurality of cores.

A method of utilizing 3-level wHCSs created in the first generation to accommodate 3-level conveyer-integrated workgroups in a production facility to make these workgroups work collaboratively as one Task crew-entity is disclosed. By installing the 3-level 3-link-typed TeamProcessors in a 3-level wHCS with Task feedback-control operation-oriented OSs, Task operation programs and Task-operation and management libraries, a 3-level Task operation workgroup-computing Entity-oriented system, can be established to support the Task crew-entity as a whole and provide fine-grained-proactive closed-loop-problem-solving (PS) operations for external users, collaborators and supervisors in a real-time concurrent and secure manner, abiding by the self-improving solution-domain PS-principle.

A system including a controller and a plurality of power stages is described. The system can include a communication interface, the plurality of power stages, and a controller connected to the plurality of power stages through the communication interface. The controller can generate a data packet including a command encoding a task and an address identifying at least one power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages through the communication interface. Each power stage among the plurality of power stages can receive the data packet through the communication interface, compare the address in the data packet with an address assigned to the power stage, determine whether to perform the task based on a result of the comparison between the address in the data packet with an address assigned to the power stage.

The application discloses an online upgrading method of a multi-core microcontroller starting guide program, and the PC pointer is pointed to the RAM before erasing and writing the FLASH, and the B core is put to sleep and waits for the instruction; when the A core has an upgrading request, the B core receives the IPC interrupt request, the PC pointer jumps to the storage area of the interrupt vector table, the corresponding IPC interrupt service function address is searched, the corresponding upgrading service processing is executed, the PC pointer jumps back to the RAM after the execution is completed, the PC pointer is prevented from pointing to the invalid address, and thus the B core is prevented from abnormally stopping and the starting guide program upgrading operation is successfully completed.

The present invention discloses a tensor processing system based on reconfigurable computing, its working method, and an FPGA development board. The system includes: a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, a RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module, and a result return network. The system has two working methods: a CPU control method and a cluster computing method. The CPU control method is used to control global calculations and outputs through the CPU during single-chip computing; the cluster computing method is used to connect to a host computer and cooperate with the host computer to perform computing tasks such as matrix calculations. The system is implemented through an FPGA development board, and the FPGA development board uses Virtex UltraScale+VU13P as the main logic implementation platform. The present invention can realize multiple operation modes and improve hardware utilization through dynamic granularity configuration of on-chip microcode; the hardware implements multiple configuration strategies and is highly versatile.

A method may include identifying a time window of a procedure. The method may also include obtaining operational information of the time window. The operational information may include a limit of pulse repetition frequency (PRF) acceleration and a plurality of preliminary radio frequency (RF) PRFs. The method may also include determining a plurality of updated RF PRFs by updating the plurality of preliminary RF PRFs. A rate of variation between any two adjacent updated RF PRFs may be less than or equal to the limit of PRF acceleration. The method may also include causing an RF source to generate electromagnetic waves at the plurality of updated RF PRFs in the time window.

The application provides a splitting implementation method of a RISC-V vector cryptography instruction, which splits a message scheduling instruction into a plurality of micro-instructions for execution on a processor with a vector data path bit width of 128 bits according to a preset splitting rule in an instruction decoding stage, the splitting rule comprising: obtaining a message scheduling instruction in a SHA-512 algorithm, the message scheduling instruction being used to expand an input message block into a required message sequence; splitting the message scheduling instruction into a 0th type micro-instruction for processing a transformation path of sig0 and a 1st type micro-instruction for processing a transformation path of sig1 according to a calculation type; and the method does not introduce additional storage data space, and can reduce the area overhead of the processor for implementing the instruction while maintaining the unit data path operation throughput.

The present invention describes how a workgroup expert system can be established to mimic a real world task-expert and possess the equal four expert-Human-Intelligent (expert-HI) Problem-Solving (PS) competencies, including: 1) real-time concurrent workgroup-AI PS-processing, 2) real-time semantic workgroup-AI PS-transactions, 3) real-time task-domain workgroup-AI PS-collaborations and 4) real-time fine-grained adaptive workgroup-AI PS-services, based on multi-node workgroup architectures with derived workgroup-software methods and developed workgroup-system disciplines. Therefore, according to the Turing Test, the workgroup expert-task system should be deemed "Strong-AI-PS competent" for solving any task that is handled by one task expert with the help of functional processors, while all the current nodes-service-infrastructures with four node-AI-PS competencies can only mimic a group of real world functional processors with pre-developed logic-modelled processor-Human-Intelligent (processor-HI) PS-competencies for solving a pre-defined / specific multi-function-modelled task-oriented problem and should be deemed "Weak-AI-PS competent".

The invention discloses a speculative fusion design structure supporting discontinuous microcodes. The speculative fusion design structure is composed of a fusion predictor, a microcode queue, a reservation station and a fusion historical queue. The invention further discloses a speculation fusion optimization method supporting the discontinuous microcodes, which comprises the following steps of: S1, accessing the fusion predictor, acquiring fusion information of the corresponding microcodes, and storing the hit corresponding microcodes and the fusion information carried by the microcodes into a microcode queue; s2, after the microcodes and fusion information carried by the microcodes are stored in a microcode queue, internal correlation check and deadlock check of the microcodes are carried out; and S3, checking the correctness of microcode fusion in a submission stage after microcode fusion. According to the method, effective detection can be carried out during non-continuous microcode fusion, the problem of execution conflicts generated after non-continuous microcode fusion is avoided, the confidence degree of the prediction path is dynamically monitored, and the prefetching range and the prefetching accuracy are both considered.

An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine a plurality of addresses of packed data and fetch the packed data from a memory device based on the plurality of addresses. The packed data is stored on the memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the fetched packed data to the processor, where the output data is configured according to the predefined data structure. The memory fetch device is configured to process the packed data in a predefined order.

The invention relates to a method of controlling a device (104) of a vehicle (102) in order to modify a state of the vehicle (102), of the type comprising, for each problem (P) in a domain (D), the domain (D) defining possible actions of the device (104) modifying the state of the vehicle (102) and the problem (P) indicating a starting state of the vehicle (102) and an arrival state of the vehicle (102): - a search, by a planning software (110) installed on an embedded computer system (108) in the vehicle (102), for a solution (S) to the problem (P), the solution (S) listing actions of the domain (D) to go from the starting state to the arrival state; - an evaluation, by a validator software (116) installed on the embedded computer system (108), of the solution (S);and - if the solution (S) is validated by the validator software (116), a transmission of the solution (S) to a control system (106) of the device (104) so ​​that the device successively performs the actions listed in the solution (S). The validator software (116) is first obtained by a translation, by a translator software (114) executed by a computer system (114) external to the vehicle (102), of the domain (D) so that the validator software (116) is dedicated to the domain (D), then installed on the embedded computer system (108). Figure for the abbreviation: Fig. 1;

Systems and methods for cloud-based hybrid service mesh in microservice architecture are disclosed. A method for selecting a microservice in a cloud-based hybrid mesh microservice architecture can include: (1) receiving, at a hybrid service mesh repository in a first microservice instance, a request for a second microservice, wherein the hybrid service mesh repository includes microservice information for a plurality of microservice instances, the microservice information including an identification of each microservice instance, a location of each microservice instance, and a status of each microservice instance; (2) identifying, by the hybrid service mesh repository, a number of microservice instances for the microservice and a location of each microservice instance; (3) selecting, by the hybrid service mesh repository, one of the plurality of microservice instances; and (4) invoking, by the hybrid service mesh repository, the selected microservice instance.

The embodiment of the invention provides a universal verification component, a verification platform and a related method and equipment, and the universal verification component is applied to verification of a to-be-tested design compatible with an instruction set and comprises an instruction verification component and a micro instruction verification component, the instruction verification component is used for receiving an instruction sequence, generating an instruction decoding microinstruction entry sequence based on the instruction sequence, and providing the instruction decoding microinstruction entry sequence for the microinstruction verification component; the instruction sequence is generated based on an instruction set compatible with a to-be-tested design; the microinstruction verification assembly is used for receiving the instruction decoding microinstruction entry sequence and the test case microinstruction entry sequence to form a mixed microinstruction sequence, and generating test excitation based on the mixed microinstruction sequence; the test case microinstruction entry sequence is generated based on the test case; the test case is defined through the verification scene. According to the universal verification assembly provided by the embodiment of the invention, the coverage rate of each instruction in the verification process of the to-be-tested design compatible with the instruction set is improved.

The invention provides a random instruction sequence generation method, a random instruction sequence generator and a random instruction sequence verification system. N instances are created according to microinstruction quantity parameters in a target test case; determining an instruction slot identifier and a target instruction library corresponding to each instance according to the number of instruction slots; determining a matching instruction of the instance according to the target instruction library; performing register allocation according to the matching instruction of each instance, and determining information of each register in the microinstruction corresponding to the instance to obtain a corresponding assembly instruction; and generating an assembly instruction file according to the sorting number corresponding to each instance and all the assembly instructions, wherein the assembly instruction file comprises a random instruction sequence formed by the assembly instructions according to the sorting numbers corresponding to the instances and an instruction slot identifier corresponding to each assembly instruction. A random instruction sequence matched with the processor of the ultra-long instruction word framework can be generated, various test scenes can be simulated and completed, and the method is used for verifying the processor of the ultra-long instruction word framework.

The present invention discloses a method and system for implementing a distributed lock based on Redis, belonging to the technical field of Java under the microservice architecture. The technical problem to be solved by the present invention is how to handle the concurrent access of data with Redis distributed locks and ensure the ultimate consistency of data. The technical solution is as follows: The method is specifically as follows: Obtain the current time in milliseconds; Request to acquire a lock from the Redis master node in sequence; The client sets the network connection and response timeout, and the response timeout is less than the expiration time of the lock; If the response timeout expires, skip this Redis master node and try the next Redis master node; The client uses the current time minus the time when the lock acquisition started to obtain the time used for lock acquisition: Only when more than half of the Redis master nodes have acquired the lock and the time used for lock acquisition is less than the lock expiration time, the lock acquisition is successful, and the true effective time of the acquired lock needs to subtract the time used for lock acquisition; When the lock acquisition fails, the client unlocks on all Redis master nodes.

The present disclosure provides methods, microcontrollers, and system-on-a-chip devices for cryptographic operations. A memory address corresponding to encrypted data transmitted via a serial memory interface (SMIF) is determined by a processing device to be within a range of memory addresses corresponding to a computational key stored in a key cache. In response to determining that the memory address is within the range of memory addresses corresponding to the computational key, an exclusive-OR (XOR) operation is performed on the encrypted data and the computational key to generate plaintext corresponding to the encrypted data.

The invention discloses a command transmission method and device, a processor, a system on chip, equipment and a medium, and belongs to the technical field of computers. The method comprises the steps of generating a microcode instruction through a central processing unit according to a task attribute of a processing task; the microcode instruction is composed of an operation code field, a microcode configuration field and an operand; the microcode instruction comprises an immediate microcode or a stream microcode; sending the microcode instruction to a microcode processor in a graphics processor through a central processing unit; the microcode processor is composed of logic units in the graphics processor; and analyzing the microcode instruction through the microcode processor, and distributing the processing task to an execution unit in the graphics processor. The problem that an existing instruction generation method is high in complexity can be solved.

This invention proposes a micro-operation decomposition module, processor, and electronic device. A numbering update unit provides the current micro-operation number to an element quantity counting unit and an execution module. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and decoding information. Performing micro-operations before instruction execution avoids excessive pipeline delays caused by micro-operations, enabling rapid response to instruction changes, accurate completion of micro-operations, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

The present invention discloses a synchronous execution method, device, storage medium and equipment. The present invention is described from the perspective of a master controller. The master controller synchronizes operation instructions to slave controllers, activates the instruction counter after receiving the correct signals fed back by all slave controllers, and accumulates the instruction count. After receiving the instruction count result of the master controller, the slave controller accumulates it independently. It can ensure that as long as the slave controller successfully receives the synchronization instruction count of the master controller once before the master controller operation is executed (that is, before the count reaches a threshold), all controllers can realize synchronous execution of operations. Compared with the existing technology, the robustness of operation synchronization execution when communication abnormality occurs between the master controller and the slave controller in a redundant environment is improved.

The embodiment of the invention discloses a processor core, a chip, electronic equipment and an instruction running method, relates to the technical field of semiconductors, and can effectively improve the utilization rate of a physical register in the processor core. The processor core comprises: a renaming component configured to map a logical register in a microinstruction to a physical register and then send the microinstruction to a scheduling component; wherein the computer instruction comprises a first instruction, the microinstructions obtained by decoding the first instruction comprise at least two target microinstructions, and the target microinstructions have a dependency relationship with each other; the target operands of the target microinstructions are mapped to the same physical register; the execution component is configured to execute the microinstructions under the scheduling of the scheduling component and broadcast a first composite identifier in response to the completion of execution of each target microinstruction; and the scheduling component is configured to schedule each to-be-executed target microinstruction according to the first composite identifier. The method is suitable for microinstruction scheduling.

The invention provides an electronic device and an updating method for the electronic device. The electronic device comprises a processor, a display unit, a memory circuit and a time schedule controller. When an update command is obtained, the processor converts the update code into code display data. The memory circuit stores code data. The timing controller operates based on the code data. When an update command is obtained, the timing controller generates a timing corresponding to the code display data. The display unit displays an image corresponding to the code display data in a first specific display area using a timing of the code display data. The time schedule controller obtains code display data corresponding to the first specific display area according to the update command, converts the code display data back to the update code, and updates the code data of the memory circuit by using the update code.

The embodiments of the present disclosure disclose a distributed electromagnetic signal generation method, system, storage medium and program product. The method comprises: generating a continuous signal event description character stream in real time based on an electromagnetic scene simulation description file; analyzing the signal event description character stream in a frame as the minimum unit to generate a corresponding micro-instruction stream; distributing the micro-instruction stream to multiple signal processing nodes for parallel processing, and synchronously generating multiple IQ signal streams by each signal processing node; and modulating and converting the IQ signals in each IQ signal stream to generate corresponding electromagnetic signals. The method can realize efficient parallel, flexible expansion and multi-channel synchronization of the electromagnetic signal generation system through distributed analysis, scheduling and parallel signal generation.

This application provides a microprocessor and a method thereof. In one embodiment, a microprocessor includes: an instruction cache configured to receive instruction fetches including a first byte portion and a second byte portion; a side cache tag array configured to signal further processing of the second byte portion other than the first byte portion based on a hit in the side cache tag array; and a side cache data array configured to store instruction data of the second byte portion.