19results about "Microcontrol arrangements" patented technology

The application provides a splitting implementation method of a RISC-V vector cryptography instruction, which splits a message scheduling instruction into a plurality of micro-instructions for execution on a processor with a vector data path bit width of 128 bits according to a preset splitting rule in an instruction decoding stage, the splitting rule comprising: obtaining a message scheduling instruction in a SHA-512 algorithm, the message scheduling instruction being used to expand an input message block into a required message sequence; splitting the message scheduling instruction into a 0th type micro-instruction for processing a transformation path of sig0 and a 1st type micro-instruction for processing a transformation path of sig1 according to a calculation type; and the method does not introduce additional storage data space, and can reduce the area overhead of the processor for implementing the instruction while maintaining the unit data path operation throughput.

Systems and methods for cloud-based hybrid service mesh in microservice architecture are disclosed. A method for selecting a microservice in a cloud-based hybrid mesh microservice architecture can include: (1) receiving, at a hybrid service mesh repository in a first microservice instance, a request for a second microservice, wherein the hybrid service mesh repository includes microservice information for a plurality of microservice instances, the microservice information including an identification of each microservice instance, a location of each microservice instance, and a status of each microservice instance; (2) identifying, by the hybrid service mesh repository, a number of microservice instances for the microservice and a location of each microservice instance; (3) selecting, by the hybrid service mesh repository, one of the plurality of microservice instances; and (4) invoking, by the hybrid service mesh repository, the selected microservice instance.

The present disclosure provides methods, microcontrollers, and system-on-a-chip devices for cryptographic operations. A memory address corresponding to encrypted data transmitted via a serial memory interface (SMIF) is determined by a processing device to be within a range of memory addresses corresponding to a computational key stored in a key cache. In response to determining that the memory address is within the range of memory addresses corresponding to the computational key, an exclusive-OR (XOR) operation is performed on the encrypted data and the computational key to generate plaintext corresponding to the encrypted data.

The embodiments of the present disclosure disclose a distributed electromagnetic signal generation method, system, storage medium and program product. The method comprises: generating a continuous signal event description character stream in real time based on an electromagnetic scene simulation description file; analyzing the signal event description character stream in a frame as the minimum unit to generate a corresponding micro-instruction stream; distributing the micro-instruction stream to multiple signal processing nodes for parallel processing, and synchronously generating multiple IQ signal streams by each signal processing node; and modulating and converting the IQ signals in each IQ signal stream to generate corresponding electromagnetic signals. The method can realize efficient parallel, flexible expansion and multi-channel synchronization of the electromagnetic signal generation system through distributed analysis, scheduling and parallel signal generation.

The present disclosure discloses an instruction processing device, an instruction processing method and related products, including an integrated circuit device, a board card and a computer readable storage medium. The method can be included in a combined processing device, which can include a computing device, an interface device, a processing device and a storage device. The technical solution of the present disclosure can process based on the type of instructions to be processed, which is more conducive to software personnel to directly intervene in the decoding behavior of instruction disassembly.

An apparatus and method for efficiently processing denormals on a processor. For example, one embodiment of a processor comprises: a decoder to decode instructions of a program code sequence into mircooperations (uops); a control register to store one or more bits related to denormal processing; uop morphing circuitry to generate or select a first type of FP divide or square root uop when the one or more bits indicate no possibility of denormals and to generate or select a second type of FP divide or square root uop when the one or more bits indicate a possibility of denormals; and execution circuitry to execute the first type of FP divide or square root uop to generate a result or to execute the second type of FP divide or square root uop, handling any denormals in hardware, to generate the result.

This disclosure provides a memory access instruction processing method, apparatus, device, storage medium, and program product, relating to the field of processor technology. In some embodiments of this disclosure, when a store instruction reaches the first stage of the store instruction pipeline, the physical address of the store instruction is obtained; based on the physical address of the store instruction, a memory access instruction violation check is performed to obtain the target violation fetch instruction; the target violation fetch instruction and all instructions following the target violation fetch instruction are re-executed; this disclosure checks and processes violations of store and fetch instructions to ensure the correctness of memory access instruction execution, improve the execution efficiency of memory access instructions, and enhance the overall performance of the processor.

The invention discloses a program control instruction generation method based on large model federation prompt fine tuning, which realizes the collaborative utilization of multi-party data on the premise of protecting the data privacy of each party by constructing a multi-level conditional diffusion model federation learning architecture. The problem of rapid adaptation of new equipment is solved through a heterogeneous document-oriented hierarchical retrieval enhancement generation method, and the problems of information fragmentation and text discontinuity in the traditional RAG technology are solved by constructing an operation process knowledge graph and a multi-granularity semantic representation learning framework and adopting a continuous perception retrieval mechanism. And finally, solving a fundamental contradiction between large model probability generation and test instruction preciseness through a constraint satisfaction deterministic generation mechanism, and converting a probability generation process into a strict logical reasoning process by adopting a beam search algorithm guided by a complete deterministic constraint. By constructing a three-dimensional constraint system of grammar constraint, semantic constraint and security constraint and a multi-stage verification mechanism, each generated instruction is ensured to have uniqueness, correctness and security.

A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

Methods, apparatus, and computer programs are disclosed to identify a restart instruction for multiple load microoperations. In one embodiment, a method comprises: receiving a request indicating that a load microoperation identified by a microoperation identifier needs to be restarted; looking up a load recovery data structure to identify a matching entry that indicates an instruction to restart for the load microoperation, the matching entry providing the instruction to restart for a range of microoperation identifiers mapped to a plurality of microoperations including the load microoperation, the matching entry indicating a restart microoperation identifier that is mapped to a first microoperation of the instruction to restart; and fetching the instruction to execute on the computer processor based on the matching entry being identified in the load recovery data structure.

The application discloses a digital controller of an analog comparator, comprising an ACMP register group, a channel switching counter, a filter counter, a polling channel counter and a positive and negative terminal output channel selection module. Four working modes of single continuous mode, single sequence mode, intermittent sequence mode and continuous sequence mode are realized, the channel selection module is used for selecting the channel for comparison, the channel switching time can be freely controlled, and the comparison results of all the polling channels can be updated in real time. New polling channels can be configured in the comparison process, and the user can flexibly define the comparison order of the channels. The technical scheme of the application can realize the working modes of the analog comparator in multiple modes, is flexible in configuration, suitable for multiple working occasions and wide in application.

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

The application provides a micro control unit reset filter circuit, a method, a device and a medium, and the system comprises a first-stage filter group, a first flip-flop, a second flip-flop, a third flip-flop and a fourth flip-flop, the first flip-flop and the third flip-flop are electrically connected to a high-level signal, the output end of the first flip-flop is electrically connected to the input end of the second flip-flop, wherein the reset end of the first flip-flop and the reset end of the second flip-flop are directly electrically connected to an original reset signal, the reset end of the third flip-flop and the reset end of the fourth flip-flop are electrically connected to the original reset signal through a first inverter, a AND gate, the first input end of the AND gate is electrically connected to the second flip-flop through a second inverter, the second input end of the AND gate is directly electrically connected to the fourth flip-flop, and the output end of the AND gate is used for outputting a first reset signal. According to the technical scheme of the embodiment of the application, the inaccurate threshold constant is replaced by the accurate digital timing control, and the anti-interference ability and the reliability of the micro control unit can be improved.

Container scaling and migration for container-based microservices are provided. A first set of features is extracted from each respective microservice of a plurality of different microservices. A number of containers required by each respective microservice of the plurality of different microservices at a future point in time is predicted using a trained prediction model and the first set of features extracted from each respective microservice. A scale tag and a scale value are assigned to each respective microservice of the plurality of different microservices based on a predicted change in a current number of containers corresponding to each respective microservice in accordance with the number of containers required by each respective microservice at the future point in time. The current number of containers corresponding to each respective microservice of the plurality of different microservices is adjusted based on the scale tag and the scale value assigned to each respective microservice.

The application relates to an interrupt or exception event processing method, a processor and an electronic device. The method comprises the following steps: after an interrupt or exception event is detected by a write-back unit, flushing a pipeline and triggering a hardware stack operation; based on the stack operation, a microinstruction splitting unit splits a stack microinstruction sequence of the hardware stack to obtain a register stack switching instruction while a fetch unit sequentially obtains to-be-processed instructions; the microinstruction splitting unit switches a first register stack currently used to a second register stack based on the register stack switching instruction; and sends to-be-executed instructions to an execution unit; the execution unit executes the to-be-executed instructions to perform interrupt or exception processing, and stores intermediate data and / or result data generated after execution to the second register stack. The first register stack and the second register stack are physically isolated in the processor, and a microinstruction splitting mechanism automatically triggered by hardware is combined, so that an interrupt or exception processing flow is significantly optimized.

The present disclosure relates to a method of managing NOP instructions in a microcontroller, the method comprising replicating all jump instructions that generate NOP instructions to form a new instruction set; inserting an internal NOP instruction into each of the jump instructions; running the subsequent instructions of the new instruction set when the jump instructions are run; and running the internal NOP instruction when the running of the subsequent instructions is skipped.

The present application provides a control circuit, a microcontroller and a control method. The control circuit includes a detection circuit, a sampling circuit and an operation circuit. The detection circuit collects an external information to generate a detection signal. The sampling circuit has a sampling frequency and samples the detection signal to generate a sampling signal. The operation circuit inputs the sampling signal into an inference model to generate an inference result, and judges whether a preset condition is satisfied according to the inference result. When the preset condition is satisfied, the operation circuit adjusts the sampling frequency from a first preset value to a second preset value. When the preset condition is not satisfied, the operation circuit maintains the sampling frequency at the first preset value.

The present disclosure provides a function configuration method of an actuator connected to an end mechanism for driving the end mechanism to move, the function configuration method comprising: constructing an extended function package, the extended function package comprising a physical model of the end mechanism, user configuration parameters and an extended function algorithm, the extended function algorithm being executable to realize an extended function of the actuator; receiving the extended function package by the actuator, and parsing the physical model, the user configuration parameters and the extended function algorithm in the extended function package by a runtime environment in the actuator; and calling interface information of the actuator according to the physical model and the user configuration parameters by the runtime environment, executing logic of the extended function algorithm to realize the extended function of the actuator corresponding to the extended function algorithm.