225results about "Microcontrol arrangements" patented technology

The invention provides a memory access instruction processing method and a processor, and relates to the technical field of data processing, and the method comprises the following steps: splitting a target vector memory access instruction into a plurality of target vector memory access micro-operations based on a memory access width, combining the target scalar memory access instruction with at least one unexecuted scalar memory access instruction into a target scalar memory access micro-operation; executing each target vector memory access micro-operation, and / or executing a target scalar memory access micro-operation; the memory access width is determined based on a number of data cache banks in a data cache in the processor and a bit width of the data cache banks. According to the memory access instruction processing method and the processor provided by the invention, resources can be more reasonably allocated for vector memory access and scalar memory access during data memory access through splitting of the vector memory access instruction and merging of the scalar memory access instruction, and maximum resource sharing of the vector memory access and the scalar memory access is realized.

The embodiment of the invention provides a computing chip and an instruction processing method, and relates to the technical field of integrated circuits, the computing chip adopts a superscalar processor architecture, and comprises an instruction processing unit and a plurality of registers coupled with the instruction processing unit, the plurality of registers comprise a general register and a plurality of private registers respectively coupled with the general register; the general register is used for storing an execution result of a microinstruction which is executed before the jump instruction and is referenced by the microinstruction executed after the jump instruction in a plurality of microinstructions of the calculation task; each private register in the plurality of private registers is used for storing an execution result of any microinstruction in the plurality of microinstructions; the instruction processing unit is used for analyzing each microinstruction in the plurality of microinstructions; and obtaining data in the register according to the analysis result to execute the microinstruction and storing an execution result to the register. According to the embodiment of the invention, the processing efficiency of the processor on the microinstruction can be improved.

The invention discloses a tensor processing architecture based on reconfigurable calculation, a working mode of the tensor processing architecture and an FPGA (Field Programmable Gate Array) development board. The overall architecture comprises a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, an RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module and a result return network. The working modes of the overall architecture are divided into two modes: a CPU control mode and a cluster computing mode, wherein the CPU control mode is used for controlling global computing and output through a CPU during single-chip computing; the cluster calculation mode is used for being connected with an upper computer to cooperate with the upper computer to execute calculation tasks such as matrix calculation; the whole architecture is realized through an FPGA (Field Programmable Gate Array) development board, and the FPGA development board adopts Virtex UltraScale + VU13P as a main logic realization platform. Through the dynamic granularity configuration of the on-chip microcode, multiple operation modes can be realized, and the utilization rate of hardware is improved; and hardware realizes multiple configuration strategies, and the universality is high.

Disclosed are techniques for macro-operation fusion. In an aspect, a method for macro-operation fusion comprises detecting that a plurality of macro-operations involving a first register is a fusible set of macro-operations comprising a first macro-operation to perform an arithmetic operation using a second register and a second macro-operation to perform the arithmetic operation using an immediate value, wherein the arithmetic operation is addition or subtraction. The method also comprises decoding the fusible set to one micro-operation that performs functions of the fusible set, and executing the one micro-operation that performs the functions of the fusible set. In some aspects, the detection, decoding, and executing steps may be performed by an instruction fetch unit, a decoder unit, and an execution unit, respectively, of a processor. In some aspects, the instruction fetch unit routes the fusible set of macro-operations to the same decoder unit from a plurality of available decoder units.

A pipelined decoding microarchitecture design method for RISC-V vector instructions includes the following steps: S1, extracting an instruction packet according to a PC, performing preprocessing, and writing a preprocessing result, each instruction field and preprocessed instruction information into a cache; S2, reading the cache, obtaining pre-decoding result data and recognizing each configuration instruction; S3, transmitting the pre-decoding result data to an instruction buffer, and acquiring field information, a split quantity and predicted vtype information; and splitting each instruction into multiple microoperations, and constructing a queue to store each microoperation; and S4, transmitting first, by means of the queue, each configuration instruction, performing decoding and execution, acquiring vtype information generated after execution, and when the vtype information generated after execution is identical with the predicted vtype information, controlling the number of microoperations input to multiple decoders, and transmitting a decoding result to an instruction slot.

Systems and methods for wireless interface sharing for Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include an OOB Microcontroller Unit (MCU) integrated into a heterogeneous computing platform and a network traffic routing controller integrated into the heterogeneous computing platform, where the network traffic routing controller is coupled to the OOB MCU and to a host processor, and where the network traffic routing controller is configured to determine whether to route a packet to the OOB MCU or to the host processor.

The invention relates to a microinstruction inter-board synchronous triggering method and a microinstruction control test system, and the method comprises the steps: receiving a synchronous clock signal sent by a communication board card, and starting the cycle counting based on the synchronous clock signal, and obtaining a clock count value; sequentially expanding each test instruction into one or more microinstructions based on the sequence of the plurality of test instructions pre-loaded to the cache; receiving a starting instruction sent by the communication board card, wherein the starting instruction comprises a starting count value; the starting count value is compared with the clock count value, when the clock count value is equal to the starting count value for the first time, operation of the microinstruction is triggered, and the problems that communication time needs to be spent and the real-time performance is poor when the microinstruction is synchronously triggered are solved.

The invention discloses a superconducting quantum measurement and control microcontroller and measurement and control system based on an extended instruction set, and relates to the technical field of quantum computing, and the superconducting quantum measurement and control microcontroller comprises a state machine which is used for controlling system operation and managing the execution sequence and state switching of instructions; the assembly line is of a four-step two-stage assembly line structure, a current instruction is sequentially subjected to instruction fetching, decoding, execution and write-back stages, instruction fetching of a next instruction is started to be executed in the write-back stage, and each instruction is completed in three clock periods; the code word transmitting instruction is used for generating a control pulse signal of the superconducting quantum bit; the time sequence control instruction is matched with the time delay module and is used for controlling a time interval in quantum bit operation; the feedback transmitting instruction is used for adjusting the state of the quantum bit in real time according to the feedback signal and supporting quantum error correction; according to the superconducting quantum measurement and control microcontroller and the measurement and control system, efficient and low-delay quantum bit control and real-time feedback are realized.

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

The disclosed system may include a processor configured to encode dependencies using an encoding scheme that reduces the number of bits required to represent one or more instructions in an instruction set in an instruction buffer represented by a dependency matrix, the dependency indicates that the child instruction represented in the dependency matrix depends on the parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependencies in a dependency matrix and dispatch an instruction in an instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix of the instruction. Various other methods, systems, and computer readable media are also disclosed.

The invention discloses a vector processor, an operation method of the vector processor and electronic equipment. The vector processor comprises a scalar core used for executing a received scalar request instruction to obtain a first instruction execution result, and sending a received vector request instruction to a vector unit; the vector unit is connected with the scalar core through the communication interface unit and used for executing the vector request instruction to obtain a second instruction execution result; and the controller is respectively connected with the scalar core and the vector unit, and is used for configuring clock domains of the scalar core and the vector unit according to the first clock frequency and the second clock frequency, and configuring power supply domains of the scalar core and the vector unit according to the first working state and the second working state. The technical problem that the processing efficiency of a processor in the related technology is low is solved.

The invention provides a microprocessing system and a program execution method, the microprocessing system comprises a microprocessor, an external random access memory and a read-only memory, and the address range of the external random access memory is overlapped with the address range of the read-only memory; wherein the microprocessor, the external random access memory and the read-only memory are connected to three groups of buses, and the three groups of buses are a control bus, an address bus and a data bus; the data bus and the address bus are respectively provided with a path switching circuit, and the path switching circuits are used for switching a program in the read-only memory to the external random access memory for execution by switching a program access path of the microprocessor. According to the technical scheme, the program reading and executing speed of the microprocessor can be improved.

The invention relates to a method, system and device for uploading data after a whole vehicle is awakened, and the method comprises the steps: collecting vehicle bus data after a microcontroller is awakened from a dormant state, and caching the vehicle bus data to a memory; after the microcontroller detects that the system-on-chip is awakened from the dormant state, the vehicle bus data in the memory are sent to the system-on-chip through a gateway, and the awakening duration of the system-on-chip is longer than that of the microcontroller. The integrity of the recorded data of the system-on-chip at the initial stage of vehicle wakeup is ensured.

The utility model provides a power management system and electronic equipment. The power management system comprises a switch, a switch state detection module and a power control module, the switch state detection module is used for outputting a switch-off signal to the control module and the power supply control module when the switch is detected to be switched off, and the switch-off signal is used for indicating the control module to finish data read-write operation; and the power supply control module is used for responding to the off signal and is disconnected after a preset delay duration, so that the first power supply stops supplying power to the control module. According to the invention, the problem of data loss caused by directly cutting off a power supply through a switch can be solved.

An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.

This specification describes methods and systems for accessing attribute data in graph neural network (GNN) processing. An example system includes: a plurality of cores, each of the plurality of cores comprises a key-value fetcher and a filter, and is programmable using a software interface to support a plurality of data formats of the GNN attribute data, wherein: the key-value fetcher is programmable using the software interface to perform key-value fetching associated with accessing the GNN attribute data, and the filter of at least one of the plurality of cores is programmable using the software interface to sample node identifiers associated with accessing the GNN attribute data; and a first memory communicatively coupled with the plurality of cores, wherein the first memory is configured to store data shared by the plurality of cores.

A method of utilizing 3-level wHCSs created in the first generation to accommodate 3-level conveyer-integrated workgroups in a production facility to make these workgroups work collaboratively as one Task crew-entity is disclosed. By installing the 3-level 3-link-typed TeamProcessors in a 3-level wHCS with Task feedback-control operation-oriented OSs, Task operation programs and Task-operation and management libraries, a 3-level Task operation workgroup-computing Entity-oriented system, can be established to support the Task crew-entity as a whole and provide fine-grained-proactive closed-loop-problem-solving (PS) operations for external users, collaborators and supervisors in a real-time concurrent and secure manner, abiding by the self-improving solution-domain PS-principle.

A system including a controller and a plurality of power stages is described. The system can include a communication interface, the plurality of power stages, and a controller connected to the plurality of power stages through the communication interface. The controller can generate a data packet including a command encoding a task and an address identifying at least one power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages through the communication interface. Each power stage among the plurality of power stages can receive the data packet through the communication interface, compare the address in the data packet with an address assigned to the power stage, determine whether to perform the task based on a result of the comparison between the address in the data packet with an address assigned to the power stage.

The application discloses an online upgrading method of a multi-core microcontroller starting guide program, and the PC pointer is pointed to the RAM before erasing and writing the FLASH, and the B core is put to sleep and waits for the instruction; when the A core has an upgrading request, the B core receives the IPC interrupt request, the PC pointer jumps to the storage area of the interrupt vector table, the corresponding IPC interrupt service function address is searched, the corresponding upgrading service processing is executed, the PC pointer jumps back to the RAM after the execution is completed, the PC pointer is prevented from pointing to the invalid address, and thus the B core is prevented from abnormally stopping and the starting guide program upgrading operation is successfully completed.

The invention provides an electronic device and a method for managing microoperation. In an embodiment, the method comprises: when a processing unit executes a translation instruction, determining, by the processing unit, whether a microoperation corresponding to the translation instruction is stored in a translation buffer and a microoperation cache; when the microoperation corresponding to the translation instruction is not stored in the translation buffer area and the microoperation cache, outputting a specific microoperation by the processing unit to enter a system management mode; translating, by the processing unit, the translation instruction into a micro-operation corresponding to the translation instruction in a management mode; and storing, by the processing unit, a microoperation corresponding to the translation instruction in a microoperation cache.

The invention provides a vibration measuring device with electricity waste estimation and quantitative emission reduction functions and a method for measuring vibration to estimate electricity waste and quantitative emission reduction. The device comprises a microprocessor and a vibration meter. The vibration meter measures vibration of a motor device to obtain a vibration value and transmits the vibration value to the microprocessor; the microprocessor calculates a plurality of vibration values to obtain a vibration root-mean-square value and calculates the vibration values to obtain a frequency domain distribution value; the microprocessor obtains a health index by using the vibration root-mean-square value; the microprocessor obtains an electricity waste percentage value by using the frequency domain distribution value and the health index; the microprocessor obtains an increased carbon emission value by using a power value of the motor device, the power waste percentage value and a power carbon emission coefficient.

The present invention discloses a tensor processing system based on reconfigurable computing, its working method, and an FPGA development board. The system includes: a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, a RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module, and a result return network. The system has two working methods: a CPU control method and a cluster computing method. The CPU control method is used to control global calculations and outputs through the CPU during single-chip computing; the cluster computing method is used to connect to a host computer and cooperate with the host computer to perform computing tasks such as matrix calculations. The system is implemented through an FPGA development board, and the FPGA development board uses Virtex UltraScale+VU13P as the main logic implementation platform. The present invention can realize multiple operation modes and improve hardware utilization through dynamic granularity configuration of on-chip microcode; the hardware implements multiple configuration strategies and is highly versatile.

A method may include identifying a time window of a procedure. The method may also include obtaining operational information of the time window. The operational information may include a limit of pulse repetition frequency (PRF) acceleration and a plurality of preliminary radio frequency (RF) PRFs. The method may also include determining a plurality of updated RF PRFs by updating the plurality of preliminary RF PRFs. A rate of variation between any two adjacent updated RF PRFs may be less than or equal to the limit of PRF acceleration. The method may also include causing an RF source to generate electromagnetic waves at the plurality of updated RF PRFs in the time window.

The invention provides a microinstruction analysis method and device, equipment and a storage medium. The method comprises the steps of obtaining a currently executed target microinstruction; converting the target microinstruction into a binary system; according to the query function, segmenting a binary target microinstruction to obtain a plurality of sub microinstructions; and according to the query function, sequentially analyzing the plurality of sub micro-instructions to obtain the meaning of the target micro-instruction, and displaying the target micro-instruction and the meaning of the target micro-instruction.

The application provides a splitting implementation method of a RISC-V vector cryptography instruction, which splits a message scheduling instruction into a plurality of micro-instructions for execution on a processor with a vector data path bit width of 128 bits according to a preset splitting rule in an instruction decoding stage, the splitting rule comprising: obtaining a message scheduling instruction in a SHA-512 algorithm, the message scheduling instruction being used to expand an input message block into a required message sequence; splitting the message scheduling instruction into a 0th type micro-instruction for processing a transformation path of sig0 and a 1st type micro-instruction for processing a transformation path of sig1 according to a calculation type; and the method does not introduce additional storage data space, and can reduce the area overhead of the processor for implementing the instruction while maintaining the unit data path operation throughput.

The present invention describes how a workgroup expert system can be established to mimic a real world task-expert and possess the equal four expert-Human-Intelligent (expert-HI) Problem-Solving (PS) competencies, including: 1) real-time concurrent workgroup-AI PS-processing, 2) real-time semantic workgroup-AI PS-transactions, 3) real-time task-domain workgroup-AI PS-collaborations and 4) real-time fine-grained adaptive workgroup-AI PS-services, based on multi-node workgroup architectures with derived workgroup-software methods and developed workgroup-system disciplines. Therefore, according to the Turing Test, the workgroup expert-task system should be deemed "Strong-AI-PS competent" for solving any task that is handled by one task expert with the help of functional processors, while all the current nodes-service-infrastructures with four node-AI-PS competencies can only mimic a group of real world functional processors with pre-developed logic-modelled processor-Human-Intelligent (processor-HI) PS-competencies for solving a pre-defined / specific multi-function-modelled task-oriented problem and should be deemed "Weak-AI-PS competent".

The invention discloses a speculative fusion design structure supporting discontinuous microcodes. The speculative fusion design structure is composed of a fusion predictor, a microcode queue, a reservation station and a fusion historical queue. The invention further discloses a speculation fusion optimization method supporting the discontinuous microcodes, which comprises the following steps of: S1, accessing the fusion predictor, acquiring fusion information of the corresponding microcodes, and storing the hit corresponding microcodes and the fusion information carried by the microcodes into a microcode queue; s2, after the microcodes and fusion information carried by the microcodes are stored in a microcode queue, internal correlation check and deadlock check of the microcodes are carried out; and S3, checking the correctness of microcode fusion in a submission stage after microcode fusion. According to the method, effective detection can be carried out during non-continuous microcode fusion, the problem of execution conflicts generated after non-continuous microcode fusion is avoided, the confidence degree of the prediction path is dynamically monitored, and the prefetching range and the prefetching accuracy are both considered.

An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine a plurality of addresses of packed data and fetch the packed data from a memory device based on the plurality of addresses. The packed data is stored on the memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the fetched packed data to the processor, where the output data is configured according to the predefined data structure. The memory fetch device is configured to process the packed data in a predefined order.